INVENTIVE

Delay Modeling with ECSM

(Effective Current Source Model)

Statistical Extensions
Tom Spyrou
Cadence Design Systems
OA Conference, April 2008

 Highest integration SoC through 2001

1st silicon success, & recognized with
DAC 2001 Gold Design Achievement
Award

ECSM used since for many highprofile designs, several that were
industry-first

4/18/2008

eDRAM

eDRAM
ISSCC2001
9.6

http://www.cadence.com/datasheets/delaycal_tp.pdf

eDRAM

eDRAM

eDRAM

Synthesized Blocks

eDRAM

eDRAM

eDRAM

Data I/O

280M transistors
21.7 x 21.3 mm2

Data I/O

Data I/O

Power

Developed by Altius ( later Simplex > Cadence Design Services) 1998

Initially a binary format (ipdb) but
now a text extension to Liberty (.lib +
ecsm)
First public ECSM announcement
was the Sony GSI-32 (ISSCC, Feb
2001)

Distribution

Sony Computer
Entertainment - GSI-32

Microprocessor Interface
Power
Distribution

ECSM History

Effective Current Source Model (ECSM)

Proven Timing, SI, Power, and Variation Modeling

Less
Pessimism
Better Silicon

First Current Source Modeling Format

Timing

Power Extensions

1000+ tapeouts at 130nm & 90nm in its 9 year history

Accurate to within 2% (SPICE)
Characterization technique is very similar to NLDM (voltage Based)

ECSM Power Extensions

Current
(mA)

Based on the tapeout proven VoltageStorm library format &

Dynamic Current
characterization
Waveform
0.6
0.58
0.42
0.4
0.38

0.1

SI Extensions
ECSM SI Extensions

Statistical Extensions

Based on the tapeout proven CeltIC cdB format

ECSM Statistical Extensions for SSTA

Collaborative effort by Cadence, Magma, Altos, Extreme DA, ARM, Sun
Microsystems in

victim

Truly Open Standard

OMC Board approves all changes

Currently support in both EDA and customer base

Only Open Standard Format!

4/18/2008

ECSM- Si2 Open Modeling

Formed in mid-2005 to address
Address modeling accuracy, consistency, security, and process
variations & characterization consistency

Member List
ARM, Cadence, Extreme DA, Freescale, IBM, Intel, LSI Logic,
Magma, Philips, Renesas, Sun Microsystems, Virage Logic, ++

Working groups
Statistical Timing, Technical Steering, ECSM Change
Management, Joint Data Model Consistency, Characterization
Data

4/18/2008

ECSM Tapeout Success Slide from 2002

1000M

200+ chips
97% 1st Silicon Success

Sony GS I-32

Sony Graphics Synthesizer I-32

Transistors (#)

DAC2001 Gold Design Achievement Award; 287.5M transistors; ISSCC2001

Sony PlayStation2 Graphics Synthesizer

Infineon Technologies Titan 19244

100M

Industry-first single-chip OC-768 (40Gb/s) SONET/SDH TDM Framer & Pointer Processor SoC; ISSCC2003

Azanda Network Devices Scimitar AZ6110

Industry-first single-chip full-duplex OC-48 Traffic Manager and ATM SAR SoC; DAC2002, ISSCC2003

TeraChip TCF 16X10

Industry-first single-chip 160Gbps switch fabric SoC; ISSCC2004; AnalogZone Product of the Year

10M

Cirrus Logic 3Ci, DVD/R

Industry-first SoCs; Innovation of the Year, Top Ten Development, ISSCC1999

Industry-first single chip OLED SVGA micro-display

Electronic Products 2001 Product-of-the-Year Award

1M
0

4/18/2008

3Ci

>30 ARM-based designs

90 nanometer chips
6

9
Volume (#, M/year)

12

15

Industry Support
VENDORS
Virage Logic
Support ECSM
Extensions

ARM/Artisan
Currently support
ECSM
Going forward releases
will support ECSM
Power & SI extensions

TSMC
Currently support
ECSM
Memory support
coming soon

CUSTOMERS
Cisco
Freescale
ATI
Cortina
Neomagic
Sandisk
Dallas Semi

4/18/2008

Ricoh
Transchip
Globespan
SuperH
Adaptec
Fujitsu
Renesas

Sony
Marvell
Fujitsu
Renesas
Sony
Marvell
Phililps

ADI
Oki
UMC
Agere
Faraday
Epson
Agilent

ECSM Specification Timeline

September 14, 2005
Si2 forms Open Modeling Coalition
SAN
FRANCISCO
Looking to emulate the success of its popular OpenAccess
March
7, 2006
Coalition
andECSM
to address
critical issues
in the characterization
andDeliverable
modeling offrom
libraries
Si2
Releases
2.0 Standard
for Design
Libraries as First
and
intellectual
(IP), the Silicon Integration Initiative (Si2) Wednesday
Open
Modelingproperty
Coalition
announced the formation of the Open Modeling Coalition (OMC).
July 24, 2006
The Silicon Integration Initiative, Inc. (Si2) has released the Effective Current Source
Si2
Releases
Power
Extensions
in ECSM 2.1
for Design
Modeling
(ECSM)
Version
2.0 specification,
theStandard
first deliverable
from Libraries;
the Open Open
ModelingCoalition
Coalition(OMC).
Continues
on Roadmap
Modeling
The OMC
Working Group which produced the standard has
AUSTIN, Texas--(BUSINESS WIRE)--July 24, 2006--The Silicon Integration Initiative (Si2) today released the Effective
representatives
from
industry
Cadence
Design
Systems,
Freescale
August
2006Modeling
Current
Source
(ECSM)
Versionleaders:
2.1 specification,
which includes
dynamic
power analysis
power extensions.
Semiconductor,
LSI
Logic,power
Magma
Design
Automation,
Silicon
Navigator,
Sunto
These extensions
allowIntel,
powersubmitted
and dynamic
grid analysis
information
to be passed
from cell
characterization
ECSM
SI
Extensions
to
Si2
design
tools
enabling
them
to
perform
accurate
power
predictions
for
nanometer
design.
The
Open
Modeling
Coalition
Microsystems,
and Virage Logic.
(OMC) working group which produced this latest version of the standard has representatives from industry leaders:
Cadence Design
Systems, Freescale Semiconductor, Intel, LSI Logic, Silicon Navigator, Sun Microsystems, and Virage
November
2006
Logic.
ECSM Statistical Extensions joint development submitted to Si2

2007
ECSM Statistical Extensions released by Open Modeling Coalition
ECSM SI Extensions released by Open Modeling Coalition

4/18/2008

ECSM Technical Overview

4/18/2008

ECSM Delay Model

Modeling Vdd Impact on Delay with ECSM

ECSM Vs SPICE (Half Adder 90nm)
4000
3500
3000

Delay
Arc

Delay (ps)

Input
Slope

Output Slope

SPICE
ECSM

Non-linear
increase in
Delay due to IR
Drop

2500
2000
1500
1000

Cload

500

Linear
Approximation

1.2

ECSM (Effective Current Source Model)

Driver modeled as a current source
I/V curve for each slope, load combination
Benefits include better accuracy for
Long chip level interconnects (buses,
clocks)
Parallel drivers (clock meshes)
Modeling of voltage impact on delay (ir
drop, dynamic voltage scaling)

1.1

4/18/2008

0.9

Voltage (V)

0.8

0.7

0.6

Example accuracy
ECSM mean <2%
1500

nldm mean <5%

1000

500

-10

-5

10

 C-effective that varies with the output

frequency

I/V curve for each slope, load

combination
Voltage-based measurement for
characterization
Easily builds on existing voltage
measurement & characterization
techniques
Voltage waveform (V/T) is converted to a
Current-Voltage waveform (I/V) during
delay calculation

0.25
0.2
0.15
0.1
0.05
0
0

0.1 0.2

0.3

0.4 0.5

0.6

0.7

0.8

V
0.9

S6

Time Quantized Ceff

Time Quantized Ceff

0.002

ECSM Timing Features

Modeling Miller Caps

Multiple Input Pin Cap Model

Accurately models receiver pin-caps for
large fanout nets with short interconnect

10

4/18/2008

Receiver R0

Delay Accuracy Resistive Interconnect

1800

RISE

ECSM (ps)

1500
1200
900

0.1%

600
300
0

Total C: 16.40 ff
Total R: 15.0 Ohms

300

600

900

1200

1500

1800

SPICE (ps)

1200

FALL

ECSM (ps)

1000
800

0.7%

600
400
200

Total C: 119.45 ff
Total R: 1500.0 Ohms

0
0

200

400

600

800

1000

SPICE (ps)

( 130 nm technology )

11

4/18/2008

ECSM
NLDM

Std. Deviation
0.86
4.17

Min Error
-2.06%
-6.72%

Max Error
3.19%
12.25%

1200

Delay Accuracy
Parallel Drivers

ECSM (ps)

500

RISE

400
300

0.24%

200
100
0
0

100

200

300

400

500

SPICE (ps)

Traditional NLDM
Average w.r.t SPICE
RISE
-14.70%

FALL
-8.60%

ECSM (ps)

( 130 nm technology )
450
400
350
300
250
200
150
100
50
0

FALL

1.2%
0

50

100

150

200

250

SPICE (ps)

12

4/18/2008

300

350

400

450

ECSM Format Definitions

ecsm_waveform : voltage versus time per input slew, output load
define_group( ecsm_waveform, rise_transition);
define_group( ecsm_waveform, fall_transition);
define( index_1, ecsm_waveform, string );
define( values, ecsm_waveform, string );
ecsm_capacitance : pin capacitance versus input slew
define_group( ecsm_capacitance, rise_transition);
define_group( ecsm_capacitance, fall_transition);
define( values, ecsm_capacitance, string );
ecsm_version: ecsm format version number
define( ecsm_version, library, float );

13

4/18/2008

Driver Model Example

rise_transition( temp__1x4) {
index_1 : 0.1n;
index_2 : 0.1p 0.2p 0.3p 0.4p;
values ( 0.01n, 0.02n, 0.026n, 0.45n ) ;
ecsm_waveform( "0" ) {
index_1 : "0.1, .3, .7,.9";
values : "1.005n, 1.012n, 1.018n, 1.02n";
}
ecsm_waveform( "1" ) {
index_1 : "0.1, .48, .7,.9";
values : "1.011n, 1.02n, 1.027n, 1.032n";
}
ecsm_waveform( "2" ) {
index_1 : "0.1, .2, .4, .7,.9";
values : "1.015n, 1.02n, 1.028n, 1.035n,
1.07n";
}
ecsm_waveform( "3" ) {
index_1 : "0.1, .2, .45, .7,.9";
values : "1.021n, 1.029n, 1.04n, 1.06n, 1.07n";
}
}

14

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Voltage Impact on Delay

Characterize ECSM data for 3 voltage levels for each corner
(same process, temp)
typical (1.2V), mid (1.0V), min (0.7V)

Delay calculator employs nonlinear interpolation of voltage

sensitivity for any cell at a voltage between voltage levels
(1.2V 0.7V) and linear extrapolation beyond that range

Encounter
CeltIC NDC/
Encounter

1.2V

.lib + ECSM data

1.0V

.lib+ ECSM data

0.7V

.lib + ECSM data

Typ, 25oC

15

4/18/2008

Voltage Variation Impact on Delay

ECSM Vs SPICE (IBM 90nm) Sensitivity Based
ECSM Vs SPICE (Half Adder IBM 90nm)
4000

SPICE 0.04ns Slew, 1.165fF Load

ECSM 0.04ns Slew, 1.165 Load
SPICE 0.04ns Slew, 109.51fF Load

3500

Delay (ps)

3000
2500

ECSM 0.04ns Slew, 109.51 fF Load

SPICE 0.175ns Slew, 13.048fF Load

Linear Approximation

2000

ECSM 0.175ns Slew, 13.048 Load

SPICE 1.25ns Slew, 1.165 fF Load

1500
1000

ECSM 1.25ns Slew, 1.165fF Load

SPICE 1.25ns Slew, 109.51 Load
ECSM 1.25ns Slew, 109.51 fF Load

500
0

1.2

1.1

0.9

0.8

0.7

0.6

Voltage (V)

Half Adder Cell, 90nm, Slow corner

16

4/18/2008

Statistical ECSM
Extensions to ECSM
(Current Waveform
Modeling)
Adds process and
environmental
parameters to the
existing ECSM
Vth, Leff, Tox, etc
Sensitivity based
Uses Waveform
Sensitivities

tr

Delay Table

tf
tr
tf

Slew Rate
Table

ttr Voltage
vs.
Voltage
vs.
rt
Voltage
vs.
r
Time
Time
ttf
Time
ft
f
tr
tf

Timing
Checks

ECSM Model
Nominal

tr
CL

tf
tr

CL

C
L
CC
L
L

tf

Delay
Sensitivities
Table

CL

Slew Rate
Sensitivities
Table

CL

ttr Voltage
vs.
Voltage
vs.
rt
Waveform
r
Time
C
Time
ttf
CCLL
Sensitivities
ft
L
f
tr Timing Checks

CL

tf
tr
tf

Sensitivities

Cell Random
Sensitivity

CL

CL

Sensitivity Tables For

Delta-P
17

4/18/2008

Parameters Variation
Active Area

Contact

Key Device parameters:

Lgate channel length

VT threshold voltage
Tox oxide thickness
Wgate Channel Width

Lgate

Lgate
Drain

Wgate

4/18/2008

n+

Metal (n+1)
h2
Metal n

Line-width w

Metal thickness t

Metal n

Line-spacing s
ILD Thickness h1
Metal (n-1)

18

source

Key Interconnect
Parameters
Metal thickness t
Dielectric thickness h1, h2
Metal line width (or line
spacing) w or s

Tox
n+

Gate
Oxide

Metal n

S-ECSM Format Definitions (v1.2)

Detailed Process Parameter Specification through new
ecsm_parameter() group at library level

Parameter classification (global/local/random/environmental)

Parameter units
Parameter nominal value
Parameter characterization points (around nominal value)
Parameter range (range of valid values allowed for
characterization)

Higher-order sensitivity modeling

Second/third order sensitivities
Cross product sensitivities

19

4/18/2008

Example of S-ECSM cell (v1.0)

ecsm_timing_sensitivity(){
ecsm_parameter_type : leff;
fall_transition(tmg_ntin_oload_5x5) {
index_1("0.01, 0.06494796, 0.2578274, 0.6261584, 1.2");
index_2("0.01, 0.030465, 0.1023016, 0.239484, 0.4532074");
values("");
}
cell_fall(tmg_ntin_oload_5x5) {
index_1("0.01, 0.06494796, 0.2578274, 0.6261584, 1.2");
index_2("0.01, 0.030465, 0.1023016, 0.239484, 0.4532074");
values( "");
}
rise_transition(tmg_ntin_oload_5x5) { } /* rise_transition */
cell_rise(tmg_ntin_oload_5x5) { } /* cell_rise */
}
ecsm_timing_sensitivity() {
ecsm_parameter_type : tox;
}

20

4/18/2008

Mergelib S-ECSM from Corner Libraries

delay
A11.lib

A12.lib
A1

-x

nom +x

delay
A21.lib

A22.lib
A2

-x

A32.lib
A3

Mergelib

2 Corner
libraries for P3

nom +x

delay
A41.lib

A42.lib
A4

-x

2 Corner
libraries for P2

nom +x

delay
A31.lib
-x

2 Corner
libraries for P1

Configuration
file

Sensitivity
Library
(S-ECSM)
Statistical.lib

Nominal library
2 Corner
libraries for P4

nom +x

Cell process parameters (P1, P2, P3, P4, , Pn)

A11.lib

21

4/18/2008

Conclusion
ECSM has benn the technology leading timing model for
almost 10 years
It has been standardized through Si2 and has an open
evolution process
It has been extended to handle Power, Noise and now
Statistical Delay Calculation

22

4/18/2008