Вы находитесь на странице: 1из 105

Electronics Design Automation Laboratory

Part A
Introduction to SPICE

Electronics Design Automation Laboratory


List of Experiments
1. Introduction to OrCAD PSPICE
2. Simulation of a potential divider Network
3. Clipping and Clamping Circuits
4. RC Coupled Amplifier
5. RC Phase Shift Oscillator
6. Astable Multi-vibrator

Electronics Design Automation Laboratory


1. Introduction to OrCAD PSPICE
Introduction to OrCAD Capture and PSpice
This brief introduction explains how to get started with Cadence OrCAD version 16.3
to draw a circuit (schematic capture) and simulate it using PSpice. It includes examples of
all four types of standard simulation and a selection of different plots.
CAPTURE used to drawn a circuit on the screen, known formally as schematic capture. It
offers great exibility compared with a traditional pencil and paper drawing, as design
changes can be incorporated and errors corrected quickly and easily. (On the other hand, it is
much faster to develop the outline of a circuit using pencil and paper.)
PSPICE simulates the captured circuit. You can analyse its behaviour in many ways and
conrm that it performs as specied.
The aim of this laboratory is to simulate the behaviour of a simple electrical circuit. The
program used is a version of SPICE (Simulation Program for Integrated Circuit
Engineering), which you will use throughout your degree. SPICE was developed at the
University of California at Berkeley in the 1970s and for many years has been the most
widely used circuit simulator in the electronics industry. You will be using a version called
PSpice A/D. There are three steps to using this software.
1. Draw an electronic circuit on the computer using Capture.
2. Simulate it with PSpice using specic models for your devices.
3. Analyse its behaviour with Probe, which can produce a range of plots. Historically this
was a separate application but it is now integrated with PSpice.
Starting OrCAD
Select Capture with Start > Programs > Cadence > Release 16.3 > OrCAD Capture (the
version number may be different if the software has been updated). I use > throughout this
document to show the levels of a hierarchical menu. There will be a short delay while the
software is loaded and the licence server is accessed. Select OrCAD Capture from the start

Electronics Design Automation Laboratory


menu. Wait until the red splash screen disappears. The screen will then show the OrCAD
Capture main window with a menu bar and a dimmed tool bar as shown in Fig. 1. The
untitled sub-window at the bottom is the Session Log. OrCAD creates a large number of
les as it runs, which are organised into a project. These les should be stored in your
workspace.

Fig. 1. Dialogue box to choose product when Capture starts. Select OrCAD Capture.

Always create a new folder whenever you start work on a new project with OrCAD.
Your rst action must always be to create a new project when you are starting a design or to
open an existing project if you are returning to a previous design. Follow these steps to
create a new project.
1. Select File > New > Project. . . from the menu bar. This brings up the New Project
dialogue box.
2. Select the Analog or Mixed A/D button. This is essential or you will not be able to
3.
4.
5.
6.

use PSpice.
Create a directory for the new project if you have not done this already.
Enter a name for the project, such as potdiv as shown in Fig. 2.
Click on OK in the New Project dialogue box to create the project.
Select the Create a blank project button in the small dialogue box that appears,
shown in gure 3, and click OK.

Electronics Design Automation Laboratory

Fig. 2 Dialogue boxes to create a new project.

Fig. 3. Final dialogue box to create a PSPice project. Select create a blank project.

This should open a Schematic window as shown in Fig. 4 on the next page but without
the circuit, which well draw later. The layout may be slightly different if you have a larger
monitor. If you dont see a schematic window, expand the tree in the Project window (top
left) and double-click PAGE1.

Electronics Design Automation Laboratory

Project Manager
Schematic page

Session log

Fig. 4 Screenshot of Capture with the Draw toolbar on the right.


Capture windows
The screenshot of capture shown in Fig. 4 shows three windows.
Project manager usually in the top left corner of the screen. Here is what it contains.
Its title is that of the project, except that its far too long to display because it shows the
whole path.
Under the title is the type of project, which should be Analog or Mixed A/D if you want to
use PSpice.
The body of the window shows the various les that are used by your project, although
you dont have to bother with most of them. I have expanded the tree for ./potdiv.dsn, which
is the current design, by clicking on the + signs. Each design can contain several schematic
drawings, each of which can comprise several pages, but usually there is only one of each. If
you close the schematic window by mistake, expand the tree and double-click on PAGE1.
Schematic Page where you draw your circuit. The Draw toolbar down the right-hand edge
of the screen appears when this window is active.

Electronics Design Automation Laboratory


Session Log along the bottom, title not shown. Most of the material written to this window
can be ignored but you should study it carefully if an error occurs because this is where you
nd the explanation.
The manuals are also installed as pdf les.
Now we will simulate a simple circuit: a potential divider.

2. Simulation of a potential divider Network


7

Electronics Design Automation Laboratory


Aim: To draw and simulate a potential divider network using OrCAD SPICE Software.
Schematic Drawing Procedure:
1. Open new capture project as described in the introduction chapter.
2. Place the components into the schematic window using place part from the menu
tool bar.
3. Add necessary SPICE library files from the pspice folder. For example we need to
add analog library and source library to the library in the place part.
4. Now select the necessary components from the place part menu. The component
resistor is available in the analog library. DC source is available from the source
library. The Fig. 5 shows the capture window with all the selected components.
5. After placing the components, set the values of the components. Capture gives each
component a default value when it is placed but this must usually be changed.
Double-click on a value to change it. This brings up the dialogue box shown in Fig. 6
on the next page for the battery (VDC).
6. The nal step is to connect the components using the wiring tool. Choose Place >
Wire from the menu bar, the button on the Draw toolbar or type W. Always join
components with wires, not by placing them next to each other so that their pins
overlap. Again you cant tell whether the connection has been made correctly.

Fig. 5 Components for potential divider before connecting them.

Electronics Design Automation Laboratory

Fig. 6 Dialogue box

for changing the


value of a component, VDC here

Bias point simulation procedure:


1. The rst step in a simulation is to create a simulation prole, which contains the
instructions to PSpice.
2. Choose PSpice > New Simulation Prole or use the button, which brings up the
dialogue box in Fig. 7 on the following page. Each prole needs a name, which is
used to identify the plots.
3. Click Create and you will see the Simulation Settings dialogue box in Fig. 8. This is
where you tell PSpice what to do. It has several tabs but you rarely need to look at
anything except Analysis.
4. Choose Bias Point analysis, as in Fig. 8 on the following page, and click OK.
5. Now you can run the simulation with PSpice > Run or the arrow on the toolbar.
6. Click on the V button in the toolbar (it may be active already), which displays the
voltage at each node of the circuit. Clicking on I shows the currents in the same way.
The result for the potential divider is shown in Fig. 9.

Fig. 7 Dialogue box to create a new simulation prole.

Electronics Design Automation Laboratory

Fig. 8 Bias Point simulation settings for the simple potential divider

Fig. 9 Simulated voltages and currents for the simple potential divider
DC Sweep Simulation Procedure:
1. Create a new simulation prole.
2. Choose a DC Sweep for the type of analysis as shown in Fig. 10. The Sweep variable
should be a voltage source and we have to tell PSpice the name of the source that we
wish to vary.
3. Copy the name from your schematic drawing; its V1 here.
4. The Sweep type should be Linear and I chose a range from 10 to 10 with an
increment of 1.
5. Click OK and run the simulation as usual.
6. Observe the PSpice A/D window. There should be a plot in the window with a
horizontal scale to match the variable in the simulation, V1 here.

10

Electronics Design Automation Laboratory


7. We must now tell PSpice what to plot on the vertical axis. This can be done from
within PSpice by choosing Trace > Add Trace. . . from the menu bar.
8. Turn off the V button if the original values are still displayed they get in the way.
9. Choose the Voltage Probe tool (something like an oscilloscope probe, or select
PSpice >Markers > Voltage Level from the menu bar) and click on the wire that joins
the two resistors as in Fig. 11. The probe will change colour.
10. Return to PSpice and you will nd a line whose colour matches that of the probe.
11. Make the PSpice window active again and you should see a line on the plot, as in
Fig. 12. This shows the voltage at the selected node as a function of V1.

Fig. 10 Simulation prole for a DC sweep

Fig. 11 Potential divider with a voltage probe

11

Electronics Design Automation Laboratory

Fig. 12 PSpice A/D with a plot of the voltage in the potential divider

Result: Potential divider circuit schematic is created, bias point and DC Sweep simulation is
done.

3. Clipping and Clamping Circuits


Aim: To simulate various clipping and clamping circuits using diodes.

I.

Clipping Circuits:

Transient analysis Procedure: (Time domain analysis)


1. Create new project as described in the previous session.
2. Draw the schematic diagram as shown in Fig. 3.1, 3.2 and 3.3.

12

Electronics Design Automation Laboratory


3. Create new simulation profile as shown in Fig. 3.4 & 3.5.
4. Select the analysis type as Transient with options general settings.
5. Specify the Run to time settings.
6. Also specify the Maximum step size.
7. Click Ok to close the new simulation profile.
8. Place the Voltage probe to the output node.
9. Click on the Run PSpice button to start the Transient analysis.
10. The simulation results will be displayed on the screen.
11. Plot the results as shown in Fig. 3.6, 3.7, and 3.8.
DC Sweep analysis Procedure (For plotting transfer curve):
1. Draw the schematic diagram as shown in Fig. 3.9, 3.10 and 3.11.
2. Create new simulation profile.
3. Select the analysis type as DC sweep with options primary sweep.
4. Specify the source name for DC sweep.
5. Specify the range of sweep setting and step size.
6. Also specify the type of DC sweep (select linear sweep).
7. Click Ok to close the new simulation profile.
8. Place the Voltage probe to the output node.
9. Click on the Run PSpice button to start the DC sweep analysis.
10. The transfer curve will be plotted on the simulation window.
11. Plot the results as shown in Fig. 3.12, 3.13, and 3.14.

Fig. 3.1 Series Clipper Circuit

13

Electronics Design Automation Laboratory

Fig. 3.2 Shunt clipper circuit

Fig. 3.3 Biased shunt clipper circuit

14

Electronics Design Automation Laboratory

Fig. 3.4 Dialogue box for creating new simulation profile

Fig. 3.5 Create new simulation profile

15

Electronics Design Automation Laboratory

Fig. 3.6 Simulated output waveform for series clipper.

Fig. 3.7 Simulated output waveform of shunt clipper.

Fig. 3.8 Simulated output waveform of biased shunt clipper.

16

Electronics Design Automation Laboratory

Fig. 3.9 Transfer curve for series clipper circuit.

Fig. 3.10 Transfer curve for shunt clipper circuit.

Fig. 3.11 Transfer curve for biased shunt clipper circuit.

17

Electronics Design Automation Laboratory

II.

Clamping Circuits:

Transient analysis Procedure: (Time domain analysis)


1. Create new project as described in the previous session.
2. Draw the schematic diagram as shown in Fig. 3.12, 3.13 and 3.14.
3. Create new simulation profile.
4. Select the analysis type as Transient with options general settings.
5. Specify the Run to time settings.
6. Also specify the Maximum step size.
7. Click Ok to close the new simulation profile.
8. Place the Voltage probe to the output node.
9. Click on the Run PSpice button to start the Transient analysis.
10. The simulation results will be displayed on the screen.
11. Plot the simulation results as shown in Fig. 3.15, 3.16, and 3.17.

Fig. 3.12 Positive clamper circuit

18

Electronics Design Automation Laboratory

Fig. 3.13 Negative clamper circuit

Fig. 3.14 Biased negative clamper circuit

Fig. 3.15 Simulated output waveform of positive clamper

19

Electronics Design Automation Laboratory

Fig. 3.16 Simulated output waveform of negative clamper

Fig. 3.17 Simulated output waveform of biased negative clamper

Result: Various clipping and clamping circuits are simulated and plotted its output
waveforms.

20

Electronics Design Automation Laboratory


4. RC Coupled Amplifier
Aim: To simulate a Common Emitter (CE) amplifier using BJT.
Transient analysis Procedure: (Time domain analysis)
1. Create new project as described in the previous session.
2. Draw the schematic diagram as shown in Fig. 4.1.
3. Create new simulation profile.
4. Select the analysis type as Transient with options general settings.
5. Specify the Run to time settings.
6. Also specify the Maximum step size.
7. Click Ok to close the new simulation profile.
8. Place the Voltage probe to the output node.
9. Click on the Run PSpice button to start the Transient analysis.
10. The simulation results will be displayed on the screen.
11. Click on the V icon I icon in the menu bar to get bias point simulation for voltage
and current as shown in Fig. 4.2.
12. Plot the results as shown in Fig. 4.3.
AC Sweep analysis Procedure (For plotting frequency response):
1. Draw the schematic diagram as shown in Fig. 4.4. Note the VSIN source has been
replaced with VAC.
2. Create new simulation profile.
3. Select the analysis type as AC sweep with options general settings as shown in Fig.
4.5.
4. Specify the start frequency, End frequency and Points/decade.
5. Specify the sweep type to logarithmic.
6. Click Ok to close the new simulation profile.
7. Place the Voltage probe to the output node.
8. Click on the Run PSpice button to start the AC sweep analysis.
9. The Frequency response will be plotted on the simulation window.
10. Plot the frequency response as shown in Fig. 4.6.
11. To measure bandwidth, go to Trace >>Evaluate measurement >>
Bandwidth_Bandpass_3dB(V(R10:2)). Here R10 is the load resistance.
12. Click Ok to get the reading at the bottom of the measurement pane.
13. To measure upper-cut off frequency, goto Trace>>Evaluate measurement>>
Cutoff_Lowpass_3dB(V(R10:2)). Click ok to get the upper cut-off frequency at the
bottom of the measurement pane.
14. To measure lower cut-off frequency, goto Trace>>Evaluate measurement>>
Cutoff_Highpass_3dB(V(R10:2)). Click ok to get the upper cut-off frequency at the
bottom of the measurement pane.

21

Electronics Design Automation Laboratory

Fig. 4.1 Schematic diagram of the CE Amplifier

Fig. 4.2 Bias point simulated output

22

Electronics Design Automation Laboratory

Fig. 4.3 Simulated output voltage waveform using transient analysis

Fig. 4.4 Schematic diagram of CE amplifier for AC Sweep analysis

23

Electronics Design Automation Laboratory

Fig. 4.5 Dialogue box for AC sweep analysis settings

Fig. 4.6 Frequency response of the CE amplifier


Result: Transient and AC sweep analysis of the CE amplifier is studied and plotted its output
waveform. Also measured the Upper cut-off frequency, Lower cut-off frequency and
Bandwidth.

24

Electronics Design Automation Laboratory


5. RC Phase Shift Oscillator
Aim: To simulate an RC Phase Shift Oscillator using BJT.
Transient analysis Procedure: (Time domain analysis)
1. Create new project.
2. Draw the schematic diagram as shown in Fig. 5.1.
3. Create new simulation profile.
4. Select the analysis type as Transient with options general settings.
5. Specify the Run to time settings.
6. Also specify the Maximum step size.
7. Click Ok to close the new simulation profile.
8. Place the Voltage probe to the output node.
9. Click on the Run PSpice button to start the Transient analysis.
10. The simulation results will be displayed on the screen.
11. Click on the V icon I icon in the menu bar to get bias point simulation for voltage and
current as shown in Fig. 5.2.
12. Plot the simulation results as shown in Fig. 5.3.
Schematic Diagram:

Fig. 5.1 Schematic diagram of the RC Phase Shift Oscillator using BJT

25

Electronics Design Automation Laboratory

Fig. 5.2 Bias point simulation of RC Phase Shift Oscillator

Fig. 5.3 Simulated output waveform

Result: RC Phase Shift Oscillator circuit is simulated using OrCAD PSPICE. Plotted the
output waveform.

26

Electronics Design Automation Laboratory

Part B
Introduction to HDL

27

Electronics Design Automation Laboratory

List of Experiments
1. Familiarization of Xilinx ISE
2. Demonstration of different VHDL Models: Behavioral, Dataflow And
3.
4.
5.
6.
7.
8.
9.

Structural models using XOR Gate


Multiplexer: Dataflow and Structural models
1:4 De-multiplexer: Dataflow and Structural models
Comparator: Dataflow and Structural models
Full Adder
4-bit Ripple Carry Adder
D Flip-Flop
Sequence Generator using FSM Model

Experiment No. 1

28

Electronics Design Automation Laboratory


Familiarization of Xilinx ISE
Xilinx ISE (Integrated Software Environment) is software too produced by Xilinx for
synthesis and analysis of HDL designs, enabling the developer to synthesize (compile) their
designs, perform timing analysis, examine RTL diagrams, stimuli and configure the target
device with programmers.
ISE controls all aspects of the design flow. Through the project Navigator interface, we can
access all of the design entry and design implementation tools. We can also access the files
and document associated with our project.
Hardware Description Language (HDL) is a popular mode of design entry. Two popular
HDLs are VHDL and Verilog. VHDL is a hardware description language used to describe
the behavior and structure of digital systems. VHDL is a general purpose HDL that can be
used to describe and stimulate the operation of wide variety of signal digital systems,
ranging in complexity from a few gates to an introduction of many complex integrated
circuits. VHDL can describe a digital system at several different levels:
1) Behavioral
2) Dataflow
3) Structural
If we can put several of the building blocks for digital circuits into an IC and provide user
with mechanism to modify the configuration, we can implement almost any circuit within a
chip. This is the general principle of programmable logic devices. Programmable logic
devices such as PALs and FPGAs are used for implementation of digital circuits because
there is reasonable integration ability allowing implementation of a significant amount of
functionality into one physical chip. PLDs remove the use of multiple off the shelf devices
and the inconvenience and unreliability associated with external wires. Second, there is
increased ability to change designs. Many of the programmable devices allow easy
reprogramming. PLDs are in general classified as Factory Programmable and Field
Programmable. Field Programmable devices include SPLD, CPLD and FPGA. Again, SPLD
includes PROM, PLA, PAL, GAL. A Field Programmable gate array (FPGA) is an
integrated circuit designed to be configured by a customer or a designer after manufacture.
FPGA configuration generally specified using a HDL similar to that used for an application
specific integrated circuit (ASIC).
The integrated software environment (ISE) is the Xilinx design software suit that allows

I.

Create a new project


29

Electronics Design Automation Laboratory


Create a new ISE project which will target the FPGA device on the Spartan 3E startup kit
demo board. To create a new project
1) Select file New project. The New Project Wizard appear
2) Type project Name
3) Verify that HDL is selected from the top level source type list
4) Click next to move to the device properties page
5) Fill in the properties in the table as shown below

Product category :ALL

Family :Spartan 3E

Device :XC3S500E

Package :FG320

Speed rate :-4

Top level source type :HDL

Synthesis tool :XST

Simulator :ISim

Preferred language : VHDL

Verify that enable enhanced design sum is selected.


6) Click next to proceed to create new source window in the New Project Wizard. At
the end of the section your project will complete.

II.

Create an HDL source:

1) Click the new source button in the New Project Wizard


2) Select VHDL module as the same type

30

Electronics Design Automation Laboratory


3) Type in the file name
4) Verify that the add to project check on is selected
5) Click next
6) Declare the ports of the counter design by filling in the port information
7) Click next, then finish in the new source information dialog box to complete new
source file template
8) Click next, then next and then finish.
The source file containing the entity/ architecture pair displayed in the workspace. Enter the
VHDL code and then save and check syntax.

III.

Design simulation

1) Select the file name HDL file in the source window


2) Create new test bench waveform source by selecting project new source
3) Select test bench waveform and enter a name
4) Click then next and then finish
5) Save the waveform.
6) In the source window, select the behavioral simulation. View to see that test bench
waveform is automatically added to our project.
7) Click the test bench waveform. Select the test bench waveform in the source
window.
8) Double click on the simulate behavioral mode and check the waveform
VHDL language was introduced in 1981 for the Department of Defense (DoD) under the
VHSIC program. In 1983, IBM, Texas, instruments and Intermetrics started to develop this
language. In 1985, VHDL 7.2 version was released. In 1987, IEEE standardized the
language. VHDL stands for Very high speed integrated circuit Hardware Description

31

Electronics Design Automation Laboratory


Language which is one of the programming languages used to model a digital system by
data flow, behavioral and structural style of modeling.

Describing a design
In VHDL, a VHDL module is used to describe a hardware module. A VHDL module can be
described using:
1) Entity declaration
2) Architecture
3) Configuration
4) Package declaration
5) Package body

Entity declaration
It defines the name, input, output signal and modes of a hardware module.

Syntax
entity EntName is
port (P1, P2: in Std_logic;
P3: out Std_logic_vector(7 downto 0));
end EntName;
An entity is modeled using an entity declaration and at least one architecture body. Entity
declaration should start with the key word entity and ends with end. Ports are signal
through which the entity communicates with the other models in its external environment.
Each port must have a name, direction and a type. The direction can be input, output or
inout. Entity declaration of a half adder circuit is shown below
entityhalf_adder is
port (A, B: in bit;

32

Electronics Design Automation Laboratory


sum, carry :out bit);
endhalf_adder;

Architecture:
The internal details of an entity are specified by an architecture body. It describes the
functionality of structure of entity. An entity can have many internal views, each of which is
describe using separate architecture body. An entity can have one or more architecture
bodies. Generally there are 4 modeling styles.
1) As a set of inter connected components (structural)
2) As a set of concurrent assignment statements (data flow)
3) As a set of sequential assignment statements (behavioral)
4) Any combination of the above three.
Syntax
Basic Syntax:
Architecture ArchName of EntName is
--Signal Initialization, Component declaration etc.
Begin
--Process statement in case of behavioral modelling with sequential code blocks like if-elsifelse, case statement, loop statement etc.
--Port Map statement in case of structural modelling.
--Concurrent statements in case of data flow modelling
endArchName;
The - - indicates a comment, which is not processed by VHDL.

Configuration declaration
A configuration declaration is used to select one of the possibly many architecture bodies
that an entity may have and behind the components used to represent structure in that

33

Electronics Design Automation Laboratory


architecture body, entities represented by an entity architecture pair or by a configuration
which resides in the assign library.
Syntax
Configuration ConfigurationName of EntityName is
Declarations... --use, attribute or group
forArchitectureName--of entity named above
use...
ConfigurationItems
end for;
end [configuration] [ConfigurationName];
Example:
librarycmos.LIB.MY_LIB;
configurationHA.binding of half adder is
forHA_structure

-- specifies that the architecture body HA_structure is selected.

for x1: XOR 2;


use entity cmos.LIB.XOR_gate
end for;
for A1: And 2
use configuration MY.LIB.AND_config:
end for;

-- component instantiation

end for;
endHA_binding;
An architecture body that does not contain any component instantiation for example, when
dataflow style is used, can also be selected to create a configuration. Configuration specifies
how a top level entity is organized in term of lower level entities by specifying the binding
between them.

34

Electronics Design Automation Laboratory

Package declaration
A package declaration is used to store a set of common declarations, such as component,
types, procedures and functions.
Syntax
Package package_name is
package item declaration

--these may be sub program declaration type declaration,

construct declaration, signal declaration etc.


end [package] [package_name];
usework.package_name.all imports all declaration into current entity declarations.

Package body
It is used to store the definitions of function and procedures that were declared in the
corresponding package declarations and also the complete constant declarations for any
constants that appear in the package declaration. A package declaration can have almost one
package body associated with it.
Syntax
Package_body_item_declarations -- these are sub program bodies, complete constant
declarations, subprogram declarations, type and subtype declarations
end [package body] [package_name];

The internal working of an entity can be defined using different modeling styles inside
architecture body. They are
1) Data flow modeling
2) Behavioral modeling
3) Structural modeling

35

Electronics Design Automation Laboratory


Data flow model
In this style of modeling the internal working of an entity can be implemented using
concurrent signal assignment.
Lets take half adder example which is having one XOR gate and an AND gate.
libraryIEEE;
Use IEEE.STD_LOGIC_1164.all;
entityhalf_adder is
port(A, B: in bit
S,C : out bit);
endhalf_adder;
architectureha_ad of half_adder is
begin
S<=A XOR B;
C<= A AND B;
endha_ad;
Here STD_LOGIC_1164 is an IEEE standard which defines a nine values logic type called
STD_LOGIC use is a keyword, which imports all the declarations from this package. The
architecture body consists of concurrent signal assignments which describe the functionality
of the design whenever is evaluated and the value is assigned to LHS.

Behavioral modeling
In this style of modeling, the internal working of an entity can be implemented using set of
statements. It consists
1) Process statements
2) Sequential statements
3) Signal assignment statement
4) Wait statement

36

Electronics Design Automation Laboratory


Process statement is the primary mechanism consists sequential statements, variable
assignments etc. it may or may not contain sensitivity if an event occurs on any of the
signals on the sensitivity list.
Inside the process, the execution of statements will be sequential and if one entity is having
tow process, the execution of this process will be concurrent. At the end, it waits for another
event to occur.
A typical Behavioral model program can have the following syntax:
architectureArchName of EntName is
signalSignalName, SignalName2: Std_logic := 'U';
begin
P: process (P1,P2,P3) -- Either sensitivity list or wait statements!
variableVariableName, VarName2: Std_logic := 'U';
begin
SignalName<= Expression after Delay;
VariableName := Expression;
if Condition then
-- sequential statements
elsif Condition then
-- sequential statements
else
-- sequential statements
end if;
case Selection is
when Choice1 =>
-- sequential statements
when Choice2 | Choice3 =>

37

Electronics Design Automation Laboratory


-- sequential statements
when others =>

--Keyword others accounts for all other possibilities

-- sequential statements
end case;
for I in A'Range loop

--loop repeated for each element of vector A.

-- sequential statements
end loop;
end process P;
SignalName<= Expr1 when Condition else Expr2;
endArchName;
Structural modeling
The implementation of an entity is done through a set of interconnected components. It
contains
1) Signal declaration
2) Component instances
3) Port maps
4) Wait statements
Component declaration syntax
componentComponentName [is]
[Port;]
end component [ComponentName];
Before instantiations the component, it should be declared using component declaration as
shown above. Componentdeclaration declares the name of the entity and interface of a
component.
A structural model can have the following syntax:

38

Electronics Design Automation Laboratory


Architecture ArchName of EntName is
componentCompName
port (P1: in Std_logic;
P2: out Std_logic);
end component;
signalSignalName, SignalName2: Std_logic := 'U';
begin
--Positional association:
InstanceLabel1: CompName port map (S1, S2);
--Named association:
InstanceLabel2: CompName port map (P1 => S1, P2 => S2);
End ArchName

Basic VHDL Statement Syntax


Library syntax
Library

<library_name>;

Use

<library_name>.<package_name>.<package_parts>;

Component instantiation syntax


Label:<component_name>port map (signal mapping);
Signal declaration syntax
signal<signal_name>:signal_type(Range):=Initial value;

Variable declaration syntax:


Variable
value;

<variable=name>:variable_type(Range):=

Initial

39

Electronics Design Automation Laboratory


Constant declaration syntax:
Constant
values;

<constant_name>:constant_type

(Range)=initial

Simple when/else syntax


[Label:] Target_Signal<= [Options]
Expression_1 [after TimeExpression] when Condition1 else
Expression_2 [after TimeExpression] when Condition2 else
...
Expression_N [after TimeExpression] [when ConditionN];

WhereTimeExpressionis a time interval like 20ns, 40ns etc.


[Options]specifies the delay model like inertial, transport etc. This is optional.

With/select/when:
[Label:] with Expression select
Target_Signal<= [Options]
Expression [after TimeExpression] when Choices,
Expression [after TimeExpression] when Choices,
... ;
Choices may be a constant, a range, or the keyword others to include all other possible
results of Expression.

Process syntax
[Label:] process [ (SensitivityList) ] [is]
Declarations...

40

Electronics Design Automation Laboratory


begin
SequentialStatements...
end process [Label];
If statement syntax:
[Label:] if Condition then
SequentialStatements...
[elsif Condition then
SequentialStatements...]
... {any number of elsif parts}
[else
SequentialStatements...]
end if [Label];
Case statement syntax:
[Label:] case Expression is
when Choices =>
SequentialStatements...
when Choices =>
SequentialStatements...
... {any number of when parts}
end case [Label];
While loop statement:
[LoopLabel:] while Condition loop
SequentialStatements...
end loop [LoopLabel];

41

Electronics Design Automation Laboratory


For loop syntax:
[LoopLabel:] for ParameterName in Range loop
SequentialStatements...
end loop [LoopLabel];;
Wait statement syntax:
wait until <signal_condition>;
wait on signal <signal1, signal2..>;
wait for <time>;
Wait statements can only be used in processes without sensitivity lists.

42

Electronics Design Automation Laboratory


Experiment No. 2
Demonstration of Different VHDL Models: Behavioral, Dataflow and
Structural Models Using XOR Gate

AIM
To write a VHDL program of XOR gate using dataflow, behavioral and structural modeling
DESIGN FLOW
Block Diagram
A

0
0
1
1

0
1
0
1

0
1
1
0

Truth Table

Logic Expression
C= A B+ A B

43

Electronics Design Automation Laboratory

Circuit Diagram

ALGORITHM
Dataflow Model
Step 1: Define entity as XOR_gate.
Step 2: Define the entity with two input ports A and B and output pin as C.
Step 3: Define architecture name as dataflow.
Step 4: Define functionality inside architecture under begin statement as C <= A xor B
Step 5: End

Behavioral Model
Step 1: Define entity as XOR_gate.
Step 2: Define the two inputs pins A and B and output pin C to be as structure of entity.
Step 3: Provide architecture name as behavioral.
Step 4: Inside the architecture statement follow sequential method. Use the logic of checking
whether the two inputs are equal or not. If equal, output as low, else as high. Use process
statement.

44

Electronics Design Automation Laboratory


Step 5: End
Structural Model:
Step 1: Define entity as XOR gate.
Step 2:Provide entity architecture pair of gates involved. Define entity not gate, architecture
first and functionality
B <= not A
Define entity and gate, architecture second and functionality
C <= A and B
Define entity or gate, architecture third and functionality
C <= A or B
Step 3: Define main architecture Structural.
Step 4: Instantiate component and signals involved
Step 5: Map ports using Port Map statement.
Step 5: End

PROGRAM
Dataflow Model

45

Electronics Design Automation Laboratory

Behavioral Model

46

Electronics Design Automation Laboratory

Structural Model

47

Electronics Design Automation Laboratory

48

Electronics Design Automation Laboratory

49

Electronics Design Automation Laboratory

SIMULATION

RESULT

Dataflow Model

50

Electronics Design Automation Laboratory

Behavioral Model

Structural Model

SYNTHESIZED HARDWARE

51

Electronics Design Automation Laboratory

RESULT
(1) VHDL program for XOR gate was written, executed, output obtained and verified in
dataflow, behavioral and structural modelling.
(2) Familiarized with Xilinx ISE Simulator
(3) Familiarized with VHDL Programming.

52

Electronics Design Automation Laboratory


Experiment No.3
Multiplexer: Dataflow and Structural models
AIM
To write a VHDL program for 4:1 multiplexer using dataflow and structural modelling
DESIGN FLOW
Block diagram

S(0)

S(1)

0
0
1
1

0
1
0
1

d(0)
d(1)
d(2)
d(3)

Truth table

53

Electronics Design Automation Laboratory

Logic Expression

Y = S (0) S ( 1 ) d ( 0 ) + S ( 1 ) S ( 0 ) d (1 ) + S ( 0 ) S ( 1 ) d ( 2 ) +S ( 0 ) S ( 1 ) d (3)
Circuit Diagram

ALGORITHM
Data flow model
Step1: Define entity as muxp
Step2: Declare ports with input port d (std_logic_vector (3 down to 0)) and S
(Std_logic_vector (3 down to 0)) and output port Y.
Step3: Define architecture as dataflow.
Step4: Statement part of architecture is defined using concurrent statement when-else

54

Electronics Design Automation Laboratory


Step5: End.

Structural modelling
Step1: Define entity as muxp
Step2: declare input ports d (std_logic_vector (3down to 0)) and S (Std_logic_vector
(3down to 0)) and output port Y.
Step3: Define entity architecture pair for each component in logic diagram (3 input AND
gate, 4 input OR gate, NOT gate)
Step4: Define main architecture.
Step5: Declare component and interconnection signal. In statement part instantiate all
components.
Step6: End.

PROGRAM
Data flow Model

55

Electronics Design Automation Laboratory

Structural Model

56

Electronics Design Automation Laboratory

57

Electronics Design Automation Laboratory

Testbench of Structural Model

58

Electronics Design Automation Laboratory

SIMULATION RESULT

SYNTHESIZED HARDWARE

59

Electronics Design Automation Laboratory

RESULT

VHDL Program for 4:1 multiplexer using dataflow and structural models were simulated
and the output waveforms were observed.

60

Electronics Design Automation Laboratory

Experiment No.4
1:4 Demultiplexer: Dataflow and Structural models
AIM
To write a VHDL program for 1:4 demux using data flow and structural model

DESIGN FLOW
Block diagram

Truth Table
s(1) s(0) y(0
)

y(1
)

y(2
)

y(3
)

Logic Expression

61

Electronics Design Automation Laboratory


y ( 0 )= s (0 ) s (1 ) d
y (1 ) =s (1 ) s ( 0 ) d
y (2 )=s ( 0 ) s ( 1 ) d
y (3 )=s(0)s (1 ) d

Circuit Diagram

62

Electronics Design Automation Laboratory

ALGORITHM
Data flow model
Step1: Define the entity as d2.
Step2: Declare input ports s (std_logic vector) (1 down to 0) and d and output port y
(std_logic vector) (3 down to 0)
Step3: Define architecture. The statement part is defined using when-else statement.
Step4: End.

Structural model
Step1: Define entity as demux
Step2: Declare input pots as d and s (vector) and output port as y (vector)
Step3: Define entity architecture pair for each component in logic diagram (3 input AND
gate, NOT gate).
Step4: Define main architecture struct.
Step5: Declare components and interconnect signal.
Step6: Instantiate each component in statement part of architecture.
Step7: End.

PROGRAM
Behavioral Model

63

Electronics Design Automation Laboratory

Structural Model

64

Electronics Design Automation Laboratory

65

Electronics Design Automation Laboratory

SIMULATION RESULT
Behavioral Model

Structural Model

SYNTHESIZED HARDWARE

66

Electronics Design Automation Laboratory

RESULT
VHDL program for 1:4 de-multiplexer was developed, simulated and observed the output
waveform in both behavioral and structural models.

67

Electronics Design Automation Laboratory


Experiment No.5
1-bit Comparator: Dataflow and Structural models
AIM
To write a VHDL program for one bit comparator using dataflow and structural models.

DESIGN FLOW
Block diagram

Truth Table
A

Y(0
)

Y(1
)

Y(2
)

0
0
1
1

0
1
0
1

0
0
1
0

0
1
0
0

1
0
0
1

K Map
y(2)

y(1)

y(2)

68

Electronics Design Automation Laboratory


B

B
A

0
0
1

1
0
0

0
0 0
Logic Expression
1 0

1
1
0

0
1
A

y ( 0 )= A B
y (1 ) = A B
B
y (2 )=AB+ A
=

A
0
1

0
1
0

1
0
1

B
A

Circuit Diagram

ALGORITHM

69

Electronics Design Automation Laboratory


Dataflow Model
Step 1: Define entity comp.
Step 2: Declare input ports A and B and output port Y (vector).
Step 3: Define architecture dataflow
Step 4:Define functionality inside the architecture under begin as
Y(0) <= a and (not B)
Y(1) <= (not a) and B
Y(2) <= (not a) and (not B) or (a and B)
Step 5: End

Structural Model
Step 1: Define entity cmp.
Step 2: Declare input ports A and Band output Y
Step 3: Define entity architecture pair for each component in circuit diagram (two input
AND gate and OR gates)
Step 4: Define architecture comparator
Step 5: Declare component used and interconnecting signals in declarative part
Step 6: Instantiate each component in the statement part of architecture
Step7: End

PROGRAM

70

Electronics Design Automation Laboratory


Dataflow Model

Structural Model

71

Electronics Design Automation Laboratory

72

Electronics Design Automation Laboratory

SIMULATION RESULT
Dataflow Model

73

Electronics Design Automation Laboratory

Structural Model

SYNTHESIZED HARDWARE

74

Electronics Design Automation Laboratory

RESULT
VHDL Program for 1 bit comparator in dataflow and structural model was developed,
simulated and waveforms were observed.

75

Electronics Design Automation Laboratory


Experiment No. 6
Full Adder
AIM
To write a VHDL program for full adder using package.

DESIGN FLOW
Block Diagram

Truth Table
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

Cin
0
1
0
1
0
1
0
1

S
0
1
1
0
1
0
0
1

Cout
0
0
0
1
0
1
1
1

K-Map
S

Cout
A
B

AB
Ci
n
0
1

00 0
1
0 0
0 1

11 10
1
1

0
1
76

Electronics Design Automation Laboratory


Ci
n
0
1

0
0
0
1

0
1
1
0

11 1
0
0 1
1 0

Boolean Expression
B C + A B C + A
B C + A B C = A B C
S= A
C out = A B+ B C + A C
Circuit diagram

ALGORITHM
Step1: Declare the package basic gate.
Step2: Declare component 3 input XOR gate, 2 input AND gate and 3 input OR gate inside
the package declaration (no package body is needed).
77

Electronics Design Automation Laboratory


Step3: Define entity-architecture pairs for each and every component.
Step4: Take new VHDL module.
Step5: Use new library statement. Use work.basicgate.all to include the package in the
project.
Step6: Declare entity- full adder with input input ports a,b,cin and output ports s and cout.
Step7: Define architecture strct.
Step8: Define interconnecting signal.
Step9: Instantiate component declared in package inside the architecture statement part.
Step10: End.

PROGRAM

78

Electronics Design Automation Laboratory


Structural model

79

Electronics Design Automation Laboratory

80

Electronics Design Automation Laboratory

SIMULATION RESULT

81

Electronics Design Automation Laboratory


Structural model

SYNTHESIZED HARDWARE

RESULT
VHDL program for full adder was developed using package, simulated and observed the
output waveform.

82

Electronics Design Automation Laboratory


Experiment No.7
4-bit Ripple Carry Adder
AIM
To write a VHDL program for four bit ripple carry adder using dataflow, behavioral and
using package

DESIGN FLOW

Boolean Expression
For full adder, sum = A B C
Cout = (A B ) C

+ AB

S (0) =A (0) B ( 0 ) C
S (1) = A (1) B ( 1 ) C0 (1)
S (2) =A (2) B ( 2 ) C0 (2)

83

Electronics Design Automation Laboratory


S (3) =A (3) B ( 3 ) C 0 (3)
C (0) = (A (0) B(0) ) C

+ A (0) B (0)

C (1) = (A (1) B(1) ) C

+ A (1) B (1)

C (2) = (A (2) B(2) ) C

+ A (2) B (2)

C (3) = (A (3) B(3) ) C

+ A (3) B (3)

ALGORITHM
Dataflow Model
Step 1: Define entity RCA.
Step 2: Declare input ports a (4 bit vector), b (4 bit vector) and inout ports s (4 bit vector)
and co (4 bit vector).
Step 3: Define architecture ripple carry.
Step 4: Define the functionality inside the architecture using Boolean expression.
Step 5: End
Behavioral Model
Step 1: Define entity RCA.
Step 2: Declare input ports a (4 bit vector), b (4 bit vector) and inout ports s(4 bit vector) and
co(4 bit vector).
Step 3: Define architecture as behavioral.
Step 4: Inside the architecture, functionality is defined using sequential statements, for loop
inside the process statement. The carry into the circuit is cin and carryout is co(4).
Step 5: End the process statement.
Step 6: End

84

Electronics Design Automation Laboratory


Structural Model
Step 1: Define package full adder
Step 2: Declare component fa inside the package declaration.
Step 3: End the package.
Step 4: Define the entity architecture pair for fa.
Step 5: Take VHDL module.
Step 6: Use library statement .use work .full adder .all to include package into the project.
Step 7: Declare entity RCA with input ports a, b(both as input vector) and cin as in out (4 bit
vector).
Step 8: Define architecture strct.
Step 9: Inside the architecture strct, instantiate component fa.
Step 10: End

PROGRAM
Dataflow model

85

Electronics Design Automation Laboratory

Behavioral model

86

Electronics Design Automation Laboratory

Structural model

87

Electronics Design Automation Laboratory

88

Electronics Design Automation Laboratory

SIMULATION RESULT
Dataflow model

Behavioral model

Structural model

89

Electronics Design Automation Laboratory

SYNTHESIZED HARDWARE
Dataflow model

90

Electronics Design Automation Laboratory


Structural model

RESULT
VHDL program for 4 bit ripple carry adder was developed in dataflow, behavioral and
structural model using package, and simulated and verified output waveform

91

Electronics Design Automation Laboratory


Experiment No.8
D-Flip Flop
AIM
To write a VHDL program for D Flip Flop
a) Positive Edge Triggered
b) Negative Edge Triggered
c) Level Triggered

DESIGN FLOW
Block Diagram

Truth Table
CLK
0
1
1

D
X
0
1

Qn+1
Qn
0
1

Boolean Expression
Qn+1

= CLK Qn + CLKD

ALGORITHM

92

Electronics Design Automation Laboratory


Edge Triggered D-Flip-flop
Step 1:Define Entity as dff
Step 2: Define input port as CLK and D and output port as Q
Step 3: Define architecture as behavioral
Step 4: Inside the architecture functionality is defined using the sequential statement if
inside the process statement. Use the event attribute to detect triggering of clock pulse.
Step 5: For positive Edge Triggered D flipflop, condition to be checked is CLKEVENT and
CLK = 1.
For negative Edge Triggered D flipflop, condition to be checked is CLKEVENT and CLK
= 0.
Step 6: If condition is True, then D is assigned to output.
Step 7: End Process
Step 8 End.

Level Triggered D-Flipflop


Step 1:Define Entity as dff
Step 2: Define input port as CLK and D and output port as Q
Step 3: Define architecture as behavioral
Step 4: Inside the architecture functionality is defined using the sequential statement if
inside the process statement.
Step 5: For Level Triggered D flipflop, condition to be checked is CLK = 1.
Step 6: If condition is True, then D is assigned to output.
Step 7: End Process
Step 8 End.

PROGRAM

93

Electronics Design Automation Laboratory


Behavioral model
Positive edge triggered D Flip-flop

Negative edge triggered D Flip-flop

Level triggered D Flip-flop

94

Electronics Design Automation Laboratory

SIMULATION RESULT
Positive edge triggered D Flip-flop

Negative edge triggered D Flip-flop

95

Electronics Design Automation Laboratory

Level triggered D Flip-flop

SYNTHESIZED HARDWARE
Positive edge triggered D Flip-flop

96

Electronics Design Automation Laboratory


Negative edge triggered D Flip-flop

Level triggered D Flip-flop

RESULT
VHDL program for positive, negative edge triggered and level triggered D flip-flop was
developed and output waveform is verified.

97

Electronics Design Automation Laboratory


Finite State Machines
Finite-state machine (FSM) is an important area in digital logic design. FSMs are commonly
used as controllers or sequence detectors in a digital system. A finite state machine can be
described in terms of following structures.
1. A set of inputs X.
2. A set of outputs Z.
3. A finite length state table enumerating valid states.
4. Specifying which is the initial state.
5. A Boolean Function NS(S,X) which maps present state S to next state NS.
6. An output function F(S,X) which calculates Z from S and X in Mealy machines and F(S)
in case of Moore machines.
A sequence detector is an example for a finite state machine.
The standard way of modelling an FSM is as follows:
Step 1: Define an enumerated data type to represent valid states. The actual code assignment
to the states is left to the synthesis tool. The encoding may be binary, gray code, one hot or
one cold. Define signals PRESENT_STATE and NEXT_STATE belonging tothe enumerated
state class.
Step 2: Define one process for the memory elements which makes PRESENT_STATE as the
initial state if RESET is active else with the rising edge of the clock, it assigns the
NEXT_STATE to the PRESENT_STATE.
Step 3: Define either a concurrent statement with when else logic or a process with case
logic which determines the NEXT_STATE based on the present state and the present input
X.
Step 4: Define either a concurrent statement with when else logic or a process with case
logic which determines the output Z. In case of a mealy machine, Z depends on the present
state and the present input X. In case of a moore machine, Z depends only on the present
state.

98

Electronics Design Automation Laboratory


Experiment No. 9
Sequence Generator
AIM
To write a VHDL program to generate the sequence 1101 using D-flip flops.
DESIGN FLOW
Block Diagram

The number of flip-flops (n) needed to generate a sequence of N bits is given by


N 2n1 .Thus, for a 4 bit sequence, we need three flip-flops. We have three outputs
Q0 ,Q1Q 2

from the three flipflops FF0, FF1 and FF2. The flip-flops are connected as a

shift register with feedback. The input D2 of FF2 is fed by a function of the three outputs
Q0 ,Q1Q 2
.
To determine this function, we make a table as follows:
CLK
1
2
3
4
5

Flip-flop Outputs
Q2
1
1
0
1
1

Q1
1
1
1
0
1

Q0
0
1
1
1
0

Z
1
0
1
1
1

99

Electronics Design Automation Laboratory


6
7
8

1
0
1

1
1
0

The entries of the column

Q2

is the required sequence.

1
1
1
Q1

0
1
1
and

Q0

gets the same

sequence delayed by one and two units respectively, as the system acts like a shift register.
Q2
The last column Z gives the input D2 to FF2. To obtain the output
, Z must be the
sequence 11011101 but time advanced by one unit, i.e., 10111011
We now observe that we have four distinct states for the system, i.e, four distinct set of
Q2 Q1 Q0
outputs
. Now we need to determine the logic expression for Z using these four
states and having the other states of the system act as dont care values. The K-Map of the
system is shown below.
K-Map
Z
Q1 Q0
Q2
0
1

0
0
1
1

0
1
1
1

1
1
1
0

1
0
1
1

This results in an expression Z = Q2+ Q1+ Q 0 = Q2 Q1 Q0

Thus the system may be described by the following Circuit diagram.


Circuit Diagram

100

Electronics Design Automation Laboratory

ALGORITHM
Step 1: Define entity sequence generator with inputs clock and reset, and output vector data
out.
Step 2: Define the entity architecture pair for D-flip-flop.
Step 3: Define the architecture for sequence generator. Declare the D flip-flop as a
component of the sequence generator. Also declare required signals.
Step 4: Inside a process triggered by the clock signal, assign the value NOT(Q2 AND Q1
AND Q0) to the signal Z.
Step 5: Outside the process, use the required port mapping statements to make the
connections as per the circuit diagram.
Step 6: End.

PROGRAM
This VHDL program is a combination of behavioral and structural modelling.

101

Electronics Design Automation Laboratory


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entityseqgen is
Port ( clk : IN std_logic;
RSTn : in std_logic;
data_out : out STD_LOGIC_VECTOR(2 downto 0));
endseqgen;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entitydff is
Port ( clk: in STD_LOGIC;
RSTn : in std_logic;
q :inout STD_LOGIC;
d : in STD_LOGIC);
enddff;

architecture Behavioral of dff is


begin
process(clk)
begin
ifclk'event and clk='1' then

102

Electronics Design Automation Laboratory

ifRSTn='1' then
q <= '1';
else
q <= d;
end if;
end if;
end process;
end Behavioral;

architecture Structural of seqgen is


COMPONENT dff
PORT(
clk : IN std_logic;
RSTn : in std_logic;
d : IN std_logic;
q : INOUT std_logic
);
END COMPONENT;

SIGNAL data_reg: STD_LOGIC_VECTOR(2 downto 0);


SIGNAL Z: STD_LOGIC;
begin
process(clk)

103

Electronics Design Automation Laboratory


begin
Z <= NOT(data_reg(0) AND data_reg(1) and data_reg(2));
end process;

dff2: dff PORT MAP(clk, RSTn, Z, data_reg(0));


dff1: dff PORT MAP(clk,RSTn, data_reg(0),data_reg(1));
dff0: dff PORT MAP(clk,RSTn, data_reg(1),data_reg(2));
data_out<= data_reg;
end Structural;
SIMULATION RESULT
The reset pulse is to be active for a clock period before it goes inactive. This starts the
sequence generator. Each of the outputs Q2, Q1 and Q0 (shown as [2], [1] and [0]) generates
delayed versions of the sequence 1101.

SYNTHESIZED HARDWARE

104

Electronics Design Automation Laboratory

The block dff is actually the shift register containing three d flip-flops.
RESULT
VHDL program for sequence generator was developed using a combination of behavioral
and structural modelling, simulated and verified the output waveform

105