designfeature By Thomas Neu, Texas Instruments

PRESERVE PC-BOARD SIGNAL INTEGRITY WITH THIS UNIQUE

METHOD FOR CREATING LAYER INTERCONNECTS (VIAS) THAT
CLOSELY MATCH THE SIGNAL-TRACE IMPEDANCE.

Designing controlledimpedance vias

s data-communication speeds increase be- calculated capacitances depend on the via diameters,
yond 3 Gbps, signal integrity becomes crucial the dielectric constant, and the distance between the
for successful data transmission. Board design- signal and ground via. The clearance (antipad) of the
ers try to eliminate every impedance mismatch along center via touches the outer vias so that the cathe high-speed signal path, because those disconti- pacitance is homogeneous along the vertical channuities generate jitter and decrease the data eye nelpreventing a dramatic capacitance increase at
openingnot only reducing the maximum possible every power and ground plane. The ground vias on
distance of data transmission, but also minimizing the outside provide the path for the signal-return
the margin to common jitter specifications, such as current and form an inductance loop between sigSONET (synchronous optical network) or XAUI nal and ground vias.
You can calculate the capacitance and inductance
(10-Gigabit attachment-unit interface).
Due to the increasing signal density on pc boards, formed by one ground via and the signal via with
more signal layers are necessary, and transitions with simple formulas (Reference 1). For the calculation,
layer interconnects (vias) become unavoidable. In you can assume that the two vias are essentially two
the past, vias represented a significant source of sig- wires of equal diameters. D is the diameter of one
nal distortion, because their impedance is usually via, and a is the center-to-center distance between
around 25 to 35. This large impedance disconti- the signal and the ground via. The inductance, L, of
nuity can reduce the data eye opening by as much one via pair calculates to:
as 3 dB and can create a significant amount of jitter

D
L = cosh1 .
depending on the data rate. As a result, board de 2a

signers have either tried to avoid vias on the highspeed lines or implemented new techniques, such
as counter boring or blind vias. Those methods help
but add complexity and greatly increase board cost.
You can eliminate the significant impedance mismatch of standard vias with a new coaxlike via
structure. This structure places ground vias around
the signal via in a special configuration. Vias designed with this technique show an impedance discontinuity of less than 4% (502) on a TDR
(time-domain-reflectometry) plot and improved
signal quality. This new approach creates a vertical
channel with a tunable impedance. Developers created the via structure using a simple coax model with
the signal wire in the center; the surrounding ground
shield builds a homogeneously distributed impedance. Four ground vias, which align in a ring
around the signal via in the center, replace the
Figure 1
uniform ground shield (Figure 1). Because
these outer vias connect to the pc-board ground or
VDD (supply), they carry a charge, and a capacitance New techniques for pc-board-layer-interconnect design provide predictable path
builds between each of them and the signal via. The impedance and improved signal integrity.

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October 2, 2003 | edn 67

designfeature Controlled-impedance vias

The capacitance C calculates to:

.
C=
D
h1
cosh
(1)
2a
Because the vertical channel, mainly
formed by the five vias, is homogeneous,
the impedance Z calculates to:
L
.
C
Equation 1 calculates the capacitance
in a standard two-wire system. The improved via structure adds three more
ground vias so that the amount of positive charges in the signal via stays the
same, but all the negative charges distribute evenly among the four ground
vias. Therefore, the overall capacitance of
the improved via structure is about the
same as that of a two-wire system. However, the inductance of this via model is
The yellow trace shows a TDR plot of a channel with a regular via. The green trace
one-quarter of the inductance of a
Figure 2
shows the TDR plot for a channel with a controlled-impedance via.
two-wire system, because four parallel inductance loops form between the
signal and the four ground vias, resulting ter of 14.5 mils and an antipad (clear- However, for a regular via, the match is
ance) of 10 mils, and the other channel good, and, according to this plot, you
in via impedance Z:
has the improved via structure with via should expect little signal distortion.
L
diameters of 14.5 mils and center-to-cenOne disadvantage of the TDR measZ=
.
4C
ter distances of 41 mils. The TDR plot urement is that the results are relative to
Experimenters tested this via structure shows that the impedance mismatch of the rise time of the equipment. It does
using FR4 polyclad 370, Getec, and the SMA connector is the same in both not show the frequency response of the
Rogers board materials on pc boards cases. The controlled-impedance via has discontinuity for discrete frequencies. A
varying from 60 mils and six layers thick an impedance of about 52, and the im- better way to demonstrate and compare
to 130 mils and 16 layers thick. They ver- pedance of the regular via is 48 to 54. the impedance mismatch of the vias is to
ified the calculated via impedance with The impedance match of the regular via look at the S21 scatter parameter on a
TDR measurements and a 3-D field is worse than that of the via structure. network analyzer (Figure 3). A plot of the
solver from CST (Computer SimFigure 3
ulation Technology). The formulas
they derived predict the impedance exceptionally well (2), regardless of the
board thickness, because the formula for
the via impedance is independent of the
board thickness. Table 1 compares calculated impedances for a six-layer, 62-mil
FR4 test board (er4.1) with the TDR
measurement results and simulated impedance values from the Microwave Studio 3-D field solver from CST. The calculated via impedances are within 2 of
the measured results.
A TDR plot is a good method for determining the impedance of vias or other discontinuities on a signal channel.
Figure 2 shows the TDR plot measured
on two almost-identical channels of the
test board. The only difference is that one This S21 plot shows the controlled-impedance-via channel in green and the regular-via channel in
channel has a regular via with a diame- yellow.
Z=

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designfeature Controlled-impedance vias

S21 shows how specific frereflection would appear at
quencies of the signal pass
the receiver, and another rethrough the transmissionflection would appear at the
line channel and how others
via closest to the transmitter.
get reflected or attenuated.
These reflections result in a
Figure 3 shows the S21 plot
lengthy distance from receivof the two channels in the
er to via to receiver, which
TDR measurement. They
again translates to a low resare identical, except that one
onance frequency.
channel has the via strucThe second S21 measureture (green curve), and the
ment conclusion is that
other channel has a
the signal-return current
Figure 4
regular via (yellow
contributes a considerable
curve). The via structure
amount of reflection. The
shows an exceptional freS21 measurement in Figure
quency response, and the
3 shows two almost-identifirst resonances are visible at Experimenters developed a test board with both standard and improved
cal channels that differ only
about 10 GHz. The regular impedance vias to measure signal performance.
in their signal-return path
via, on the other hand,
and a slightly different imshows multiple reflections over the entire
pedance mismatch. The S21 plot shows
1
frequency band, even though the imped- f VIA = 2 DISTANCE PROPAGATION DELAY = more reflections at the absence of this
ance mismatch is small. These reflections
close return path for the regular via be1
= 2.35 GHz.
cause certain frequencies of a signal to be
cause the signal-return current takes the
pSEC
2 1.4 IN. 150
IN.
(2) closest, least inductive path available,
more attenuated than others, thus further degrading the high-speed signal.
even if it is an inch away, thereby causf VIA SMA =
On this test board (Figure 4), the dising resonances.
1
tance between the SMA connectors and
The signal-return current could flow
= 4.8 GHz.
pSEC
2 0.7 IN. 150
(3) through the inner-plane capacitance of
the via is about 1.4 in., which equates to
IN.
a frequency of about 2.35 GHz (using
adjacent power and ground planes, but
f
R
ETURNPATH
(
SMA
SMA ) =
Equation 2) that is clearly visible in the
that capacitance is usually so small that
1
S21 plot. Although the frequency reonly high frequencies can pass. In most
= 2 GHz.
pSEC
(4) cases, the signal-return current flows
sponse of discontinuities for an asym2 1.6 IN. 150
metrical channel may differ slightly, the
through the closest via that connects the
IN.
channels are designed to be symmetric.
The first conclusion you can draw reference layers of the signal trace. Those
The signal-return-current path mainly from the S21 measurement is that the return-current vias can be far from the
causes the other reflections on the yellow, resonance frequency depends greatly on actual signal via (Figure 5). To demonregular-via curve.
the location of the discontinuity on the strate this effect, experimenters placed a
Because the regular via provides no transmission line. This statement does ground via approximately 100 mils from
path for the signal-return current, the not imply that you should place the via the regular via and plotted the current
current takes the least inductive path close to the transmitter or connector so density in a controlled-impedance via
closest to the regular via. The signal-re- that the impedance mismatch appears at (Figure 5a) with the current density for
turn current flows through the ground frequencies greater than 10 GHz. Unfor- the structure (Figure 5b). It is clear that
vias of the SMA connector and through tunately, in practice, this approach would most of the return current flows through
the ground-via structure of the adjacent work only if there were a perfect imped- the added ground via some distance away.
channel. Because the return current takes ance match at the receiver. Otherwise, a This extra distance for the return current
the closest path, resonance frequencies in
the S21 plot are, as you would expect, at
about 5 GHz (0.7 in.) and not at 4.2 GHz
(0.8 in.). Furthermore, the return current
flows from the ground vias of that SMA
to the far-end SMA connector (an approximately 1.6-in.-long current path),
Figure 5
causing another resonance at about 2
GHz (equations 3 and 4). You can clearly observe both phenomena, which the
return current causes, in the S21 plot.
(b)
The following equations calculate the (a)
A
plot
comparing
the
current
densities
for
the
controlled-impedance
via (a) and the regular via (b)
resonance frequencies of the channel
shows that the return current flows through the added ground via some distance away.
with the regular via:

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designfeature Controlled-impedance vias

causes reflections that appear in
tance results, due to the pads, and
the S21 plot.
increases the capacitance, which reThe impact of broadband reduces the overall impedance.
flections becomes more visible
In a typical design, four ground
when you examine a real data
vias are not always available. The via
signal with a wide frequency
structure works equally well with
spectrum, such as a PRBS
power vias as long as the return cur(pseudorandom-bit-stream)
rent has a path from VDD to
Figure 6
ground through a nearby bypattern. To illustrate this impass capacitor.
pact, experimenters sent a 271
PRBS pattern at 3.125 Gbps
For example, consider boards
through both channels and
that contain this via structure inrecorded the output waveforms
side a BGA pinout with a 1-mm
(Figure 6). The channels are
grid. Because of the fixed pinout,
only 2.8 in. long, but the impact A data-eye plot of a bit stream shows that the regular via (yellow you may connect only two outer
of the vias is clearly visible. The curve) attenuates multiple frequencies, resulting in a smaller data vias to ground; you connect the
regular via (yellow curve) atten- eye and a slower rise time than does a controlled-impedance via
other two vias to VDD. The via
structure works well because you
uates multiple frequencies, re- (green curve).
can also place SMD bypass capacisulting in a smaller data eye and
a slower rise time than a controlled-im- important frequency, and the stub be- tors between VDD and ground inside the
pedance via (green curve).
comes a short circuit for that frequency, BGA.
You can also use the via structure for
Finally, the impedance mismatch canceling out the original signal.
should be as small as possible. Even the
The above equations assume that the differential signals. The signals can share
smallest mismatch shows up at one dis- diameter is the same for the signal and the the two outer vias, saving board space.
crete frequency on the S21 plot and im- ground vias. To use different diameters, Texas Instruments uses this method on
pact the signal quality. You can maximize you need to modify the formula for the ca- the evaluation boards for its XAUI transthe performance of controlled-impedance pacitance. Designers should choose the via ceivers, which offer limited space inside
vias by following important design pa- diameters according to the width of the the BGA. For controlled-impedance vias,
rameters, such as spacing, trace widths, connected traces. If the trace is much the size of the layer separation does not
and pad widths. For example, the antipad, smaller than the via, the transition from matter, because the ground vias and not
or clearance size, of the signal via is criti- the 50 trace to the via pad causes an un- the metal layers form the capacitance.
cal. It must be at least the difference of dis- wanted discontinuity. Designers should Regular vias, however, depend on the catance between signal and ground via, a, also consider the distance between the pacitance from the layers. Therefore, you
and the via diameter, D, so that the signal- ground vias and the connected trace. It must design them specifically for differvia antipad touches the ground via. Oth- can become an issue when the separation ent layer stackups even if the board thickerwise, the metal on the ground, power between the ground via and the trace is ness does not change.
layer, or both comes too close to the signal smaller than the distance between the
via and creates additional unwanted ca- trace and the reference layer, creating ad- Reference
1. Pozar, David M, Microwave Engipacitance thereby reducing the via im- ditional capacitance for the trace and
pedance to less than the calculated 50.
again dropping the trace impedance to neering, Second Edition, John Wiley &
Likewise, every via that connects a mi- less than 50. On the test board, for ex- Sons Inc, 1998, pg 62.
crostrip line on the top or the bottom lay- ample, the distance between the signal
er with a stripline on an inner layer creates trace and the ground vias is about 11 mils, Authors bio graphy
a stub. When the stub length is smaller and the trace is about 10 mils above the Thomas Neu is an application engineer
for high-speed serial links at Texas Instruthan the signal rise time, the stub is bare- ground-reference layer.
ments, where he handles
ly noticeable. If the stub length is longer,
Another important design consideracustomer support for TI
it can cause considerable signal distortion. tion is pad size, because every via that conSERDES devices and RF reFor example, a stub of 40 mils has a run nects to a trace requires a pad. This pad
search. He has a diploma in
length of about 14 psec in a system with a should be as small as possible, because the
engineering from the Univer3.125-Gbps signal with a rise time of ap- distance from the pad to the ground vias
sity of Applied Sciences in
proximately 50 psec. In the worst case, the is smaller than the distance from the sigLandshut, Germany.
stub length is a quarter- wavelength of an nal via to the ground vias. A shorter dis-

TABLE 1COMPARISON OF CALCULATED, SIMULATED, AND MEASURED VIA IMPEDANCE

Diameter (mils)
Distance from signal-via center to ground-via center (mils)
Calculated impedance ()
Simulated impedance ()
Measured impedance ()

72 edn | October 2, 2003

14.5
41
50.3
51.2
52

43
51.8
52
54

45
53.3
52.1
55

12
32
48.5
51.5
50

34
50.4
51.6
51

36
52.2
51.6
53
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