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5 4 3 2 1 Model : H12YV1 Rev:A D D Intel Yonah/Merom+Calistoga 945GM+ICH7-M Revision
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4
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Model : H12YV1 Rev:A
D
D
Intel Yonah/Merom+Calistoga 945GM+ICH7-M
Revision History
A
2006/11/24
ORIGINAL RELEASE
C
C
PCB STACK UP
B
B
LAY1
TOP
LAY2
GND1
LAY3
IN1
LAY4
IN2
PG01 Cover Page
PG02 Block Diagram
PG03 Yonah (HOST)
PG04 Yonah (POWER)
PG05 CPU POWER
PG06 Calistoga (HOST/IGDS/DMI)
PG07 Calistoga (DDR2 I/F)
PG08 Calistoga (PWR/NCTF)
PG09 Calistoga (PWR/GND)
PG10 DDR2 SO-DIMM
PG11 CRT/LCD CON
PG12 ICH7-M (GTL+/DMI/PCI)
PG13 ICH7-M (PM/GPIO/LPC/IO)
PG14 ICH7-M (PWR/GND)
PG15 System Pull Up/Down
PG16 CLK GEN
PG17 HDD/CDROM CON
PG18 LAN
PG19 MINIPCI CON
PG20 1394+CardReader Controller
PG21 Audio Codec
PG22 Audio Amp
PG23 KBC M38857 KB
PG24 LPC (TPM/DEBUG CON)/FAN
PG25 I/O (1394/SATA/MDC/BT/USB)
PG26 PCI-E NEWCARD
PG27 PCI-E MINICARD
PG28 LED
PG29 PWR/WL/BT ON_OFF
PG30 PWR (3V/5V)
PG31 PWR (0.9V_SW/1.8V)
PG32 PWR(VCC_P/1.5V_SW/2.5V_SW)
LAY5
VCC
LAY6
IN3
LAY7
GND2
PG33 PWR OK
PG34 DC IN/CHARGE
PG35 SPARE PARTES
PG36 POWER SEQUENCE
LAY8
BOTTOM
A
PG37 POWER DIAGRAM
PG38 History
A
Project Name
Project Name
Project Name
H12YV1
H12YV1
H12YV1
Pag Title
Pag Title
Pag Title
Cover Page
Document
Document
Document
Rev
Rev
Rev
82+A32000+00A
82+A32000+00A
82+A32000+00A
Number
Number
Number
A
A
A
Sheet 1
Sheet
Sheet 1 1
Date:
Date:
Date:
Friday, November 24, 2006
Friday, November 24, 2006
Friday, November 24, 2006
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5 4 3 2 1 H12YT1 System Block Diagram Yonah/ Merom Differential 100MHz(GMCH/ICH7-M/ NEWCARD/MINICARD/SATA) (TBD)
5
4
3
2
1
H12YT1 System Block Diagram
Yonah/
Merom
Differential 100MHz(GMCH/ICH7-M/
NEWCARD/MINICARD/SATA)
(TBD)
CPU TEMP
96MHz(GMCH)
THERMDA/C
Differential
MONITOR
Micro-FCPGA 478
48MHz(ICH7-M/Debug Port)
133/166MHz
MAX6692
CLK GEN
33MHz(ICH7-M/1394/LAN/KBC
PG03,04
PG04
ICS954226
D
/Debug Port/MINIPCI)
D
AGTL+ BUS
14.318MHz
533/667MHz(Yonah)
667MHz(Merom Only)
DDR2 SO-DIMM x1
PG16
PG11
Differential
133/166MHz
LVDS
DDR2-A 400MHz/533MHz/667MHz
12.1" Wide XGA
TFT LCD Panel
Calistoga
DDR2 Single Channel
945GM
CRT
ODD
RGB
Micro-FCBGA 1466
CON
PG06,07,08,09
PG10
PG17
DMI
PG11
C
SATA HDD
C
USB 2.0
IDE
PG17
PG25
PG25
Port 0
Port 2, 4, 6
PG21
SATA
Bluetooth
USB
Module
PORT*3
HD Audio
ICH7-M
HD Audio
PCI Express
CODEC
PG27
PG26
ALC262
mBGA652
Port 1
Port 1
Port 2
Port 7
PCI Express
NEWCARD
SPI
Mini Card
CON
PCI 2.3
AMP
AMP
LM833MMX
MDC
MAX4411
MAX9710
PG12,13,14
PG22
PG22
PG25
Flash ROM
LPC
PG13
SPK
SPK
B
B
MINIPCI CON
IEEE1394 +
RJ11
TPM
KBC
LAN REALTEK
(Reserve For
CardReader
INT_MIC
Jack
1.2
M38857
RTL8100CL
Debug
Controller
EXT_MIC
E.phone
PG22
Daughter Board
PG24
Function)
OZ128TN
PG22
PG22
PG23
PG18
PG19
PG20
IEEE
SMBus Diagram
RJ45
1394
Touch
Jack
Port
Clock Gen
KeyBoard
Pad
4 in 1
Card
Reader
Conn
SMBICH_
SMBICH_SW
PG25
CLK/DATA
CLK/DATA
DDR2
PG18
SMBus
ICH7-M
Daughter Board
Switch
SO-DIMM
SMBus
PCI-E
Charger PWM
Switch
NEWCARD
Controller
PWR_RCLKEN
A
PCI-E
PG34
A
MINICARD
BATTERY
SMB_KBC_CLK/DATA
Project Name
Project Name
Project Name
CPU FAN
H12YV1
H12YV1
H12YV1
Battery
Pag Title
Pag Title
Pag Title
KBC
MAX6692
PG24
Block Diagram
Thermal Sensor
Document
Document
Document
Rev
Rev
Rev
M38857
82+A32000+00A
82+A32000+00A
82+A32000+00A
Number
Number
Number
A
A
A
Sheet 2
Sheet 2
Sheet 2
Date:
Date:
Date:
Friday, November 24, 2006
Friday, November 24, 2006
Friday, November 24, 2006
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38
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MIC In
Line Out
5 4 3 2 1 6 AGTL+_REQ#[0:4] AGTL+_D#[0:63] 6 Layout note of COMP0,2 : 18mil
5
4
3
2
1
6
AGTL+_REQ#[0:4]
AGTL+_D#[0:63]
6
Layout note of COMP0,2 : 18mil wide traces and
shorter than 0.5'' traces.
U54A
U54A
AGTL+_REQ#0
AGTL+_D#0
K3
E22
REQ0#
D0#
AGTL+_REQ#1
AGTL+_D#1
Layout note of COMP1,3 : 5mil wide trace and shorter
than 0.5" trace.
H2
F24
REQ1#
D1#
AGTL+_REQ#2
AGTL+_D#2
K2
E26
REQ2#
D2#
AGTL+_REQ#3
AGTL+_D#3
J3
H22
U54B
U54B
REQ3#
D3#
AGTL+_REQ#4
AGTL+_D#4
L5
F23
6
AGTL+_A#[3:31]
REQ4#
D4#
AGTL+_D#5
COMP0
R578R578
27.4_1%27.4_1%
0402R0402R
G25
R26
D5#
COMP0
AGTL+_A#3
AGTL+_D#6
COMP1
J4
E25
U26
R577R577
54.9_1%54.9_1%
0402R0402R
A3#
D6#
COMP1
AGTL+_A#4
AGTL+_D#7
COMP2
R138R138
27.4_1%27.4_1%
0402R0402R
L4
E23
A6
U1
A4#
D7#
12
CPU_A20M#
A20M#
COMP2
AGTL+_A#5
AGTL+_D#8
COMP3
M3
K24
B5
V1
R139R139
54.9_1%54.9_1%
0402R0402R
A5#
D8#
12
CPU_DPSLP#
DPSLP#
COMP3
AGTL+_A#6
AGTL+_D#9
K5
G24
A5
A6#
D9#
12
CPU_FERR#
D
FERR#/PBE#
D
AGTL+_A#7
AGTL+_D#10
BPM#0
M1
J24
C4
AD4
A7#
D10#
12
CPU_IGNNE#
IGNNE#
BPM0#
TP8TP8
AGTL+_A#8
AGTL+_D#11
BPM#1
N2
J23
B3
AD3
A8#
D11#
12
CPU_INIT#
INIT#
BPM1#
TP3TP3
AGTL+_A#9
AGTL+_D#12
BPM#2
J1
H26
C6
AD1
A9#
D12#
12
CPU_INTR
LINT0/INTR
BPM2#
TP5TP5
AGTL+_A#10
AGTL+_D#13
BPM#3
N3
F26
B4
AC4
A10#
D13#
12 CPU_NMI
LINT1/NMI
BPM3#
TP7TP7
AGTL+_A#11
AGTL+_D#14
P5
K22
D6
A11#
D14#
12
CPU_PWRGD
PWRGOOD
AGTL+_A#12
AGTL+_D#15
P2
H25
A12#
D15#
AGTL+_A#13
AGTL+_D#16
L1
N22
D7
A13#
D16#
6
CPU_CPUSLP#
R238 for A0, A1, B0
Stepping used
SLP#
AGTL+_A#14
AGTL+_D#17
P4
K25
A3
A14#
D17#
12
CPU_SMI#
SMI#
AGTL+_A#15
AGTL+_D#18
P1
P26
D5
C26
R579R579
1K_1%_OP1K_1%_OP
0402R0402R
A15#
D18#
12
CPU_STPCLK#
STPCLK#
TEST1
AGTL+_A#16
AGTL+_D#19
R238R238
51_1%51_1%
0402R0402R
R1
R23
D25
A16#
D19#
TEST2
AGTL+_A#17
AGTL+_D#20
Y2
L25
AE6
A17#
D20#
5
PM_PSI#
PSI#
AGTL+_A#18
AGTL+_D#21
U5
L22
A18#
D21#
AGTL+_A#19
AGTL+_D#22
R230R230
1K_1%1K_1%
0402R0402R
R3
L23
E5
5,13
PM_DPRSTP#
A19#
D22#
DPRSTP#
AGTL+_A#20
AGTL+_D#23
W6
M23
A20#
D23#
AGTL+_A#21
AGTL+_D#24
Strapping option
U4
P25
B22
A21#
D24#
BSEL0
BSEL0
8,16
AGTL+_A#22
AGTL+_D#25
Y5
P22
B23
A22#
D25#
BSEL1
BSEL1
8,16
AGTL+_A#23
AGTL+_D#26
U2
P23
A22
C21
16 CLK_CPU_BCLK
A23#
D26#
BCLK0
BSEL2
BSEL2
8,16
AGTL+_A#24
AGTL+_D#27
R237R237
1K_1%1K_1%
0402R0402R
R4
T24
A21
16
CLK_CPU_BCLK#
A24#
D27#
BCLK1
AGTL+_A#25
AGTL+_D#28
T5
R24
R236R236
1K_1%1K_1%
0402R0402R
VCC_P
A25#
D28#
AGTL+_A#26
AGTL+_D#29
T3
L26
A26#
D29#
AGTL+_A#27
AGTL+_D#30
CPU_TCK
W3
T25
AC5
A27#
D30#
TCK
AGTL+_A#28
AGTL+_D#31
CPU_TDI
W5
N24
AA6
A28#
D31#
TDI
AGTL+_A#29
AGTL+_D#32
CPU_TDO
Y4
AA23
A24
AB3
A29#
D32#
4
THERMDA
THERMDA
TDO
AGTL+_A#30
AGTL+_D#33
CPU_TMS
W2
AB24
A25
AB5
A30#
D33#
4
THERMDC
THERMDC
TMS
AGTL+_A#31
AGTL+_D#34
R181
R181
0_5%
0_5%
CPU_THERMTRIP#
Y1
V24
C7
A31#
D34#
6,13
PM_THERMTRIP#
THERMTRIP#
AGTL+_D#35
0402R
0402R
CPU_PROCHOT#
CPU_TRST#
V26
D21
AB6
D35#
5
CPU_PROCHOT#
PROCHOT#
TRST#
HOST BUS
HOST BUS
AGTL+_D#36
W25
D36#
AGTL+_D#37
BPM#4
U23
AC2
D37#
PRDY#
TP2TP2
AGTL+_D#38
PM_SYS_RESET#
U25
R222
R222
0_5%_OP
0_5%_OP
CPU_DBR#
BPM#5
C20
AC1
6 AGTL+_ADSTB#[0:1]
13 PM_SYS_RESET#
D38#
DBR#
PREQ#
TP4TP4
AGTL+_D#39
0402R
0402R
C
U22
C
D39#
AGTL+_ADSTB#0
AGTL+_D#40
L2
AB25
D24
6
AGTL+_DPWR#
ADSTB0#
D40#
DPWR#
AGTL+_ADSTB#1
AGTL+_D#41
V4
W22
AA1
ADSTB1#
D41#
RSVD1
AGTL+_D#42
Y23
AA4
D42#
RSVD2
AGTL+_D#43
AA26
R279R279
0_5%0_5%
0402R0402R
VID0
AD6
AB2
D43#
5
CPU_VID0
VID0
RSVD3
AGTL+_D#44
R280R280
0_5%0_5%
0402R0402R
VID1
Y26
AF5
AA3
D44#
5
CPU_VID1
VID1
RSVD4
AGTL+_D#45
R283R283
0_5%0_5%
0402R0402R
VID2
Y22
AE5
M4
D45#
5
CPU_VID2
VID2
RSVD5
AGTL+_D#46
R284R284
0_5%0_5%
0402R0402R
VID3
H1
AC26
AF4
N5
A#[32-39], APM#[0-1]:
6
AGTL+_ADS#
ADS#
D46#
5
CPU_VID3
VID3
RSVD6
AGTL+_D#47
R281R281
0_5%0_5%
0402R0402R
VID4
E2
AA24
AE3
T2
6
AGTL+_BNR#
BNR#
D47#
5
CPU_VID4
VID4
RSVD7
AGTL+_D#48
G5
AC22
R285R285
0_5%0_5%
0402R0402R
VID5
AF2
V3
6
AGTL+_BPRI#
BPRI#
D48#
5
CPU_VID5
VID5
RSVD8
Leave escape routing on for
future functionality
AGTL+_D#49
R282R282
0_5%0_5%
0402R0402R
VID6
F1
AC23
AE2
B2
6
AGTL+_BR0#
BR0#
D49#
5
CPU_VID6
VID6
RSVD9
AGTL+_D#50
E1
AB22
C3
6
AGTL+_DBSY#
DBSY#
D50#
Yonah(120mA)
RSVD10
AGTL+_D#51
H5
AA21
B26
6
AGTL+_DEFER#
VCC1_5_SW
DEFER#
D51#
VCCA
AGTL+_D#52
F21
AB21
Merom(130mA)
B25
6
AGTL+_DRDY#
DRDY#
D52#
RSVD11
AGTL+_D#53
G6
AC25
C273
C273
C252
C252
6
AGTL+_HIT#
HIT#
D53#
AGTL+_D#54
10U_Y5V
10U_Y5V
0.01U_X7R
0.01U_X7R
E4
AD20
T22
6
AGTL+_HITM#
HITM#
D54#
RSVD12
AGTL+_D#55
0805C
0805C
0402C
0402C
H4
AE22
6
AGTL+_LOCK#
LOCK#
D55#
AGTL+_D#56
G2
AF23
Close to PIN B26
D2
6
AGTL+_TRDY#
TRDY#
D56#
RSVD13
AGTL+_D#57
AD24
F6
D57#
RSVD14
AGTL+_D#58
AE21
D3
6
AGTL+_RS#[0:2]
D58#
RSVD15
AGTL+_RS#0
AGTL+_D#59
VCC_P
F3
AD21
C1
RS0#
D59#
RSVD16
AGTL+_RS#1
AGTL+_D#60
F4
AE25
AF1
RS1#
D60#
RSVD17
AGTL+_RS#2
AGTL+_D#61
G3
AF25
D22
RS2#
D61#
RSVD18
AGTL+_D#62
AF22
C23
D62#
RSVD19
AGTL+_CPURST#
AGTL+_D#63
B1
AF26
C24
R576
R576
6
AGTL+_CPURST#
RESET#
D63#
AGTL+_DINV#[0:3]
6
RSVD20
1K_1%
1K_1%
CPU_IERR#
AGTL+_DINV#0
0402R
0402R
D20
J26
AF7
A2
IERR#
DINV0#
5
VCCSENSE
VCCSENSE
NC
AGTL+_DINV#1
M26
DINV1#
AGTL+_DINV#2
CPU_GTLREF
V23
AE7
AD26
DINV2#
5
VSSSENSE
VSSSENSE
GTLREF
AGTL+_DINV#3
AC20
GTLREF= 2/3*VCCP+-2%
B
DINV3#
AGTL+_DSTBP#[0:3]
6
B
0.5" max length
AGTL+_DSTBP#0
Yonah
Yonah
R575
R575
G22
DSTBP0#
AGTL+_DSTBP#1
N25
MFCPGA479
MFCPGA479
2K_1%
2K_1%
DSTBP1#
AGTL+_DSTBP#2
VCCSENSE/VSSSENSE
trace width & space 18mil/7mil
, Length match to within 25mils
0402R
0402R
Y25
DSTBP2#
AGTL+_DSTBP#3
AE24
DSTBP3#
AGTL+_DSTBN#[0:3]
6
AGTL+_DSTBN#0
H23
DSTBN0#
AGTL+_DSTBN#1
M24
DSTBN1#
AGTL+_DSTBN#2
W24
DSTBN2#
AGTL+_DSTBN#3
AD23
DSTBN3#
Yonah/Merom CPU BSEL[2:0]
Yonah
Yonah
BSEL[2]
BSEL[1]
BSEL[0]
BCLK frequency
MFCPGA479
MFCPGA479
L
L
L
Reserved
L
L
H
133MHz(Yonah Only)
VCC_P
3.0" max length
L
H
L
Reserved
R232R232
75_1%75_1%
0402R0402R
CPU_PROCHOT#
L
H
H
166MHz
R231R231
56_1%56_1%
0402R0402R
CPU_IERR#
2.0" max length
R184R184
150_1%150_1%
0402R0402R
CPU_TDI
R183R183
39_1%39_1%
0402R0402R
CPU_TMS
R182R182
51_1%_OP51_1%_OP
0402R0402R
CPU_TDO
A
R137R137
51_1%_OP51_1%_OP
0402R0402R
AGTL+_CPURST#
A
R223R223
150_1%_OP150_1%_OP
0402R0402R
CPU_DBR#
R168R168
27.4_1%27.4_1%
0402R0402R
CPU_TCK
R169R169
680_1%680_1%
0402R0402R
CPU_TRST#
Project Name
Project Name
Project Name
H12YV1
H12YV1
H12YV1
ITP Debug port not used strapping option
Pag Title
Pag Title
Pag Title
Yonah (HOST)
Document
Document
Document
Rev
Rev
Rev
82+A32000+00A
82+A32000+00A
82+A32000+00A
Number
Number
Number
A
A
A
Sheet 3
Sheet 3
Sheet 3
Date:
Date:
Date:
Friday, November 24, 2006
Friday, November 24, 2006
Friday, November 24, 2006
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of
of
38
38
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5
4
3
2
1
VID
VID
CLKTHM
CLKTHM
ICH
ICH
RESERVE
RESERVE
JTKDEB
JTKDEB
220U_2V_SPCAP 220U_2V_SPCAP 5 4 3 2 1 VCC_CORE U54D U54D U54C U54C A4 P6 A7
220U_2V_SPCAP
220U_2V_SPCAP
5
4
3
2
1
VCC_CORE
U54D
U54D
U54C
U54C
A4
P6
A7
V6
VSS0
VSS81
VCC0
VCCP0
A8
P21
A9
G21
D
VSS1
VSS82
VCC1
VCCP1
D
A11
P24
A10
J6
during power up, Iccp for Yonah processor can spike up to 6.0
A, Once core Vcc is enabled, Iccp max spec of 2.5 A still applies
VSS2
VSS83
VCC2
VCCP2
A14
R2
A12
K6
VSS3
VSS84
VCC3
VCCP3
VCC_P
A16
R5
A13
M6
Yonah(2.5A)
VSS4
VSS85
VCC4
VCCP4
A19
R22
A15
J21
VSS5
VSS86
VCC5
VCCP5
Merom(2A)
A23
R25
A17
K21
VSS6
VSS87
VCC6
VCCP6
A26
T1
A18
M21
VSS7
VSS88
VCC7
VCCP7
B6
T4
A20
N21
VSS8
VSS89
VCC8
VCCP8
C179
C179
C180
C180
C181
C181
C244
C244
C246
C246
C247
C247
C245
C245
C503
C503
C484
C484
V13
V13
B8
T23
B7
N6
VSS9
VSS90
VCC9
VCCP9
B11
T26
B9
R21
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
39P_NPO
39P_NPO
10U_X5R
10U_X5R
10U_X5R
10U_X5R
1000P_2.5K
1000P_2.5K
VSS10
VSS91
VCC10
VCCP10
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0805C
0805C
0805C
0805C
1206C
1206C
B13
U3
B10
R6
VSS11
VSS92
VCC11
VCCP11
B16
U6
B12
T21
VSS12
VSS93
VCC12
VCCP12
B19
U21
B14
T6
VSS13
VSS94
VCC13
VCCP13
B21
U24
B15
V21
VSS14
VSS95
VCC14
VCCP14
B24
V2
B17
W21
VSS15
VSS96
VCC15
VCCP15
C5
V5
B18
VSS16
VSS97
VCC16
C8
V22
B20
AB9
VSS17
VSS98
VCC17
VCC59
C11
V25
C9
AC10
VSS18
VSS99
VCC18
VCC60
C14
W1
C10
AB10
VSS19
VSS100
VCC19
VCC61
C16
W4
C12
AB12
VSS20
VSS101
VCC20
VCC62
C19
W23
C13
AB14
VSS21
VSS102
VCC21
VCC63
Yonah (36A)
VCC_CORE
C2
W26
C15
AB15
VSS22
VSS103
VCC22
VCC64
C22
Y3
C17
AB17
VSS23
VSS104
VCC23
VCC65
Merom (44A)
C25
Y6
C18
AB18
VSS24
VSS105
VCC24
VCC66
D1
Y21
D9
AB20
VSS25
VSS106
VCC25
VCC
VCC
VCC67
C485
C485
C492
C492
C493
C493
C496
C496
C497
C497
C504
C504
C505
C505
C483
C483
C208
C208
+ C486
C486
D4
Y24
D10
AB7
+
VSS26
VSS107
VCC26
VCC68
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
39P_NPO
39P_NPO
C_D
C_D
D8
AA2
D12
AC7
VSS27
VSS108
VCC27
VCC69
D11
AA5
D14
AC9
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0402C
0402C
VSS28
VSS109
VCC28
VCC70
D13
AA8
D15
AC12
VSS29
VSS110
VCC29
VCC71
D16
AA11
D17
AC13
VSS30
VSS111
VCC30
VCC72
C
D19
AA14
D18
AC15
C
VSS31
VSS112
VCC31
VCC73
D23
AA16
E7
AC17
VSS32
VSS113
VCC32
VCC74
D26
AA19
E9
AC18
VSS33
VSS114
VCC33
VCC75
E3
AA22
E10
AD7
VSS34
VSS115
VCC34
VCC76
E6
AA25
E12
AD9
C490
C490
C491
C491
C494
C494
C495
C495
C501
C501
C502
C502
C192
C192
C204
C204
C205
C205
VSS35
VSS116
VCC35
VCC77
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
E8
AB1
E13
AD10
VSS36
VSS117
VCC36
VCC78
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
E11
AB4
E15
AD12
VSS37
VSS118
VCC37
VCC79
E14
AB8
E17
AD14
VSS38
VSS119
VCC38
VCC80
E16
VSS
VSS
AB11
E18
AD15
VSS39
VSS120
VCC39
VCC81
E19
AB13
E20
AD17
VSS40
VSS121
VCC40
VCC82
E21
AB16
F7
AD18
VSS41
VSS122
VCC41
VCC83
E24
AB19
F9
AE9
VSS42
VSS123
VCC42
VCC84
F5
AB23
F10
AE10
VSS43
VSS124
VCC43
VCC85
C214
C214
C215
C215
C236
C236
C206
C206
C207
C207
C216
C216
C217
C217
C237
C237
F8
AB26
F12
AE12
VSS44
VSS125
VCC44
VCC86
F11
AC3
F14
AE13
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
10U_X5R
VSS45
VSS126
VCC45
VCC87
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
0805C
F13
AC6
F15
AE15
VSS46
VSS127
VCC46
VCC88
F16
AC8
F17
AE17
VSS47
VSS128
VCC47
VCC89
F19
AC11
F18
AE18
VSS48
VSS129
VCC48
VCC90
F2
AC14
F20
AE20
VSS49
VSS130
VCC49
VCC91
F22
AC16
AA7
AF9
VSS50
VSS131
VCC50
VCC92
F25
AC19
AA9
AF10
VSS51
VSS132
VCC51
VCC93
G4
AC21
AA10
AF12
VSS52
VSS133
VCC52
VCC94
G1
AC24
AA12
AF14
VSS53
VSS134
VCC53
VCC95
C191
C191
C235
C235
C193
C193
C248
C248
V3
V3
G23
AD2
AA13
AF15
VSS54
VSS135
VCC54
VCC96
G26
AD5
AA15
AF17
1000P_X7R
1000P_X7R
1000P_X7R
1000P_X7R
1000P_X7R
1000P_X7R
1000P_X7R
1000P_X7R
1000P_2.5K
1000P_2.5K
VSS55
VSS136
VCC55
VCC97
0402C
0402C
0402C
0402C
0402C
0402C
0402C
0402C
1206C
1206C
H3
AD8
AA17
AF18
VSS56
VSS137
VCC56
VCC98
H6
AD11
AA18
AF20
VSS57
VSS138
VCC57
VCC99
H21
AD13
AA20
For EMI
VSS58
VSS139
VCC58
H24
AD16
VSS59
VSS140
J2
AD19
Yonah
Yonah
B
VSS60
VSS141
B
MFCPGA479
MFCPGA479
J5
AD22
VSS61
VSS142
J22
AD25
VSS62
VSS143
J25
AE1
VSS63
VSS144
K1
AE4
VSS64
VSS145
K4
AE8
VSS65
VSS146
K23
AE11
VSS66
VSS147
K26
AE14
VSS67
VSS148
L3
AE16
VSS68
VSS149
L6
AE19
VSS69
VSS150
L21
AE23
VSS70
VSS151
L24
AE26
VSS71
VSS152
M2
AF3
VSS72
VSS153
M5
AF6
VSS73
VSS154
M22
AF8
VSS74
VSS155
M25
AF11
VSS75
VSS156
N1
AF13
VSS76
VSS157
R568R568
200_1%200_1%
0402R0402R
VCC3_CPUTS
N4
AF16
VCC3
VSS77
VSS158
N23
AF19
VSS78
VSS159
C507
C507
N26
AF21
VSS79
VSS160
P3
AF24
R570
R570
1U_Y5V
1U_Y5V
VSS80
VSS161
10K_5%
10K_5%
0603C
0603C
Yonah
Yonah
0402R
0402R
MFCPGA479
MFCPGA479
U58
U58
1 8
VCC
SCLK
SMB_KBC_CLK
23,34
7
3
THERMDA
3 2 DXP
SDA
SMB_KBC_DATA
23,34
R569
R569
0_5%_OP
0_5%_OP
6
3
THERMDC
4 DXN
ALERT#
PM_THRM# 13,15
5
0402R
0402R
OVERT# GND
C508
C508
2200P_X7R
2200P_X7R
A
0402C
0402C
MAX6692MUA+
MAX6692MUA+
A
uSOIC8
uSOIC8
29 PM_THRM_SHUTDOWN#
Route THERMDA and THERMDC on same layer.
10mil trace/10mil spacing
Project Name
Project Name
Project Name
H12YV1
H12YV1
H12YV1
Pag Title
Pag Title
Pag Title
Yonah (POWER)
Document
Document
Document
Rev
Rev
Rev
82+A32000+00A
82+A32000+00A
82+A32000+00A
Number
Number
Number
A
A
A
Sheet 4
Sheet 4
Sheet 4
Date:
Date:
Date:
Friday, November 24, 2006
Friday, November 24, 2006
Friday, November 24, 2006
of
of
of
38
38
38
5
4
3
2
1
330U_2V_SPCAP_OP 330U_2V_SPCAP_OP 330U_2V_SPCAP_OP 330U_2V_SPCAP_OP SEC_7343 SEC_7343 SEC_7343 SEC_7343
330U_2V_SPCAP_OP
330U_2V_SPCAP_OP
330U_2V_SPCAP_OP
330U_2V_SPCAP_OP
SEC_7343
SEC_7343
SEC_7343
SEC_7343
330U_2V_SPCAP
330U_2V_SPCAP
330U_2V_SPCAP
330U_2V_SPCAP
SEC_7343
SEC_7343
SEC_7343
SEC_7343
330U_2V_SPCAP
330U_2V_SPCAP
330U_2V_SPCAP
330U_2V_SPCAP
SEC_7343
SEC_7343
SEC_7343
SEC_7343
U52
U52
U57
U57
N
N
N
N
5
4
3
2
1
VIN
N
N
IRF8113PBF_OP
IRF8113PBF_OP
N
N
IRF8113PBF_OP
IRF8113PBF_OP
SOIC8
SOIC8
SOIC8
SOIC8
VCC5_SW
U51
U51
U56
U56
D14
D14
Modify RB.39
C600
C600
C476
C476
C475
C475
C472
C472
N
N
N
N
0.01U_X7R_OP
0.01U_X7R_OP
0.1U_Y5V
0.1U_Y5V
10U_X5R
10U_X5R
10U_X5R
10U_X5R
C144
C144
BAT54W-F_OP
BAT54W-F_OP
0402C
0402C
0603C
0603C
1206C
1206C
1206C
1206C
2.2U_Y5V
2.2U_Y5V
SOT323_ACN
SOT323_ACN
R147
R147
0603C
0603C
0_5%
0_5%
U17
U17
U19
U19
N
N
IRF8113PBF
IRF8113PBF
0402R
0402R
IRF7807ZPBF
IRF7807ZPBF
IRF7807ZPBF
IRF7807ZPBF
N
N
IRF8113PBF
IRF8113PBF
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
YONAH (MAX36A)
U50
U50
U55
U55
MEROM (MAX44A)
C158
C158
JP1
JP1
N
N
N
N
R288
R288
10_1%
10_1%
VIN_IMVP6
U14
U14
0.22U_X7R
0.22U_X7R
2Phase OCP 47.6A
VIN
0402R
0402R
6
2
0603C
0603C
DCR=1.1m Ohm
D
VCC
BOOT
D
C275
C275
JMP
JMP
0.1U_Y5V
0.1U_Y5V
R573
R573
0_5%
0_5%
0402R
0402R
7
1
R146
R146
20K_1%
20K_1%
JP_10A
JP_10A
VCC_CORE
FCCM
UGTE
IRF8113PBF
IRF8113PBF
IRF8113PBF
IRF8113PBF
0603C
0603C
0402R
0402R
L7
L7
SOIC8
SOIC8
SOIC8
SOIC8
IMVP6_PWM1
3
8
R563
R563
PWM
PHSE
FMJ-10402-R36_24A
FMJ-10402-R36_24A
0.002_1%_OP
0.002_1%_OP
4
5
GND
LGTE
R287
R287
10_1%
10_1%
VCC5_SW_IMVP6
CHOKE_10X11_5MM
CHOKE_10X11_5MM
RL3264
RL3264
VCC5_SW
0402R
0402R
ISL6208CBZ
ISL6208CBZ
C274
C274
SOIC8
SOIC8
1U_Y5V
1U_Y5V
D54
D54
R196
R196
R194
R194
R197
R197
R195
R195
0603C
0603C
SS34A_3A
SS34A_3A
0_5%
0_5%
0_5%_OP
0_5%_OP
0_5%
0_5%
0_5%_OP
0_5%_OP
+
+
C481
C481
+
+
C482
C482
+
+
C487
C487
C194
C194
SOD106
SOD106
0402R
0402R
0402R
0402R
0402R
0402R
0402R
0402R
1U_Y5V
1U_Y5V
0603C
0603C
R300
R300
10_1%
10_1%
VCC3_SW_IMVP6
VCC3_SW
0402R
0402R
Modify RB.46
Modify
RB.46
C284
C284
VCC3_SW
0.1U_Y5V
0.1U_Y5V
IMVP6_VSUM
R291
R291
5.1K_1%
5.1K_1%
0402R
0402R
0402C
0402C
IMVP6_ISEN1
R265
R265
10K_1%
10K_1%
0402R
0402R
R264
R264
10_1%
10_1%
0402R
0402R
6m Ohm
R298
R298
10K_5%
10K_5%
U32
U32
VIN
0402R
0402R
VCC5_SW
D21
D21
Modify RB.39
R315
R315
0_5%
0_5%
0402R
0402R
1
24
C599
C599
C489
C489
C488
C488
C480
C480
3
PM_PSI#
PSI#
FCCM
R296
R296
499_1%
499_1%
0402R
0402R
0.01U_X7R_OP
0.01U_X7R_OP
0.1U_Y5V
0.1U_Y5V
10U_X5R
10U_X5R
10U_X5R
10U_X5R
36
6,13
PM_DPRSLPVR
DPRSLPVR
R299
R299
0_5%
0_5%
0402R
0402R
37
C253
C253
BAT54W-F_OP
BAT54W-F_OP
0402C
0402C
0603C
0603C
1206C
1206C
1206C
1206C
3,13
PM_DPRSTP#
DPRSTP#
C145
C145
0.1U_Y5V
0.1U_Y5V
C254
C254
0.1U_Y5V
0.1U_Y5V
R297
R297
0_5%
0_5%
0402R
0402R
38
2.2U_Y5V
2.2U_Y5V
SOT323_ACN
SOT323_ACN
R248
R248
16 PM_CLK_EN#
CLK_EN#
0402C
0402C
0402C
0402C
R314
R314
0_5%
0_5%
0402R
0402R
0603C
0603C
0_5%
0_5%
U21
U21
U20
U20
40
27
13,33
PM_VGATE
PGOOD
PWM1
C
0402R
0402R
IRF7807ZPBF
IRF7807ZPBF
IRF7807ZPBF
IRF7807ZPBF
C
R316
R316
0_5%
0_5%
0402R
0402R
R266
R266
0_5%_OP
0_5%_OP
0402R
0402R
SOIC8
SOIC8
SOIC8
SOIC8
2
32,33
PM_VCCP_PWRGD
PGD_IN
23
C268
C268
0.22U_X7R
0.22U_X7R
C270
C270
JP2
JP2
ISEN1
0603C
0603C
U22
U22
0.22U_X7R
0.22U_X7R
6
2
0603C
0603C
VCC
BOOT
DCR=1.1m Ohm
JMP
JMP
7
1
R247
R247
20K_1%
20K_1%
JP_10A
JP_10A
FCCM
UGTE
0402R
0402R
L8
L8
R317
R317
0_5%
0_5%
VR_TT#
IMVP6_PWM2
R566
R566
4
26
3
8
3 CPU_PROCHOT#
VR_TT#
PWM2
PWM
PHSE
0402R
0402R
R267
R267
0_5%_OP
0_5%_OP
0402R
0402R
FMJ-10402-R36_24A
FMJ-10402-R36_24A
0.002_1%_OP
0.002_1%_OP
4
5
GND
LGTE
28
CHOKE_10X11_5MM
CHOKE_10X11_5MM
RL3264
RL3264
3
CPU_VID0
VID0
(Rseries)
29
22
C269
C269
0.22U_X7R
0.22U_X7R
ISL6208CBZ
ISL6208CBZ
3
CPU_VID1
VID1
ISEN2
0603C
0603C
SOIC8
SOIC8
T
T
30
3
CPU_VID2
VID2
R290
R290
2.7K_1%
2.7K_1%
31
D55
D55
R207
R207
R205
R205
R206
R206
R204
R204
3
CPU_VID3
VID3
0402R
0402R
SS34A_3A
SS34A_3A
0_5%
0_5%
0_5%_OP
0_5%_OP
0_5%
0_5%
0_5%_OP
0_5%_OP
+
+
C499
C499
+
+
C500
C500
+
+
C498
C498
C238
C238
32
3
CPU_VID4
VID4
(Rpar)
33
SOD106
SOD106
0402R
0402R
0402R
0402R
0402R
0402R
0402R
0402R
1U_Y5V
1U_Y5V
3
CPU_VID5
VID5
R289
R289
4.7K_1%
4.7K_1%
34
0603C
0603C
3
CPU_VID6
VID6
0402R
0402R
R574
R574
0_5%
0_5%
IMVP6
IMVP6
25
PWM3
VCC5_SW
R286
R286
10K_5%
10K_5%
0402R
0402R
35
0402R
0402R
VCC3_SW
VR_ON
C277
C277
0.1U_Y5V
0.1U_Y5V
C288
C288
270P_X7R
270P_X7R
Soft-Start Time of 429.65us
Modify R1.05
0402C
0402C
0402C
0402C
C296
C296
0.047U_X7R_OP
0.047U_X7R_OP
21
R292
R292
0_5%
0_5%
IMVP6_VSUM
R270
R270
5.1K_1%
5.1K_1%
0402R
0402R
ISEN3
0402C
0402C
0402R
0402R
C276
C276
(Rdrp1)(Cn)
R304
R304
R303
R303
(Rdrp2)
C295
C295
0.015U_X7R
0.015U_X7R
IMVP6_ISEN2
6
R269
R269
10K_1%
10K_1%
0402R
0402R
SOFT
0402C
0402C
IMVP6_VO
R268
R268
10_1%
10_1%
0402R
0402R
6m Ohm
R313
R313
150K_1%
150K_1%
3
RBIAS
0.22U_X7R
0.22U_X7R
1K_1%
1K_1%
5.36K_1%
5.36K_1%
0402R
0402R
Close to CPU Socket Point
0603C
0603C
0402R
0402R
0402R
0402R
R318
R318
4.7K_1%
4.7K_1%
RT1
RT1
T
T
470K_5%_NTC
470K_5%_NTC
5
C297
C297
1000P_X7R
1000P_X7R
NTC
0402R
0402R
0402R
0402R
0402C
0402C
B
B
Close to Phase 1 Inductor
7
R319
R319
10K_1%
10K_1%
OCSET
C294
C294
0.01U_X7R
0.01U_X7R
(Rocset)
0402R
0402R
VCCSENSE/VSSSENSE: 100 ohm Pull up/Pull down
resister close to CPU Socket, Max length 2"
0402C
0402C
IMVP6_VSUM
17
VSUM
C301
C301
2200P_X7R
2200P_X7R
R323
R323
187_1%
187_1%
11
R185
R185
100_1%
100_1%
0402R
0402R
VDIFF
0402C
0402C
0402R
0402R
C209
C209
R322
R322
1.2K_1%
1.2K_1%
0.01U_X7R
0.01U_X7R
0402R
0402R
R186
R186
100_1%
100_1%
0402R
0402R
0402C
0402C
10
FB
16
VO
C300
C300
0.022U_X7R
0.022U_X7R
R321
R321
68K_1%
68K_1%
9
COMP
VCCSENSE/VSSSENSE
trace width & space 18mil/7mil
, Length match to within 25mils
0603C
0603C
0402R
0402R
RT2
RT2
VCCSENSE
3
C299
C299
220P_X7R
220P_X7R
10K_5%_NTC
10K_5%_NTC
VSSSENSE
3
0402C
0402C
0603R
0603R
R320
R320
6.49K_1%
6.49K_1%
8
Close to CPU
VW
0402R
0402R
C298
C298
1000P_X7R
1000P_X7R
15
DFB
0402C
0402C
Close to Phase 1
Inductor
CCM MODE Fix to 307.55KHz
C289
C289
0.1U_Y5V
0.1U_Y5V
0402C
0402C
14
DROOP
Modify RB.01
ISL6260CRZ
ISL6260CRZ
LFCSP41
LFCSP41
C286
C286
0.01U_X7R
0.01U_X7R
C285
C285
C287
C287
0.01U_X7R
0.01U_X7R
0402C
0402C
0.01U_X7R
0.01U_X7R
0402C
0402C
A
0402C
0402C
A
TP11TP11
VSSSENSE_IMVP6
R225
R225
0_5%
0_5%
0402R
0402R
VCCSENSE_IMVP6
R224
R224
0_5%
0_5%
0402R
0402R
Project Name
Project Name
Project Name
TP12TP12
H12YV1
H12YV1
H12YV1
R301
R301
R302
R302
27.4_1%_OP
27.4_1%_OP
27.4_1%_OP
27.4_1%_OP
Pag Title
Pag Title
Pag Title
0402R
0402R
0402R
0402R
CPU POWER
Document
Document
Document
Rev
Rev
Rev
82+A32000+00A
82+A32000+00A
82+A32000+00A
Number
Number
Number
A
A
A
Close to IMVP6 within 100mils(resistor & test point)
Sheet 5
Sheet 5
Sheet 5
Date:
Date:
Date:
Friday, November 24, 2006
Friday, November 24, 2006
Friday, November 24, 2006
of
of
of
38
38
38
5
4
3
2
1
39
3V3
13
RTN
41
GND
19
VSS
12
VSEN
20
VDD
18
VIN
4
5
4
5
G
D4
G
D4
3 2 1
6
3 2 1
6
S3
D3
S3
D3
7
7
S2
D2
S2
D2
8
4
5
8
4
5
S1
D1
G
D4
S1
D1
G
D4
3 2 1
6
3 2 1
6
S3
D3
S3
D3
7
7
S2
D2
S2
D2
8
8
S1
D1
S1
D1
4
5
4
5
G
D4
G
D4
3 2 1
6
3 2 1
6
S3
D3
S3
D3
7
7
S2
D2
S2
D2
8
4
5
8
4
5
S1
D1
G
D4
S1
D1
G
D4
3 2 1
6
3 2 1
6
S3
D3
S3
D3
7
7
S2
D2
S2
D2
8
8
S1
D1
S1
D1
4
5
4
5
G
D4
G
D4
3 2 1
6
3 2 1
6
S3
D3
S3
D3
7
7
S2
D2
S2
D2
8
8
S1
D1
S1
D1
5 4 3 2 1 DMI: 100MHz reference clock (shared with PCI Express Graphics Attach)
5
4
3
2
1
DMI: 100MHz reference clock (shared with PCI Express Graphics Attach)
U53A
U53A
U53B
U53B
DMI_TXN[0:3]
12
DMI_TXN0
G28
AE35
13
PM_BMBUSY#
PM_BM_BUSY#
DMI_RXN0
R92R92
100_1%100_1%
0402R0402R
DMI_TXN1
AH34
AF39
3 AGTL+_D#[0:63]
AGTL+_A#[3:31]
3
13,24,26,27
PM_PLTRST#
RSTIN#
DMI_RXN1
DMI_TXN2
AH33
AG35
13,29,33
PM_PWROK
PWROK
DMI_RXN2
DMI_TXP[0:3]
12
AGTL+_D#0
AGTL+_A#3
H9
R219R219
0_5%0_5%
0402R0402R
DMI_TXN3
F1
G6
AH39
3,13
PM_THERMTRIP#
HD0#
HA3#
THRMTRIP#
DMI_RXN3
AGTL+_D#1
AGTL+_A#4
DMI_TXP0
J1
C9
F25
AC35
HD1#
HA4#
10,15
PM_EXTTS0#
PM_EXT_TS0#
DMI_RXP0
AGTL+_D#2
AGTL+_A#5
PM_EXTTS1#
DMI_TXP1
H1
E11
H26
AE39
HD2#
HA5#
15
PM_EXTTS1#
PM_EXT_TS1#
DMI_RXP1
AGTL+_D#3
AGTL+_A#6
DMI_TXP2
J6
G11
K28
AF35
HD3#
HA6#
13 MCH_ICH_SYNC#
ICH_SYNC#
DMI_RXP2
AGTL+_D#4
AGTL+_A#7
DMI_TXP3
H3
F11
AG39
HD4#
HA7#
DMI_RXP3
AGTL+_D#5
AGTL+_A#8
K2
G12
R559
R559
0_5%
0_5%
A16
HD5#
HA8#
5,13
PM_DPRSLPVR
VCC1_5_SW
TV_DAC_A
DMI_RXN[0:3]
12
AGTL+_D#6
AGTL+_A#9
DMI_RXN0
D
G1
F9
0402R
0402R
C18
AE37
D
HD6#
HA9#
TV_DAC_B
DMI_TXN0
AGTL+_D#7
AGTL+_A#10
DMI_RXN1
G2
H11
A19
AF41
HD7#
HA10#
TV_DAC_C
DMI_TXN1
AGTL+_D#8
AGTL+_A#11
DMI_RXN2
K9
J12
AG37
HD8#
HA11#
DMI_TXN2
DMI_RXP[0:3]
12
AGTL+_D#9
AGTL+_A#12
DMI_RXN3
K1
G14
B16
AH41
HD9#
HA12#
TV_IRTN_A
DMI_TXN3
AGTL+_D#10
AGTL+_A#13
DMI_RXP0
K7
D9
B18
AC37
HD10#
HA13#
TV_IRTN_B
DMI_TXP0
AGTL+_D#11
AGTL+_A#14
DMI_RXP1
J8
J14
B19
AE41
HD11#
HA14#
TV_IRTN_C
DMI_TXP1
AGTL+_D#12
AGTL+_A#15
DMI_RXP2
H4
H13
AF37
HD12#
HA15#
DMI_TXP2
AGTL+_D#13
AGTL+_A#16
DMI_RXP3
J3
J15
K30
AG41
HD13#
HA16#
TV_DCONSEL0
DMI_TXP3
AGTL+_D#14
AGTL+_A#17
K11
F14
J29
HD14#
HA17#
TV_DCONSEL1
AGTL+_D#15
AGTL+_A#18
G4
D12
A33
HD15#
HA18#
LA_CLKN
LVDS1_CLK-
11
AGTL+_D#16
AGTL+_A#19
T10
A11
F34
A32
HD16#
HA19#
EXP_RXN0
LA_CLKP
LVDS1_CLK+
11
AGTL+_D#17
AGTL+_A#20
W11
C11
G38
HD17#
HA20#
EXP_RXN1
AGTL+_D#18
AGTL+_A#21
T3
A12
H34
C37
HD18#
HA21#
EXP_RXN2
LA_DATAN0
LVDS1_Y0-
11
AGTL+_D#19
AGTL+_A#22
U7
A13
J38
B35
HD19#
HA22#
EXP_RXN3
LA_DATAN1
LVDS1_Y1-
11
AGTL+_D#20
AGTL+_A#23
U9
E13
L34
A37
HD20#
HA23#
EXP_RXN4
LA_DATAN2
LVDS1_Y2-
11
AGTL+_D#21
AGTL+_A#24
U11
G13
M38
HD21#
HA24#
EXP_RXN5
AGTL+_D#22
AGTL+_A#25
T11
F12
N34
B37
HD22#
HA25#
EXP_RXN6
LA_DATAP0
LVDS1_Y0+
11
AGTL+_D#23
AGTL+_A#26
W9
B12
P38
B34
HD23#
HA26#
EXP_RXN7
LA_DATAP1
LVDS1_Y1+
11
AGTL+_D#24
AGTL+_A#27
T1
B14
R34
A36
HD24#
HA27#
EXP_RXN8
LA_DATAP2
LVDS1_Y2+
11
AGTL+_D#25
AGTL+_A#28
T8
C12
T38
HD25#
HA28#
EXP_RXN9
AGTL+_D#26
AGTL+_A#29
T4
A14
V34
E27
HD26#
HA29#
EXP_RXN10
LB_CLKN
AGTL+_D#27
AGTL+_A#30
W7
C14
W38
E26
HD27#
HA30#
EXP_RXN11
LB_CLKP
AGTL+_D#28
AGTL+_A#31
U5
D14
Y34
HD28#
HA31#
AGTL+_ADSTB#[0:1]
3
EXP_RXN12
AGTL+_D#29
T9
AA38
G30
HD29#
HOST
HOST
EXP_RXN13
LB_DATAN0
AGTL+_D#30
AGTL+_ADSTB#0
W6
B9
AB34
D30
HD30#
HADSTB0#
EXP_RXN14
LB_DATAN1
AGTL+_D#31
AGTL+_ADSTB#1
T5
C13
AC38
F29
HD31#
HADSTB1#
AGTL+_DSTBN#[0:3]
3
EXP_RXN15
LB_DATAN2
AGTL+_D#32
AGTL+_DSTBN#0
AB7
K4
HD32#
HDSTBN0#
AGTL+_D#33
AGTL+_DSTBN#1
AA9
T7
D34
F30
HD33#
HDSTBN1#
EXP_RXP0
LB_DATAP0
AGTL+_D#34
AGTL+_DSTBN#2
W4
Y5
F38
D29
HD34#
HDSTBN2#
EXP_RXP1
LB_DATAP1
AGTL+_D#35
AGTL+_DSTBN#3
W3
AC4
G34
F28
HD35#
HDSTBN3#
AGTL+_DSTBP#[0:3]
3
EXP_RXP2
LB_DATAP2
AGTL+_D#36
AGTL+_DSTBP#0
Y3
K3
H38
HD36#
HDSTBP0#
EXP_RXP3
C
AGTL+_D#37
AGTL+_DSTBP#1
LCDBLT_CTL
Y7
T6
J34
D32
C
HD37#
HDSTBP1#
EXP_RXP4
IGDS
IGDS
LBKLT_CTL
LCDBLT_CTL
11
AGTL+_D#38
AGTL+_DSTBP#2
LCD_ENBLT
W5
AA5
L38
J30
HD38#
HDSTBP2#
EXP_RXP5
LBKLT_EN
LCD_ENBLT
11
AGTL+_D#39
AGTL+_DSTBP#3
LCD_ENVCC
Y10
AC5
M34
F32
HD39#
HDSTBP3#
EXP_RXP6
LVDDEN
LCD_ENVCC
11
AGTL+_D#40
AB8
N38
HD40#
AGTL+_REQ#[0:4]
3
EXP_RXP7
AGTL+_D#41
AGTL+_REQ#0
W2
D8
P34
H30
HD41#
HREQ0#
EXP_RXP8
LCTLA_CLK
LCTLA_CLK
15
AGTL+_D#42
AGTL+_REQ#1
AA4
G8
R38
H29
HD42#
HREQ1#
EXP_RXP9
LCTLB_DATA
LCTLB_DATA
15
AGTL+_D#43
AGTL+_REQ#2
AA7
B8
T34
G26
HD43#
HREQ2#
EXP_RXP10
LDDCCLK
LDDCCLK
11,15
AGTL+_D#44
AGTL+_REQ#3
AA2
F8
V38
G25
HD44#
HREQ3#
EXP_RXP11
LDDCDATA
LDDCDATA
11,15
AGTL+_D#45
AGTL+_REQ#4
AA6
A8
W34
HD45#
HREQ4#
AGTL+_DINV#[0:3]
3
EXP_RXP12
AGTL+_D#46
AA10
Y38
HD46#
EXP_RXP13
AGTL+_D#47
AGTL+_DINV#0
DAC_RED
Y8
J7
AA34
A21
HD47#
DINV0#
EXP_RXP14
RED
DAC_RED
11
AGTL+_D#48
AGTL+_DINV#1
DAC_GREEN
AA1
W8
AB38
C22
HD48#
DINV1#
EXP_RXP15
GREEN
DAC_GREEN
11
AGTL+_D#49
AGTL+_DINV#2
DAC_BLUE
AB4
U3
E23
HD49#
DINV2#
BLUE
DAC_BLUE
11
AGTL+_D#50
AGTL+_DINV#3
AC9
AB10
F36
B21
HD50#
DINV3#
EXP_TXN0
RED#
AGTL+_D#51
AB11
G40
B22
HD51#
EXP_TXN1
GREEN#
AGTL+_D#52
AC11
E8
H36
D23
HD52#
ADS#
AGTL+_ADS#
3
EXP_TXN2
BLUE#
AGTL+_D#53
AB3
C6
J40
HD53#
BNR#
AGTL+_BNR#
3
EXP_TXN3
AGTL+_D#54
AC2
F6
L36
C25
HD54#
BPRI#
AGTL+_BPRI#
3
EXP_TXN4
DDCADATA
DDC1_DATA
11
AGTL+_D#55
AD1
C7
M40
C26
HD55#
BREQ0#
AGTL+_BR0#
3
EXP_TXN5
DDCACLK
DDC1_CLK
11
AGTL+_D#56
IGD_HSYNC
AD9
B7
N36
G23
R166R166
39_1%39_1% 0402R0402R
HD56#
CPURST#
AGTL+_CPURST#
3
EXP_TXN6
HSYNC
DAC_HSYNC
11
AGTL+_D#57
IGD_VSYNC
AC1
A7
P40
H23
R167R167
39_1%39_1% 0402R0402R
HD57#
DBSY#
AGTL+_DBSY#
3
EXP_TXN7
VSYNC
DAC_VSYNC
11
AGTL+_D#58
AD7
C3
R36
HD58#
DEFER#
AGTL+_DEFER#
3
EXP_TXN8
AGTL+_D#59
AC6
H8
T40
GMCH Pin ball G23, H23 to 39Ohm trace length <0.5"
HD59#
DRDY#
AGTL+_DRDY#
3
EXP_TXN9
AGTL+_D#60
AB5
D3
V36
HD60#
HIT#
AGTL+_HIT#
3
EXP_TXN10
AGTL+_D#61
CLK_PEG_MCH#
AD10
D4
W40
AF33
HD61#
HITM#
AGTL+_HITM# 3
EXP_TXN11
GCLKN
CLK_PEG_MCH#
16
AGTL+_D#62
CLK_PEG_MCH
AD4
E7
Y36
AG33
HD62#
HTRDY#
AGTL+_TRDY#
3
EXP_TXN12
GCLKP
CLK_PEG_MCH
16
AGTL+_D#63
AC8
B3
AA40
HD63#
HLOCK#
AGTL+_LOCK#
3
EXP_TXN13
CLK_DREF_CLK#
AB36
A27
EXP_TXN14
DREF_CLKN
CLK_DREF_CLK#
16
CLK_MCH_BCLK
CLK_DREF_CLK
AG2
AC40
A26
16
CLK_MCH_BCLK
BCLK
EXP_TXN15
DREF_CLKP
CLK_DREF_CLK
16
CLK_MCH_BCLK#
AG1
J9
16
CLK_MCH_BCLK#
BCLK#
DPWR#
AGTL+_DPWR#
3
CLK_DREF_SSCLK#
E3
D36
C40
CPUSLP#
CPU_CPUSLP#
3
EXP_TXP0
DREF_SSCLKN
CLK_DREF_SSCLK#
16
B
B
HXSWING
CLK_DREF_SSCLK
E4
F40
D41
HXSWING
EXP_TXP1
DREF_SSCLKP
CLK_DREF_SSCLK
16
HXSCOMP
AGTL+_RS#0
E2
B4
G36
HXSCOMP
RS0#
EXP_TXP2
HXRCOMP
AGTL+_RS#1
GMCH_CLKREQ#
E1
E6
H40
H32
HXRCOMP
RS1#
EXP_TXP3
CLK_REQ#
TP1TP1
HYSWING
AGTL+_RS#2
W1
D6
J36
HYSWING
RS2#
EXP_TXP4
HYSCOMP
U1
L40
HYSCOMP
EXP_TXP5
HYRCOMP
Y1
M36
H27
HYRCOMP
AGTL+_RS#[0:2]
3
EXP_TXP6
SDVOCTRL_DATA
HVREF
J13
N40
INT-L
INT-L
H28
HVREF0
EXP_TXP7
SDVOCTRL_CLK
K13
P36
HVREF1
EXP_TXP8
CRT_IREF
R40
J22
EXP_TXP9
CRT_IREF
T36
J20
EXP_TXP10
TV_IREF
VCC1_5_SW
Calistoga
Calistoga
V40
Net CRT_IREF:
EXP_TXP11
FBGA_1466_42_34_ALONE
FBGA_1466_42_34_ALONE
W36
C33
Minimum spacing of
EXP_TXP12
LVREFH
Y40
C32
R152
R152
EXP_TXP13
LVREFL
20mils
LIBG
AA36
B38
255_1%
255_1%
EXP_TXP14
LIBG
AB40
C35
0402R
0402R
EXP_TXP15
LVBG
R73
R73
24.9_1%
24.9_1%
D40
R111
R111
VCC1_5_SW
EXP_COMPI
0402R
0402R
D38
1.5K_1%
1.5K_1%
EXP_ICOMPO
VCC_P
VCC_P
VCC_P
VCC_P
VCC_P
0402R
0402R
Calistoga
Calistoga
Zdiff=100 ohm +-15%
FBGA_1466_42_34_ALONE
FBGA_1466_42_34_ALONE
Close to NB
R203
R203
R217
R217
R221
R221
R218
R218
R180
R180
DAC_RED/DAC_GREEN/DAC_BLUE
are ground referenced
221_1%
221_1%
221_1%
221_1%
54.9_1%
54.9_1%
54.9_1%
54.9_1%
100_1%
100_1%
0402R
0402R
0402R
0402R
0402R
0402R
0402R
0402R
0402R
0402R
HXSWING
HYSWING
HVREF
HXSCOMP
HYSCOMP
R202
R202
C213
C213
R216
R216
C233
C233
R179
R179
C190
C190
R126
R126
100K_1%_OP
100K_1%_OP
LCDBLT_CTL
A
A
100_1%
100_1%
0.1U_Y5V
0.1U_Y5V
100_1%
100_1%
0.1U_Y5V
0.1U_Y5V
200_1%
200_1%
0.1U_Y5V
0.1U_Y5V
0402R
0402R
0402R
0402R
0402C
0402C
0402R
0402R
0402C
0402C
HXRCOMP
HYRCOMP
0402R
0402R
0402C
0402C
R123
R123
100K_1%
100K_1%
LCD_ENBLT
R154
R154
R145
R145
R155
R155
0402R
0402R
150_1%
150_1%
150_1%
150_1%
150_1%
150_1%
R220
R220
R215
R215
0402R
0402R
0402R
0402R
0402R
0402R
R124
R124
100K_1%
100K_1%
LCD_ENVCC
Project Name
Project Name
Project Name
24.9_1%
24.9_1%
24.9_1%
24.9_1%
0402R
0402R
H12YV1
H12YV1
H12YV1
0402R
0402R
0402R
0402R
Trace width/Space:
Capacitor needs to be within 100mils of
GMCH pin J13, K13
Close to GMCH pin D32, J30, F32
Pag Title
Pag Title
Pag Title
10mil/20mil
Calistoga(HOST/IGDS/DMI)
Close to GMCH DAC_RED/DAC_GREEN/DAC_BLUE
max length 0.5"
Document
Document
Document
Rev
Rev
Rev
82+A32000+00A
82+A32000+00A
82+A32000+00A
Number
Number
Number
A
A
A
Sheet 6
Sheet 6
Sheet 6
Date:
Date:
Date:
Friday, November 24, 2006
Friday, November 24, 2006
Friday, November 24, 2006
of
of
of
38
38
38
5
4
3
2
1
DAC_RED
DAC_GREEN
DAC_BLUE
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PM
PM
TV
TV
CLK
CLK
DMILVDSCRT
DMILVDSCRT

5

4

3

2

1

D

C

5 4 3 2 1 D C B A D C B DDRA_MA[0:13] 10 U53C U53C

B

A

D

C

5 4 3 2 1 D C B A D C B DDRA_MA[0:13] 10 U53C U53C

B

DDRA_MA[0:13] 10 U53C U53C 10 DDRA_MD[0:63] DDRA_MA0 AY16 SAMA0 DDRA_MD0 DDRA_MA1 AJ35 AU14 SADQ0 SAMA1
DDRA_MA[0:13]
10
U53C
U53C
10
DDRA_MD[0:63]
DDRA_MA0
AY16
SAMA0
DDRA_MD0
DDRA_MA1
AJ35
AU14
SADQ0
SAMA1
DDRA_MD1
DDRA_MA2
AJ34
AW16
SADQ1
SAMA2
DDRA_MD2
DDRA_MA3
AM31
BA16
SADQ2
SAMA3
DDRA_MD3
DDRA_MA4
AM33
BA17
SADQ3
SAMA4
DDRA_MD4
DDRA_MA5
AJ36
AU16
SADQ4
SAMA5
DDRA_MD5
DDRA_MA6
AK35
AV17
SADQ5
SAMA6
DDRA_MD6
DDRA_MA7
AJ32
AU17
SADQ6
SAMA7
DDRA_MD7
DDRA_MA8
AH31
AW17
SADQ7
SAMA8
DDRA_MD8
DDRA_MA9
AN35
AT16
SADQ8
SAMA9
DDRA_MD9
DDRA_MA10
AP33
AU13
SADQ9
SAMA10
DDRA_MD10
DDRA_MA11
AR31
AT17
SADQ10
SAMA11
DDRA_MD11
DDRA_MA12
AP31
AV20
SADQ11
SAMA12
DDRA_MD12
DDRA_MA13
AN38
AV12
SADQ12
SAMA13
DDRA_MD13
AM36
SADQ13
DDRA_MD14
AM34
AK23
SADQ14
SA_RCVENIN#
DDRA_MD15
AN33
AK24
SADQ15
SA_RCVENOUT#
DDRA_MD16
AK26
SADQ16
DDRA_MD17
DDRA_SWE#
AL27
AY14
SADQ17
SA_WE#
DDRA_SWE#
10
DDRA_MD18
DDRA_SRAS#
AM26
AW14
SADQ18
SA_RAS#
DDRA_SRAS#
10
DDRA_MD19
DDRA_SCAS#
AN24
AY13
SADQ19
SA_CAS#
DDRA_SCAS#
10
DDRA_MD20
AK28
SADQ20
DDRA_MD21
AL28
SADQ21
DDRA_MD22
DDRA_SBS0
AM24
AU12
SADQ22
SA_BS0
DDRA_SBS0
10
DDRA_MD23
DDRA_SBS1
AP26
AV14
SADQ23
SA_BS1
DDRA_SBS1
10
DDRA_MD24
DDRA_SBS2
AP23
BA20
SADQ24
SA_BS2
DDRA_SBS2
10
DDRA_MD25
AL22
SADQ25
DDRA_MD26
AP21
SADQ26
DDRA_MD27
DDR_CS#0
AN20
AW13
SADQ27
SCS0#
DDR_CS#0
10
DDRA_MD28
DDR_CS#1
AL23
AW12
SADQ28
SCS1#
DDR_CS#1
10
DDRA_MD29
AP24
AY21
SADQ29
SCS2#
DDRA_MD30
AP20
AW21
SADQ30
SCS3#
DDRA_MD31
AT21
SADQ31
DDRA_MD32
AR12
SADQ32
DDRA_MD33
AR14
AY35
SADQ33
SCK0
DDR_CLK0
10
DDRA_MD34
AP13
AW35
SADQ34
SCK#0
DDR_CLK#0
10
DDRA_MD35
AP12
AR1
SADQ35
SCK1
DDR_CLK1
10
DDRA_MD36
AT13
AT1
SADQ36
DDR2-A
DDR2-A
SCK#1
DDR_CLK#1
10
DDRA_MD37
AT12
AW7
SADQ37
SCK2
DDRA_MD38
AL14
AY7
SADQ38
SCK#2
DDRA_MD39
AL12
AW40
SADQ39
SCK3
DDRA_MD40
AK9
AY40
SADQ40
SCK#3
DDRA_MD41
AN7
SADQ41
DDRA_MD42
AK8
SADQ42
DDRA_MD43
AK7
SADQ43
DDRA_MD44
AP9
SADQ44
DDRA_MD45
AN9
SADQ45
DDRA_MD46
AT5
SADQ46
DDRA_MD47
DDR_CKE0
AL5
AU20
SADQ47
SCKE0
DDR_CKE0
10
DDRA_MD48
DDR_CKE1
AY2
AT20
SADQ48
SCKE1
DDR_CKE1
10
DDRA_MD49
AW2
BA29
SADQ49
SCKE2
DDRA_MD50
AP1
AY29
SADQ50
SCKE3
DDRA_MD51
AN2
SADQ51
DDRA_MD52
AV2
SADQ52
DDRA_MD53
DDR_SODT0
AT3
BA13
SADQ53
SODT0
DDR_SODT0
10
DDRA_MD54
DDR_SODT1
AN1
BA12
SADQ54
SODT1
DDR_SODT1
10
DDRA_MD55
AL2
AY20
SADQ55
SODT2
DDRA_MD56
AG7
AU21
SADQ56
SODT3
DDRA_MD57
AF9
SADQ57
DDRA_MD58
AG4
SADQ58
DDRA_MD59
AF6
SADQ59
DDRA_MD60
R151R151
40.2_1%_OP40.2_1%_OP
0402R0402R
AG9
AL20
SADQ60
SMOCDCOMP0
DDRA_MD61
R178R178
40.2_1%_OP40.2_1%_OP
0402R0402R
AH6
AF10
SADQ61
SMOCDCOMP1
DDRA_MD62
AF4
SADQ62
DDRA_MD63
R192R192
80.6_1%80.6_1%
0402R0402R
AF8
AV9
VCC1_8
SADQ63
SMRCOMPN
AT9
10
DDRA_SDM[0:7]
SMRCOMPP
DDRA_SDM0
AJ33
SADM0
DDRA_SDM1
AM35
SADM1
DDRA_SDM2
AL26
R193
R193
SADM2
DDRA_SDM3
80.6_1%
80.6_1%
AN22
SADM3
DDRA_SDM4
AM14
0402R
0402R
SADM4
DDRA_SDM5
AL9
SADM5
DDRA_SDM6
AR3
SADM6
DDRA_SDM7
SMVREF
AH4
AK1
10uA
SADM7
SMVREF0
AK41
10
DDRA_DQS[0:7]
SMVREF1
DDRA_DQS0
AK33
SA_DQS0
DDRA_DQS1
AT33
SA_DQS1
DDRA_DQS2
AN28
SA_DQS2
DDRA_DQS3
AM22
SA_DQS3
DDRA_DQS4
AN12
SA_DQS4
DDRA_DQS5
AN8
SA_DQS5
DDRA_DQS6
AP3
SA_DQS6
DDRA_DQS7
AG5
SA_DQS7
10
DDRA_DQS#[0:7]
DDRA_DQS#0
AK32
SA_DQS#0
VCC1_8
DDRA_DQS#1
AU33
SA_DQS#1
DDRA_DQS#2
AN27
SA_DQS#2
DDRA_DQS#3
AM21
SA_DQS#3
DDRA_DQS#4
AM12
SA_DQS#4
DDRA_DQS#5
R90
R90
AL8
SA_DQS#5
DDRA_DQS#6
AN3
10K_1%
10K_1%
SA_DQS#6
DDRA_DQS#7
0402R
0402R
AH5
SA_DQS#7
SMVREF
Calistoga
Calistoga
FBGA_1466_42_34_ALONE
FBGA_1466_42_34_ALONE
C212
C212
C96
C96
R91
R91
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
0.1U_Y5V
10K_1%
10K_1%
0402C
0402C
0402C
0402C
0402R
0402R
Close to MGCH pin AK1, AK41

U53F

U53F

SB_DQ0

SB_DQ1

SB_DQ2

SB_DQ3

SB_DQ4

SB_DQ5

SB_DQ6

SB_DQ7

SB_DQ8

SB_DQ9

SB_DQ10

SB_DQ11

SB_DQ12

SB_DQ13

SB_DQ14

SB_DQ15

SB_DQ16

SB_DQ17

SB_DQ18

SB_DQ19

SB_DQ20

SB_DQ21

SB_DQ22

SB_DQ23

SB_DQ24

SB_DQ25

SB_DQ26

SB_DQ27

SB_DQ28

SB_DQ29

SB_DQ30

SB_DQ31

SB_DQ32

SB_DQ33

SB_DQ34

SB_DQ35

SB_DQ36

SB_DQ37

SB_DQ38

SB_DQ39

SB_DQ40

SB_DQ41

SB_DQ42

SB_DQ43

SB_DQ44

SB_DQ45

SB_DQ46

SB_DQ47

SB_DQ48

SB_DQ49

SB_DQ50

SB_DQ51

SB_DQ52

SB_DQ53

SB_DQ54

SB_DQ55

SB_DQ56

SB_DQ57

SB_DQ58

SB_DQ59

SB_DQ60

SB_DQ61

SB_DQ62

SB_DQ63

DDR2-B

DDR2-B

SBMA0

SBMA1

SBMA2

SBMA3

SBMA4

SBMA5

SBMA6

SBMA7

SBMA8

SBMA9

SBMA10

SBMA11

SBMA12

SBMA13

SB_DQS0

SB_DQS1

SB_DQS2

SB_DQS3

SB_DQS4

SB_DQS5

SB_DQS6

SB_DQS7

SB_DQS#0

SB_DQS#1

SB_DQS#2

SB_DQS#3

SB_DQS#4

SB_DQS#5

SB_DQS#6

SB_DQS#7

SBDM0

SBDM1

SBDM2

SBDM3

SBDM4

SBDM5

SBDM6

SBDM7

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

SB_CAS#

SB_RAS#

SB_BS0

SB_BS1

SB_BS2

AK39

AJ37

AP39

AR41

AJ38

AK38

AN41

AP41

AT40

AV41

AU38

AV38

AP38

AR40

AW38

AY38

BA38

AV36

AR36

AP36

BA36

AU36

AP35

AP34

AY33

BA33

AT31

AU29

AU31

AW31

AV29

AW29

AM19

AL19

AP14

AN14

AN17

AM16

AP15

AL15

AJ11

AH10

AJ9

AN10

AK13

AH11

AK10

AJ8

BA10

AW10

BA4

AW4

AY10

AY9

AW5

AY5

AV4

AR5

AK4

AK3

AT4

AK5

AJ5

AJ3

AY23

AW24

AY24

AR28

AT27

AT28

AU27

AV28

AV27

AW27

AV24

BA27

AY27

AR23

AM39

AT39

AU35

AR29

AR16

AR10

AR7

AN5

AM40

AU39

AT35

AP29

AP16

AT10

AT7

AP5

AK36

AR38

AT36

BA31

AL17

AH8

BA5

AN4

AK16

AP16 AT10 AT7 AP5 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 AK16 AK18 AR27 AR24

AK18

AT10 AT7 AP5 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 AK16 AK18 AR27 AR24 AU23

AR27

AR24

AU23

AT24

AV23

AY28

32mA

Calistoga

Calistoga

FBGA_1466_42_34_ALONE

FBGA_1466_42_34_ALONE

* DDR2 400MHz/533MHz/667MHz memory device

* 256Mb/512Mb/1Gb using *8/*16 device

* Minimum memory support 128MB

* Calistoga GMCH does not support ECC & third SCK pair non-ECC memory module.

not support ECC & third SCK pair non-ECC memory module. A Project Name Project Name Project

A

Project Name

Project Name

Project Name

H12YV1

H12YV1

H12YV1

Pag Title

Pag Title

Pag Title

Calistoga(DDR2 I/F)

Rev Rev Rev A A A 38 38 38
Rev
Rev
Rev
A
A
A
38
38
38

Sheet 7

Sheet 7

Sheet 7

Document

Document

Document

Number

Number

Number

82+A32000+00A

82+A32000+00A

82+A32000+00A

Date:

Date:

Date:

Friday, November 24, 2006

Friday, November 24, 2006

Friday, November 24, 2006

of

of

of

5

4

3

2

1

5 4 3 2 1 B7 B7 U53D U53D DHBS2012_G301 DHBS2012_G301 0805B 0805B U53G U53G
5
4
3
2
1
B7
B7
U53D
U53D
DHBS2012_G301 DHBS2012_G301
0805B 0805B
U53G
U53G
VCC_P
1.9A
VCCAUX_GMCH
AC14
AK31
VCC_P
VTT0
VCCAUX0
VCC1_5_SW
AB14
AF31
D1
VTT1
VCCAUX1
NC0
0.8A
C188
C188
C186
C186
C166
C166
C123
C123
C137
C137
W14
AE31
AD27
C41
VTT2
VCCAUX2
VCC_NCTF0
NC1
V14
AC31
0.1U_Y5V
0.1U_Y5V
39P_NPO
39P_NPO
10U_Y5V
10U_Y5V
10U_Y5V
10U_Y5V
10U_Y5V_OP
10U_Y5V_OP
AC27
C1
VTT3
VCCAUX3
VCC_NCTF1
NC2
0402C
0402C
0402C
0402C
0805C
0805C
0805C
0805C
0805C
0805C
T14
AL30
AB27
BA41
VTT4
VCCAUX4
VCC_NCTF2
NC3
C201
C201
C187
C187
C189
C189
C202
C202
R14
AK30
AA27
BA40
VTT5
VCCAUX5
VCC_NCTF3
NC4
10U_Y5V
10U_Y5V
39P_NPO
39P_NPO
P14
AJ30
Y27
BA39
VTT6
VCCAUX6
VCC_NCTF4
NC5
0805C
0805C
0402C
0402C
N14
AH30
W27
BA3
VTT7
VCCAUX7
VCC_NCTF5
NC6
M14
AG30
V27
BA2
VTT8
VCCAUX8
VCC_NCTF6
NC7
L14
AF30
U27
BA1
VTT9
VCCAUX9
VCC_NCTF7
NC8
AD13
AE30
T27
B41
VTT10
VCCAUX10
VCC_NCTF8
NC9
AC13
AD30
R27
B2
VTT11
VCCAUX11
VCC_NCTF9
NC10
AB13
AC30
AD26
AY41
VTT12
VCCAUX12
VCC_NCTF10
NC11
AA13
AG29
AC26
AY1
D
VTT13
VCCAUX13
VCC_NCTF11
NC12
D
Y13
AF29
AB26
AW41
011
= 667 MT/s(667MHz)FSB
VTT14
VCCAUX14
VCC_NCTF12
NC13
W13
AE29
AA26
AW1
VTT15
VCCAUX15
VCC_NCTF13
NC14
V13
AD29
Y26
A40
CFG[2:0]
001
= 533 MT/s(533MHz)FSB
VTT16
VCCAUX16
VCC_NCTF14
NC15
U13
AC29
W26
A4
VTT17
VCCAUX17
VCC_NCTF15
NC16
T13
AG28
V26
A39
Others = Reserved
VTT18
VCCAUX18
VCC_NCTF16
NC17
R13
AF28
U26
A3
VTT19
VCCAUX19
VCC_NCTF17
NC18
N13
AE28
B13
B13
T26
VTT20
VCCAUX20
VCC_NCTF18
M13
AH22
AMB2012R101NT
AMB2012R101NT
R26
VTT21
VCCAUX21
VCC_NCTF19
0805B
0805B
MCH_BSEL0
R199
R199
1K_1%
1K_1%
0402R
0402R
L13
AJ21
AD25
K16
VTT22
VCCAUX22
VCC_NCTF20
CFG0
BSEL0 3,16
VCCA_HPLL
MCH_BSEL1
AB12
AH21
AC25
K18
R201
R201
1K_1%
1K_1%
0402R
0402R
VCC1_5_SW
VTT23
VCCAUX23
VCC_NCTF21
CFG1
BSEL1 3,16
MCH_BSEL2
R200
R200
1K_1%
1K_1%
0402R
0402R
AA12
AJ20
AB25
J18
VTT24
VCCAUX24
VCC_NCTF22
CFG2
BSEL2 3,16
Y12
AH20
C231
C231
C243
C243
AA25
F18
VTT25
VCCAUX25
VCC_NCTF23
CFG3
W12
AH19
0.1U_Y5V
0.1U_Y5V
10U_Y5V_OP
10U_Y5V_OP
Y25
E15
VTT26
VCCAUX26
VCC_NCTF24
CFG4
0402C
0402C
0805C
0805C
V12
P19
W25
F15
VTT27
VCCAUX27
VCC_NCTF25
CFG5
CFG5
15
U12
P16
B12
B12
V25
E18
VTT28
VCCAUX28
VCC_NCTF26
CFG6
AMB2012R101NT
AMB2012R101NT
T12
AH15
U25
D19
VTT29
VCCAUX29
VCC_NCTF27
CFG7
CFG7
15
R12
P15
0805B
0805B
T25
D16
VTT30
VCCAUX30
VCC_NCTF28
CFG8
VCCA_MPLL
P12
AH14
R25
G16
VCC1_5_SW
VTT31
VCCAUX31
VCC_NCTF29
CFG9
CFG9
15
N12
AG14
AD24
E16
VTT32
VCCAUX32
VCC_NCTF30
CFG10
M12
AF14
C230
C230
C242
C242
AC24
D15
VTT33
VCCAUX33
VCC_NCTF31
CFG11
CFG11
15
0.1U_Y5V
0.1U_Y5V
10U_Y5V_OP
10U_Y5V_OP
L12
AE14
AB24
G15
VTT34
VCCAUX34
VCC_NCTF32
CFG12
CFG12
15
R11
Y14
0402C
0402C
0805C
0805C
AA24
K15
VTT35
VCCAUX35
VCC_NCTF33
CFG13
CFG13
15
P11
AF13
B5
B5
Y24
C15
VTT36
VCCAUX36
VCC_NCTF34
CFG14
AMB2012R101NT
AMB2012R101NT
N11
AE13
W24
H16
VTT37
VCCAUX37
VCC_NCTF35
CFG15
M11
AF12
0805B
0805B
V24
G18
VTT38
VCCAUX38
VCC_NCTF36
CFG16
CFG16
15
VCCA_3GPLL
R10
AE12
U24
H15
VCC1_5_SW
VTT39
VCCAUX39
VCC_NCTF37
CFG17
P10
AD12
T24
J25
VTT40
VCCAUX40
VCC_NCTF38
CFG18
CFG18
15
N10
C124
C124
C125
C125
R24
K27
VTT41
VCC_NCTF39
CFG19
CFG19
15
0.1U_Y5V 0.1U_Y5V
10U_Y5V
10U_Y5V
M10
Close to PIN Ball
< 200mil
AD23
J26
VTT42
VCC_NCTF40
CFG20
CFG20
15
P9
0402C 0402C
0805C
0805C
V23
VTT43
VCC_NCTF41
B6
B6
N9
U23
VTT44
POWER
POWER
VCC_NCTF42
M9
AMB2012R101NT AMB2012R101NT
T23
T32
VTT45
VCC_NCTF43
RSVD1
R8
0805B
0805B
R23
R32
VTT46
VCC_NCTF44
RSVD2
VCCA_DPLLA
P8
AD22
F3
VCC1_5_SW
VTT47
VCC_NCTF45
RSVD3
N8
V22
F7
VTT48
VCC_NCTF46
NCTF
NCTF
RSVD4
C
C
45mA
C154
C154
C142
C142
M8
AF1
U22
AG11
VTT49
VCCA_HPLL
VCC_NCTF47
RSVD5
P7
AF2
45mA
0.1U_Y5V
0.1U_Y5V
10U_Y5V_OP
10U_Y5V_OP
T22
AF11
VTT50
VCCA_MPLL
VCC_NCTF48
RSVD6
N7
0402C
0402C
0805C
0805C
R22
H7
VTT51
VCC_NCTF49
RSVD7
150mA
B4
B4
M7
AH1
AD21
J19
VCC1_5_SW