Submitted to:-Mr.

Nilesh
Chaurasia
Submitted by:Description of VHDL Codes

The original standard for VHDL was adopted in 1987 called IEEE 1076. A

revised standard was adopted in 1993 and called IEEE 1164.

VHDL was originally intended to serve two main purposesFirst it was used as a documentation language for describing the structure

of complex digital circuits.

Second, VHDL provided features for modeling the behavior of a digital
circuit, which allowed its use as input to software program that were then

used to simulate the circuits operation.

The CAD tools are used to synthesize the VHDL code into hardware

implementation of described circuit.

The original VHDL standard, IEEE 1076, includes a data type called BIT. An
object of this type is well suited for representing digital signals. BIT objects

only two values 0and 1.

The first step to write a VHDL code is to declare input and output signals.
This is done using a construct called an entity. Entity must assign a name.

Input and output signals for entity are called its ports and written by
keyword PORT. Each port has an associated mode that specifies whether

it is an input (IN) to the entity or an output (OUT) from entity.

The circuits functionality is specified with a VHDL construct called an

architecture. The name of the architecture can be any text string.

VHDL has built in support for the following Boolean operators: AND, OR,

NOT, NAND, NOR, EX-OR, EXNOR.

Following BEGIN keyword, our architecture specifies using the VHDL signal
assignment operator <=, that output should be assigned the result of logic

expression on the right hand side of the operator.

VHDL does not assume any precedence of logic operators, therefore

parentheses are used in expression.

BIT keyword can assume only 0 and 1. To give more flexibility, VHDL
provides another data type called STD_LOGIC. Signals represented using
this can have several different values. It also assumes Z and d values. Z

represents high impedance state and d means dont care condition.

Signal is used to represent intermediate signals in the architecture.
Component declaration statement describes the component to be used.
PORTMAP is used to connect the component ports to the rest of the
circuit. It has to list the names of the architecture signals that shall be

used in the sub-module.

Std_logic_vector data type represents a linear array of std_logic data
objects. In VHDL, Std_logic_vector is said to be a subtype of std_logic.
BIT_VECTOR also exists corresponding to BIT.

VHDL code for OR gate

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity orgate is
port (in1: in std-logic;

In2: in std_logic;
Out1:out std_logic);
end orgate;
architecture behavioral of orgate is
begin
out1<=in1 or in2;
end behavioral;

VHDL code for AND gate

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity andgate is
port

(a: in std_logic;
b: in std_logic;
y:out std_logic);

end andgate;
architecture behavioral of andgate is
begin
out1<=a and b;
end behavioral;

VHDL code for multiplexer

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;
entity mux is
port

(a,b,c,d,s1,s2:in std_logic;
y:out std_logic);

end mux;
architecture behavioral of mux is
begin
y<=(a and not s1 and not s2)or(b and not s1 and s2)or(c and s1 and not s2)or(d
and s1 and s2);
end behavioral;

VHDL code for de-multiplexer

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux is
port(a,s1,s0: in std_logic;
y1,y2,y3,y4: out std_logic);
end demux;
architecture behavioral of demux is
begin
y1<=not s1 and not s0 and a;
y2<=not s1 and s0 and a;
y3<=s1 and not s0 and a;
y4<=s1 and s0 and a;
end behavioral;

VHDL code for encoder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity enc is
port(x0,x1,x2,x3: in std_logic;
s1,s0: out std_logic);
end enc;
architecture behavioral of enc is
begin
s1<=(not x0 and not x1 and x2 and not x3)or(not x0 and not x1 and not x2 and x3);
s0<=(not x0 and x1 and not x2 and not x3)or(not x0 and not x1 and not x2 and x3);
end enc;

VHDL code for decoder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dec is
port(a,b,en: in std_logic;
y1,y2,y3,y4:out std_logic);
end dec;
architecture behavioral of dec is
begin
y1<=not a and not b and en;

y2<=not a and b and en;

y3<= a and not b and en;
y4<=a and b and en;
end behavioral;

VHDL code for half adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ha is
port(a,b:in std_logic;
sum,carry: out std_logic);
end ha;
architecture behavioral of ha is
begin
sum<=(a and not b)or(not a and b);
carry<=a and b;
end behavioral;

VHDL code for full adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fa is

port(a,b: in std_logic;
sum,carry: out std_logic);
end fa;
architecture behavioral of fa is
signal d: std_logic;
begin
d<=(a and not b)or(not a and b);
sum<=(d and not c)or(not d and c);
carry<=(d and c)or(a and b);
end behavioral;

Structural coding
Or gate
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity or1 is
port

(x,y:in std_logic;
z: out std_logic);

end or1;
architecture behavioral of or1 is
begin
z<=x or y;

end behavioral;
entity circuit is
port(a,b: in bit;
c:out bit);
end circuit;
architecture str of circuit is
component orstr
port(x,y: in bit;
y:out bit);
end component;
begin
gate:orstr portmap(a,b,c);
end orstr;

And gate
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity and1 is
port(x:in std_logic;
y: in std_logic
z: out std_logic);
end and1;
architecture behavioral of and1 is
begin

z<=x and y;
end behavioral;
entity circuit is
port(a,b: in bit;
c:out bit);
end circuit;
architecture str of circuit is
component andstr
port(x,y: in bit;
z:out bit);
end component;
begin
gate:andstr portmap(a,b,c);
end notstr;

Not gate
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity not1 is
port(x:in std_logic;
y: out std_logic);
end not1;
architecture behavioral of not1 is
begin
y<=not x;

end behavioral;
entity circuit is
port(a: in bit;
b:out bit);
end circuit;
architecture str of circuit is
component notstr
port(x: in bit;
y:out bit);
end component;
begin
gate:notstr portmap(a,b);
end notstr;

Half adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ha1 is
port

(w,x:in std_logic;
y,z: out std_logic);

end ha1;
architecture behavioral of ha1 is
begin
s<=(a and not b)or(not a and b);
c<=a and b;

end behavioral;
entity circuit is
port(a,b: in bit;
c,d:out bit);
end circuit;
architecture str of circuit is
component hastr
port(w,x: in bit;
y,z:out bit);
end component;
begin
gate:hastr portmap(a,b,c,d);
end hastr;

Full adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fa1 is
port(x0,x1,x2:in std_logic;
y0,y1: out std_logic);
end fa1;
architecture behavioral of fa1 is
begin
a<=(x0 and not x1)or(not x0 and x1);

b<=x0 and x1;

c<=and x2;
y0<=(a and not x2)or(not a and x2);
y1<=c or b;
end behavioral;
entity circuit is
port(w0,w1,w2,w3: in bit;
z0,z1:out bit);
end circuit;
architecture str of circuit is
component fastr
port(x0,x1,x2: in bit;
y0,y1:out bit);
end component;
begin
gate:fastr portmap(w0,w1,w2,z0,z1);
end fastr;

multiplexer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity notx2 is
port(inn: in bit;
outn: out bit);
end notx2;

architecture behaviour1 of notx2 is

begin
outn<=not inn;
end behaviour1;
entity andx2 is
port(ina1, ina2, ina3, ina4:in bit;
outa1,outa2: out bit);
end andx2;
architecture behaviour2 of andx2 is
begin
outa1<=ina1 and ina2 and ina3;
end behaviour2;
entity orx2 is
port(in01,in02,in03,in04:in bit;
out01,out02: out bit);
end orx2;
architecture behaviour3 of orx2 is
begin outo1<=ino1 or ino2 or ino3 or ino4;
end behaviour3;
entity mux is
port(in1,in2,in3,in4,s1,s2:in bit;
out1:out bit);
end mux;
architecture behavioural of mux is
component notx2
port(inn1:in bit;

outn:out bit);
component andx2
port(ina1,ina2,ina3,ina4: in bit;
outa1: out bit);
end component;
component orx2
port(ino1,ino2,ino3,ino4: in bit;
outo1: out bit);
end component;
signal d0,d1,d2,d3,m1,m2: bit;
begin
notg1:notx2 portmap(s1,m1);
notg2:notx2 portmap(s2,m2);
andg1:andx2 portmap(m1,m2,in1,d0);
andg1:andx2 portmap(m1,s2,in2,d1);
andg1:andx2 portmap(s1,m2,in3,d2);
andg4:andx2 portmap(s1,s2,in4,d3);
org1:orx2 portmap(d0,d1,d2,d3,out1);
end behavioural;

De-multiplexer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity notx2 is
port(inn: in bit;

outn: out bit);

end notx2;
architecture behaviour1 of notx2 is
begin
outn<=not inn;
end behaviour1;
entity andx2 is
port(ina1, ina2, ina3, ina4:in bit;
outa1,outa2: out bit);
end andx2;
architecture behaviour2 of andx2 is
begin
outa1<=ina1 and ina2 and ina3;
end behaviour2;
entity demux is
port(in1,s1,s2:in bit;
out1:out bit);
end demux;
architecture behavioural of demux is
component notx2
port(inn1:in bit;
outn:out bit);
component andx2
port(ina1,ina2,ina3,ina4: in bit;
outa1: out bit);
end component;

signal d0,d1,d2,d3,m1,m2: bit;

begin
notg1:notx2 portmap(s1,m1);
notg2:notx2 portmap(s2,m2);
andg1:andx2 portmap(m1,m2,in1,d0);
andg1:andx2 portmap(m1,s2,in1,d1);
andg1:andx2 portmap(s1,m2,in1,d2);
andg4:andx2 portmap(s1,s2,in1,d3);
end behavioural;

VHDL code for Sequential circuits

D-latch
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dl is
port

(d: in std_logic;
clk:in std_logic;
q<=out std_logic);

end dl;
architecture behavioral of dl is
begin process(d,clk)
begin if clk=1 then
q<=d;

end if;
end process;
end behavioral;

D-flipflop
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dl is
port

(d: in std_logic;
clk:in std_logic;
q<=out std_logic);

end dl;
architecture behavioral of dl is
begin process(d,clk)
begin if clkevent and clk=1, then
q<=d;
end if;
end process;
end behavioral;

D-register
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dr is
port(d: in std_logic_vector(3 downto 0);
resetn,clk:in std_logic;
q:out std_logic_vector(3 downto 0));
end dr;
architecture behaviour of dr is
begin
process
begin if resetn=1 then
q<=0000;
else
q<=d;
end if;
end process;
end behaviour;

shift register
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity df is
port(d,clk,resetn:in bit;
q:out bit);
end df;
architecture behavioral of df is
begin process (d,clk,resetn)

begin
if resetn=0 then
q<=0;
else if clkevent and clk=1 then q<=d;
else
end if;
end process;
end behavioral;
entity reg is
port(dl,clkl,resetnl:in bit;
q<=out bit);
end reg;
architecture str of reg is
component df
port(d,clk,resetn:in bit;
q<=out bit);
end component;
signal m1.m2,m3:bit;
dfg1:df portmap(dl,clkl,m1,resetnl);
dfg1:df portmap(dl,m1,m2,resetnl);
dfg1:df portmap(dl,m2,m3,resetnl);
dfg4:df portmap(dl,m3,q1,resetnl);
end str;

J-K flip flop

library ieee;
use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jk is
port(j,k,clk:in bit;
q:inout bit);
end jk;
architecture behavioral of jk is
signal qm: std_logic;
begin
process(j,k,clk)
begin if clkevent and clk=1 then
qm<=(j and not q)or(not k and q);
end if;
end process;
q<=qm;
end behavioral;

Up-counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity upcnt is
port(clk: in std_logic;
q:inout std_logic_vector(3 downto 0);
rst:in std_logic);
end upcnt;

architecture behavioral of dn is
begin
process(clk)
begin
if rst=1 and clk=1 then
q<=0000;
end if;
if rst=0and clk=1 then
q<=q+1;
end if;
end process;
end behavioral;

Down-counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dncnt is
port(clk: in std_logic;
q:inout std_logic_vector(3 downto 0);
rst:in std_logic);
end dncnt;
architecture behavioral of dncnt is
begin
process(clk)
begin

if rst=1 and clk=1 then

q<=1111;
end if;
if rst=0and clk=1 then
q<=q-1;
end if;
end process;
end behavioral;

7- Segment driver
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seven_segment is
port(d: in std_logic_vector(3 downto 0);
y: out std_logic_vector(6 downto 0));
architecture behavioral of seven_segment is
begin
with d select
y<=1111110when0000,
0110000when0001,
1101101when0010,
1111001when0011,
0110011when0100,
1011011when0101,

1011111when0110,
1110000when0111,
1111111when1000,
1111011when1001;
0000000when others;
end behavioral;

Simulation
Steps for simulation
1.
2.
3.
4.
5.
6.

First, save the coding.

Right click on source file, click new source.
Click test bench waveform and write the filename.
Give the inputs in the waveform and save it.
Opt to behavioral simulation then close the window.
Open Xilinx ISE simulator and simulate the behavioral model.

Demultiplexer

Multiplexer

Seven segment

Encoder

d-latch

Half Adder

J-K Flip-Flop

Down-Counter