LA-9911P Lenovo IdeaPad G505

A
Compal Confidential
VAWGA/B Schematics Document
2
AMD "Kabini" Platform

AMD 25W APU With Jaguar Core and Integrated Yangtze FCH + ATI Sun
LA-9911P REV: 1.0

2013-04-01
2012/04/22
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2015/04/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
COVER PAGE
Document Number
Rev
1.0
VAWGA/GB
Monday, April 01, 2013
Sheet
E
of
48
Compal Confidential
Model Name : VAWGA/B
1
AMD Kabini
VRAM 1G/2G
256M16 x 4 (2G)
128M16 x 4 (1G) P.16~19
DDR3
Memory BUS(DDR3)
204pin DDRIII-SO-DIMM X2
Single Channel
PCIe x 4
HDMI Conn.
1.5V DDRIII 1600MHz
Gen2
GFX
VRAM 1GB/2GB
DDR3 x4
LVDS Conn.
page 10~15
P21
DP0
P20
DP1
P22
DAC
CMOS P.21
Camera
AMD FT3 APU
CRT Conn.
GPP
GPP2
MINI Card
(WLAN/BT)
P26
Jaguar Core
Integrated Yangtze FCH
LAN
Atheros
AR8162/8172
HDA
SPI
P.5
Touch
Screen
Port 4
P.26
Port 1
Port 0
2
MB P.27
3.0 Conn. LP2
Port 1
USB3.0
HD Audio
SATA
Gen3 Port 0
Port 1
HDD
Conn.
ODD
Conn.
P.28
PS2
P.23
Audio
Conexant
CX20757
P.23
P.31
P.4~P.7
Touch Pad
P.27
S/B
2.0 Conn.
Port 9
Port 0
LPC
ENE
KBC9012
P.30
Port 8
USB
P25
BIOS (4M)
USB2.0
Card P.30
Reader
Port 5
MB P.27
3.0 Conn. LP1
BGA 769-balls
P24
WLAN P.26
BT Combo
Port 3
USB
GPP1
Transformer
RJ45
Int.KBD
P.8~P.9
BANK 0, 1, 2
AMD Sun Pro M2
Thermal Sensor
P.30
P.29
Int. MIC
Int. Speaker Conn.

page 31
Audio Combo Jacks

HP & MIC
page 31
page 31
Sub-borad
15"
14"
IO/B
ODD/B
LS9633P
LS9634P
page 30
Power/B
LS9631P
page 30
page 23
LED/B
LS9635P
page 30
USB/B
2012/04/22
Issued Date
page 27
Compal Secret Data
LS9632P
2015/04/22
Deciphered Date
Title
Size
B
Date:
BLOCK DIAGRAMS
Document Number
Rev
1.0
VAWGA/GB
Thursday, March 28, 2013
Sheet
E
of
48
Voltage Rails
Description
S0
S3
S5
VIN
Adapter power supply (19V)
ON
ON
ON
B+
AC or battery power rail for power circuit.
ON
ON
ON
OFF
+APU_CORE
Core voltage for APU
ON
OFF
+APU_CORE_NB
Voltage for On-die VGA of APU
ON
OFF
OFF
+VGA_CORE
0.95-1.2V switched power rail
ON
OFF
OFF
+VDDCI
0.95-1.2V switched power rail
ON
OFF
OFF
3.3V always on power rail
ON
ON
OFF
+3VS
3.3V switched power rail
ON
OFF
OFF
+1.8VALW
ON
ON
ON*
+1.8VS
ON
OFF
OFF
+0.95VALW
ON
OFF
OFF
+0.95VS
ON
OFF
OFF
Board ID
+1.5V
1.5V power rail for APU and DDR
ON
ON
OFF
+1.5VS
ON
OFF
OFF
+3VGS
3.3V switched power rail for VGA
ON
OFF
OFF
+1.8VGS
ON
OFF
OFF
+1.5VGS
ON
OFF
OFF
+0.95VGS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON
+5VS
5V switched power rail
ON
OFF
OFF
0
1
2
3
4
5
6
7
+VSB
VSB always on power rail
ON
ON
ON
+RTC_APU
RTC power
ON
ON
ON
+0.75VS
0.75V switched power rail for DDR terminator
ON
OFF
OFF
SMBUS Control Table
APU_SCLK0
APU_SDATA0
SMB_EC_CK2
3
Board ID
0
1
2
3
4
5
6
7
+3VALW
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_DA2
BOARD ID Table
Power Plane
SOURCE
VGA
BATT
KB9012
KB9012
+3VALW
+3VALW
WLAN
SODIMM WWAN
+3VS
APU
+3VS
+3VS
KB9012
+3VS
+3VS
+3VS
SIGNAL
+VALW
+V
+VS
Full ON
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
ON
OFF
OFF
OFF
STATE
SLP_S3# SLP_S5#
Board ID / SKU ID Table for AD channel

Vcc
R1562
Thermal
Sensor FCH
PCB Revision
MP
PVT
DVT
EVT
3.3V +/- 5%
100K +/- 5%
R1564
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
APU
+3VS
RTD2132
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
0
1
2
3
Port
LAN
WLAN
X
USB Port Table
EC SM Bus1 address
EC SM Bus2 address
Device
Address
HEX
Device
Address
HEX
Smart Battery
0001 011X b
16H
Thermal Sensor
1001 101X b
9AH
SB-TSI (APU)
1001 100X b
98H
VGA Internal Thermal
USB 2.0 USB 3.0
1000 001X b
82H
APU
SM Bus address
XHCI
Device
Address
HEX
DDR DIMM1
1010 000Xb
A0H
DDR DIMM2
1010 001Xb
A2H
Port
0
1
3 External
USB Port
RIGHT USB
Touch Screen
Camera
CardReader
WLAN/BT Combo
LEFT USB (for colay)
LEFT USB (for colay)
LEFT USB3.0
LEFT USB3.0
A6@
A4@
E2@
E1@
E1PC@
X4@
X5@
X2@
EMICU@
EMICP@
EMIUSB2RU@
EMIUSB2RP@
USB2R@
SUN@
MARS@
14@
15@
PX@
CMOS@
HDMI@
EMIGASP@
8162@
8172@
SWR@
LDO@
THERMAL@
ME@
UMA@
@
ZODD@
TS@
EMIP@
EMIU@
ESDP@
ESDU@
2012/04/22
2015/04/22
Deciphered Date
Date:
BTO Item
2
A6 R3 BGA APU
A4 R3 BGA APU
E2 R3 BGA APU
E1 R3 BGA APU
E1 PC BGA APU
X4 ES2 BGA APU
X5 ES2 BGA APU
X2 ES2 BGA APU
CardReader EMI Un pop
CardReadear EMI pop
Right USB2.0 port EMI un pop
Right USB2.0 port EMI pop
Right USB2.0 port component
SUN PRO GPU (R3 compal part)
MARS XT GPU (R1 compal part)
for 14" componect
for 15" componect

Common VGA circuit
CMOS Camera part
HDMI part
Gastube
Ateros AR8162 LAN Chip
Ateros AR8172 LAN Chip
LAN Switching mode
LAN LDO mode
Lenovo Thermal Sensor
ME part
UMA part
Unpop
Zero Power ODD part
Touch Screen
EMI pop component
EMI Un pop component

ESD pop component
ESD Un pop component
Title
Size
B
A
USB30 port0,1
Compal Secret Data
Issued Date
0
1
2
3
4
5
6
7
8
9
USB20 port1,2,8,9
BOM Structure
Device
0
1
2
3
USB Port
USB20 port0
BOM Structure Table
APU PCIE PORT LIST
USB OC MAPPING
OC#
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
Clock
NOTES LIST
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
of
48
M_DATA0
M_ADD1
M_DATA1
M_ADD2
M_DATA2
M_ADD3
M_DATA3
M_ADD4
M_DATA4
M_ADD5
M_DATA5
M_ADD6
M_DATA6
M_ADD7
M_DATA7
M_ADD9
M_DATA8
M_ADD10
M_DATA9
M_ADD11
M_DATA10
M_ADD12
M_DATA11
M_ADD13
M_DATA12
M_ADD14
M_DATA13
M_ADD15
M_DATA14
M_BANK1
M_DATA16
M_BANK2
M_DATA17
M_DM0
M_DATA19
M_DM1
M_DATA20
M_DM2
M_DATA21
M_DM3
M_DATA22
M_DM4
M_DATA23
M_DM6
M_DATA24
M_DM7
M_DATA25
M_DM8
M_DATA26
M_DQS_H0
M_DATA28
M_DQS_L0
M_DATA29
M_DQS_H1
M_DATA30
M_DQS_L1
<8,9>
<8,9>
M_DATA31
M_DQS_L2
M_DATA32
M_DQS_H3
M_DATA33
M_DQS_L3
M_DATA34
M_DQS_H4
M_DATA35
M_DQS_L4
M_DATA36
M_DQS_H5
M_DATA37
M_DQS_L5
M_DATA38
M_DQS_H6
M_DATA39
M_DQS_H7
M_DATA40
M_DQS_L7
M_DATA41
M_DQS_H8
M_DATA42
M_DQS_L8
M_DATA43
DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1
M_DATA45
M_CLK_L0
M_DATA46
M_CLK_H1
M_DATA47
DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1
<8>
<8>
<9>
<9>
DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#
AJ34
AR38
AL38
AN35
AJ37
AL34
AL35
+MEM_VREF
+VREF_DQ
1
R576
AD40
2
AC38
0_0402_5%
M_DATA48
M_CLK_L2
M_DATA49
M_CLK_H3
M_DATA50
M_CLK_L3
M_DATA51
M_RESET_L
M_DATA53
M_EVENT_L
M_DATA54
AM41
AN40
AT41
AU40
AL40
AM40
AR40
AT40
DDRAB_SDQ40
DDRAB_SDQ41
DDRAB_SDQ42
DDRAB_SDQ43
DDRAB_SDQ44
DDRAB_SDQ45
DDRAB_SDQ46
DDRAB_SDQ47
AV41
AW40
BA38
AY37
AU41
AV40
AY39
AY38
DDRAB_SDQ48
DDRAB_SDQ49
DDRAB_SDQ50
DDRAB_SDQ51
DDRAB_SDQ52
DDRAB_SDQ53
DDRAB_SDQ54
DDRAB_SDQ55
BA36
AY35
BA32
AY31
BA37
AY36
BA33
AY32
DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDQ58
DDRAB_SDQ59
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQ62
DDRAB_SDQ63
DP2_TXP3
DP2_TXN3
<21>
<21>
LVDS_A2
LVDS_A2#
<21>
<21>
LVDS_A1
LVDS_A1#
LVDS
<21>
<21>
LVDS_A0
LVDS_A0#
<21>
<21>
LVDS_ACLK
LVDS_ACLK#
A10
B10
TDP1_TXP1
A11
B11
TDP1_TXP2
A12
B12
TDP1_TXP3
TDP1_TXN1
TDP1_TXN2
M0_CKE1
M_DATA56
M1_CKE0
M_DATA57
M1_CKE1
M_DATA58
M0_ODT0
M_DATA60
M0_ODT1
M_DATA61
M1_ODT0
M_DATA62
M1_ODT1
M_DATA63
M0_CS_L0
M_CHECK0
M0_CS_L1
M_CHECK1
M1_CS_L0
M_CHECK2
M1_CS_L1
M_CHECK3
M_CAS_L
M_CHECK6
M_WE_L
M_CHECK7
V41
W40
AB40
AC40
U41
V40
AA41
AB41
M_ZVDDIO_MEM_S
AD41
M_RAS_L
M_CHECK5
APU_SVT
APU_SVC
APU_SVD
<11,28,29>
<11,28,29>
R124 1
R127 1
EC_SMB_CK2
EC_SMB_DA2
<40>
TDP1_TXN3
<40>
LTDP0_AUXP
LTDP0_AUXN
D15
E15
A5
B5
LTDP0_TXP1
LTDP0_HPD
H17
DAC_RED
B14
LTDP0_TXP2
LTDP0_TXN2
DAC_GREEN
A14
A7
B7
LTDP0_TXP3
DAC_BLUE
B15
DAC_HSYNC
G19
E19
APU_SIC
APU_SID
B22
B21
UAPU
DISP_CLKIN_H
H_PROCHOT#
B20
A20
APU_RST#
LDT_RST#
SVD
M_ZVDDIO
X5@
DAC_ZVSS
A16
R416 1
DAC_ZVSS
<20>
EDID_CLK
EDID_DATA
<21>
<21>
DAC_RED
<22>
DAC_GRN
<22>
DAC_BLU
<22>
CRT_HSYNC
CRT_VSYNC
<22>
<22>
CRT_DDC_CLK
CRT_DDC_DATA
<22>
<22>
CRT
+3VS
APU_RST_L
R118 1
R120 1
2 0_0402_5% APU_PROCHOT#
APU_ALERT#
PROCHOT_L
A22
B18
D29
D31
D35
D33
G27
B25
A25
LDT_RST_L
LDT_PWROK
ALERT_L
TDI
TDO
A6@
UAPU
AV33
AU33
A4@
APU_BP0
APU_BP1
APU_BP2
APU_BP3
APU_PLLTEST1
APU_PLLTEST0
APU_BPCLK_H
APU_BPCLK_L
EDID_CLK
EDID_DATA
R255 2
R256 2
RP23
8
7
6
5
T39
T40
T41
A29
FREE_2
GIO_TSTDTM0_SERIALCLK H21
TRST_L
DBRDY
GIO_TSTDTM0_CLKINIT
DAC_BLU
DAC_GRN
DAC_RED
DP_150_ZVSS
T42
APU_SCLK
APU_CLKINT
H25
1
2
3
4
150_0804_8P4R_1%
TCK
TMS
1 4.7K_0402_5%
1 4.7K_0402_5%
DBREQ_L
VDDCR_NB_SENSE
USB_ATEST1
VDDCR_CPU_SENSE
M_ANALOGIN
VDDIO_MEM_S_SENSE
M_ANALOGOUT
VSS_SENSE
TMON_CAL
AJ10
AJ8
R32
N32
AP29
HDMI_EN/DP_STEREOSYNCE21
VDD_095_FB_H
T45
T43
T44
T46
T47
DP_STEREOSYNC
VDD_095_FB_L
FT3 REV 0.51
UAPU
A4 PR KABINI AM5000IBJ44HM 1.5G BGA 769P APU
E1@
X4@
APU_PWRGD
C1270
ESDU@
1
2
100P_0402_50V8J
APU_RST#
ESDU@
2
100P_0402_50V8J
APU_TRST#
@
C164
0.1U_0402_16V7K
3
5
@ RP11
11
1
2
3
4
PU +3VS
+3VS
APU_ALERT#
APU_SID
APU_PROCHOT#
APU_SIC
R114
1K_0402_5%
X2@
UAPU
E1PC@
8
7
6
5
13
15
10K_0804_8P4R_5%
17
19
+MEM_VREF
10
11
12
13
14
15
16
19
R80
R82
R18
1
1
1
8
7
6
5
1K_0804_8P4R_5%
2 300_0402_5%
2 300_0402_5%
2 511_0402_1%
+1.8VS
17
APU_RST#
APU_PWRGD
APU_BPCLK_L
+1.8VS
RP5 @
1
2
3
4
APU_SVT
APU_SVC
APU_SVD
E1 PC 2M101082J2361 1G BGA 769P
PU +1.8VS + PD
8
7
6
5
1K_0804_8P4R_5%
PU +1.8VS
For HDMI Need
+3VS
RP4
1
2
3
4
R113
1K_0402_5%
DP_STEREOSYNC
CRT_HSYNC
2
+1.5V
R74
39.2_0402_1%
JHDT2
ESDP@ C195
0.1U_0402_16V7K
+1.8VS
FT3_BGA769
E2@
18
20
APU_TCK
APU_TMS
APU_TDI
APU_TDO
RP6
APU_TDI
APU_TMS
APU_TCK
APU_DBREQ#
1
2
3
4
APU_SCLK
APU_CLKINT
APU_SCLK
APU_CLKINT
1K_0804_8P4R_5%
10
APU_PWRGD
12
APU_RST#
14
APU_DBRDY
16
APU_DBREQ#
18
APU_PLLTEST0
20
APU_PLLTEST1
+1.8VS
RP3 @
8
7
6
5
1
2
3
4
8
7
6
5
1K_0804_8P4R_5%
PD
RP7 @
APU_BP2
APU_BP3
APU_BP0
APU_BP1
1
2
3
4
APU_TRST#
APU_PLLTEST0
APU_PLLTEST1
1
2
3
4
8
7
6
5
1K_0804_8P4R_5%
RP8
+1.8VS
8
7
6
5
4
1K_0804_8P4R_5%
RP11, RP6 will @ when MP

R19 1
APU_BPCLK_H
2 511_0402_1%
MEM_MAB_EVENT#
1
1K_0804_8P4R_1%
2
2
C337
1U_0402_6.3V6K
@ SAMTE_ASP-136446-07-B
C163
0.1U_0402_16V7K
2012/04/22
Issued Date
Compal Secret Data
2015/04/22
Deciphered Date
Title
FT3 DDR3/DISP/MISC//HDT+
Size Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
2 499_0402_1%
FT3_BGA769
DAZ0Y700101
8
7
6
5
<20,22>
<20,22>
HDMI_DET
THERMDC
E2 PR KABINI EM3000IBJ23HM 1.65G BGA 769P APU
FT3 REV 0.51
RP2
1
2
3
4
HDMI_CLK
HDMI_DATA
THERMDA
SID
APU_PWROK
APU_VDD_RUN_FB_L
A6 PR KABINI AM5200IAJ44HM 2G BGA769P APU
+1.5V
DAC_SDA
D19
D21
H27
H29
D25
BP0 A27
BP1 B27
BP2 A26
BP3 B26
PLLTEST1 B28
PLLTEST0 A28
BYPASSCLK_H B24
BYPASSCLK_L A24
PLLCHRZ_H AV35
PLLCHRZ_L AU35
M_TEST E33
SIC
B19
APU_PWRGD
2 0_0402_5%
LDT_PWRGD A19
D23
G23
E25
E23
UAPU
M_VREFDQ
+VREF_DQ
CRT_HSYNC
SVC
2 0_0402_5%
C1273
DAC_VSYNC
SVT
+1.8VS
@
C342
1U_0402_6.3V6K
<28>
<21>
<21>
+3VS
DISP_CLKIN_L
E1 PR KABINI EM2100ICJ23HM 1G BGA769P APU
15@
2 100K_0402_5%
LTDP0_TXN3
X2 ES2 KABINI ZMA5B078J2360 1.65G BGA CPU
MEMORY VREF
R897 1
ENBKL
APU_ENVDD
APU_INVT_PWM
LTDP0_TXN1
A6
B6
G31
D27
E29
APU_VDDNB_SEN
APU_VDD_SEN
UAPU
X5 ES2 ZM201079J4460 2G BGA 769P

DAZ0Y600101
H19
LTDP0_TXN0
HDT+
LA9911P
TDP1_HPD
LTDP0_TXP0
APU_SVT
APU_SVC
APU_SVD
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
<40>
<40>
2 2K_0402_1%
DIECRACKMON
APU_PWRGD
<28,34,40,6>
2 0_0402_5%
2 0_0402_5%
@
@
R117 1
M_VREF
UAPU
14@
D17
E17
DAC_SCL
ZZZ
LA9911P
TDP1_AUXN
TDP1_AUXP
A4
B4
K15
H15
<40>
<40>
<40>
R400 1
M0_CKE0
X4@
ZZZ
DDRAB_SDQ32
DDRAB_SDQ33
DDRAB_SDQ34
DDRAB_SDQ35
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDQ38
DDRAB_SDQ39
<20>
<20>
DP_150_ZVSS
DP_2K_ZVSS
DP_BLON
USB_ATEST0
M_CLK_H2
M_CHECK4
DDRAB_SRAS#
DDRAB_SCAS#
DDRAB_SWE#
AF40
AF41
AK40
AK41
AE40
AE41
AJ40
AJ41
DP2_TXP2
DP2_TXN2
DP_2K_ZVSS
M_CLK_L1
M_DATA59
AN38
AU38
AN37
AR37
<8>
<8>
<9>
<9>
<8,9>
<8,9>
<8,9>
M_CLK_H0
M_DATA55
L34
J38
J37
J34
DDRAB_SDQ24
DDRAB_SDQ25
DDRAB_SDQ26
DDRAB_SDQ27
DDRAB_SDQ28
DDRAB_SDQ29
DDRAB_SDQ30
DDRAB_SDQ31
<20>
<20>
HDMI
M_DQS_L6
M_DATA52
G38
MEM_MAB_EVENT# AE34
MEM_MAB_RST#
MEM_MAB_EVENT#
<8>
<8>
<9>
<9>
AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
M41
N40
T41
U40
L40
M40
R40
T40
M_DQS_H2
M_DATA44
<8>
<8>
<8>
<8>
<9>
<9>
<9>
<9>
DDRAB_SDQ16
DDRAB_SDQ17
DDRAB_SDQ18
DDRAB_SDQ19
DDRAB_SDQ20
DDRAB_SDQ21
DDRAB_SDQ22
DDRAB_SDQ23
DP2_TXP1
DP2_TXN1
B16
A21
B17
DP_DIGON A17
DP_VARY_BL A18
DP_150_ZVSS
TDP1_TXN0
B33
A33
B40
A40
H41
H40
P41
P40
AH41
AH40
AP41
AP40
BA40
AY41
AY33
BA34
AA40
Y41
DDRAB_SDQS0
DDRAB_SDQS0#
DDRAB_SDQS1
DDRAB_SDQS1#
DDRAB_SDQS2
DDRAB_SDQS2#
DDRAB_SDQS3
DDRAB_SDQS3#
DDRAB_SDQS4
DDRAB_SDQS4#
DDRAB_SDQS5
DDRAB_SDQS5#
DDRAB_SDQS6
DDRAB_SDQS6#
DDRAB_SDQS7
DDRAB_SDQS7#
F40
F41
K40
K41
E40
E41
J40
J41
<20>
<20>
UAPUC
DISPLAY/SVI2/JTAG/TEST
TDP1_TXP0
M_DM5
M_DATA27
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
<8,9>
DDRAB_SDQ8
DDRAB_SDQ9
DDRAB_SDQ10
DDRAB_SDQ11
DDRAB_SDQ12
DDRAB_SDQ13
DDRAB_SDQ14
DDRAB_SDQ15
A9
B9
DP2_TXP0
DP2_TXN0
B32
B38
G40
N41
AG40
AN41
AY40
AY34
Y40
B37
A38
D40
D41
B36
A37
B41
C40
<20>
<20>
M_BANK0
M_DATA18
DDRAB_SDM0
DDRAB_SDM1
DDRAB_SDM2
DDRAB_SDM3
DDRAB_SDM4
DDRAB_SDM5
DDRAB_SDM6
DDRAB_SDM7
DDRAB_SDQ0
DDRAB_SDQ1
DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ4
DDRAB_SDQ5
DDRAB_SDQ6
DDRAB_SDQ7
M_ADD8
M_DATA15
AJ38
AG35
N34
DDRAB_SBS0#
DDRAB_SBS1#
DDRAB_SBS2#
DDRAB_SDM[7..0]
B30
A32
B35
A36
B29
A30
A34
B34
M_ADD0
HDMI & LVDS should be reverse in KABINI:

APU TX0 to Connector TX2 ; APU TX1 to Connector TX1
APU TX2 to Connector TX0 ; APU TX3 to Connector CLK
<8,9>
DDRAB_SDQ[63..0]
MEMORY
DDRAB_SMA0 AG38
DDRAB_SMA1 W35
DDRAB_SMA2 W38
DDRAB_SMA3 W34
DDRAB_SMA4 U38
DDRAB_SMA5 U37
DDRAB_SMA6 U34
DDRAB_SMA7 R35
DDRAB_SMA8 R38
DDRAB_SMA9 N38
DDRAB_SMA10 AG34
DDRAB_SMA11 R34
DDRAB_SMA12 N37
DDRAB_SMA13 AN34
DDRAB_SMA14 L38
DDRAB_SMA15 L35
<8,9>
<8,9>
<8,9>
<8,9>
UAPUA
DDRAB_SMA[15..0]
<8,9>
Rev
1.0
VAWGA/GB
Sheet
E
of
48
UAPUB
APU POWER SEQUENCE
PCIE
<24>
<24>
LAN
<26>
<26>
WLAN
PCIE_DTX_C_ARX_P1
PCIE_DTX_C_ARX_N1
PCIE_DTX_C_ARX_P2
PCIE_DTX_C_ARX_N2
R10
R8
P_GPP_RXP0
P_GPP_TXP0
P_GPP_RXN0
P_GPP_TXN0
R5
R4
P_GPP_RXP1
P_GPP_TXP1
P_GPP_RXN1
P_GPP_TXN1
N5
N4
P_GPP_RXP2
P_GPP_TXP2
P_GPP_RXN2
P_GPP_TXN2
N10
N8
P_GPP_RXP3
P_GPP_TXP3
P_GPP_RXN3
P_GPP_TXN3
L2
L1
+RTC
G-A
K2
K1
PCIE_ATX_DRX_P1
PCIE_ATX_DRX_N1
C19
C20
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
J2
J1
PCIE_ATX_DRX_P2
PCIE_ATX_DRX_N2
C17
C18
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
EC_ON
PCIE_ATX_C_DRX_P1 <24>
PCIE_ATX_C_DRX_N1 <24>
LAN
PCIE_ATX_C_DRX_P2 <26>
PCIE_ATX_C_DRX_N2 <26>
WLAN
+3VALW/+5VALW
G-B
H2
H1
+1.8VALW
+0.95VALW
1
+0.95VS_APU_GFX
VGA
2 P_TX_ZVDD_095
R404
1.69K_0402_1%
<10>
<10>
PCIE_GTX_C_ARX_P0
PCIE_GTX_C_ARX_N0
<10>
<10>
PCIE_GTX_C_ARX_P1
PCIE_GTX_C_ARX_N1
<10>
<10>
PCIE_GTX_C_ARX_P2
PCIE_GTX_C_ARX_N2
<10>
<10>
PCIE_GTX_C_ARX_P3
PCIE_GTX_C_ARX_N3
W8
P_RX_ZVDD_095 W7
P_TX_ZVDD_095
L5
L4
P_GFX_RXP0
P_GFX_TXP0
P_GFX_RXN0
P_GFX_TXN0
J5
J4
P_GFX_RXP1
P_GFX_TXP1
P_GFX_RXN1
P_GFX_TXN1
G5
G4
P_GFX_RXP2
P_GFX_TXP2
P_GFX_RXN2
P_GFX_TXN2
D7
E7
P_GFX_RXP3
P_GFX_TXP3
P_GFX_RXN3
P_GFX_TXN3
P_RX_ZVDD_095
1
R73
1K_0402_1%
+0.95VS_APU_GFX
SYSON
+1.5V
G-C
G2
G1
PCIE_ATX_GRX_P0 C1 PX@
PCIE_ATX_GRX_N0 C2 PX@
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_ATX_C_GRX_P0 <10>
PCIE_ATX_C_GRX_N0 <10>
F2
F1
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
E2
E1
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
D2
D1
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
SUSP#
+3VS
G-D
+1.8VS
VGA
+1.5VS
+0.95VS
VR_ON
+APU_CORE
G-E
FT3 REV 0.51
X4@
+APU_CORE_NB
FT3_BGA769
UAPUE
2
CLK/SATA/USB/SPI/LPC
R90
R96
2
2
AL4
AL5
SATA_RX0P
SATA_TX1N
USB_HSD1P
AY17
BA17
SATA_RX1N
AR19
AP19
SATA_ZVSS
BA30
SATA_ACT_L/GPIO67
AY12
SATA_X1
SATA_RX1P
USB_HSD2P
USB_HSD2N
SATA_ZVDD_095
USB_HSD3P
USB_HSD3N
T48
USB_HSD4P
USB_HSD4N
USB_HSD5P
USB_HSD5N
BA12
SATA_X2
USB_HSD6P
USB_HSD6N
VGA
<10>
<10>
R112 1
R115 1
CLK_PEG_VGA
CLK_PEG_VGA#
0_0402_5%
2
@
2
@
0_0402_5%
2
R125 1
@
2
R126 1
@
0_0402_5%
LAN
<24>
<24>
<26>
<26>
0_0402_5%
2
@
2
@
0_0402_5%
R116 1
R119 1
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
GFX_CLKP
GFX_CLKN
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
WLAN
U4
U5
GFX_CLKP
USB_HSD7P
GFX_CLKN
USB_HSD7N
AC8
AC10
GPP_CLK0P
USB_HSD8P
GPP_CLK0N
USB_HSD8N
AE4
AE5
GPP_CLK1P
USB_HSD9P
GPP_CLK1N
USB_HSD9N
AC4
AC5
GPP_CLK2P
AA5
AA4
GPP_CLK3P
USB_SS_0TXP
GPP_CLK3N
USB_SS_0TXN
X14M_25M_48M_OSC
USB_SS_0RXP
AP13
USB_SS_ZVSS
USB_SS_1TXN
N1
X48M_X2
USB_SS_1RXP
R103 R104 for EMI

<28,6>
<6>
R103 1
R104 1
LPC_CLK0_EC
LPC_CLK1
<28>
<28>
<28>
<28>
<28,6>
<28>
USB_SS_1RXN
@
@
2 0_0402_5%
2 0_0402_5%
AY2
AW2
SERIRQ
T50
AT2
AT1
AR2
AR1
AP2
AP1
AV29
AP25
AV2
USB20_P1
USB20_N1
<26>
<26>Touch
USB20_P3
USB20_N3
<21>
<21>CAMERA
USB20_P4
USB20_N4
<30>
<30>CardReader
USB20_P5
USB20_N5
<26>
<26>WLAN/BT
USB20_P6
USB20_N6
<27>
<27>USB2.0
LP1
USB20_P7
USB20_N7
<27>
<27>USB2.0
LP2
USB30_P8
USB30_N8
<27>
<27>MB
USB3.0 port0
USB30_P9
USB30_N9
<27>
<27>MB
USB3.0 port1
USB port
Screen
AG1
AG2
AF1
AF2
AE1
AE2
AD1
AD2
AC1
AC2
AB1
AB2
AA1
AA2
AE10
USBSS_ZVSS R644 1
USBSS_ZVDD R645 1
T2
T1
2 1K_0402_1%
2 1K_0402_1%
48MHz CRYSTAL
combo
48M_X2
R938
1M_0402_5%
+0.95VALW
RP12
APU_SPI_AISO
APU_SPI_AOSI_U
APU_SPI_CLK_U
APU_SPI_CS1#_U
USB30_MRX_DTX_P0<27>
USB30_MRX_DTX_N0<27>
R1
R2
<27>
USB30_MTX_C_DRX_P1
<27>
USB30_MTX_C_DRX_N1
W1
W2
1
2
3
4
8
7
6
5
EC_SPI_AISO
EC_SPI_AOSI
EC_SPI_CLK
EC_SPI_CS1#
SPI_CLK/GPIO162
AU7
APU_SPI_CLK
APU_SPI_CS1#
SPI_CS2_L/GPIO166 AR4
LAD0
AR11
SPI_DI/GPIO164 AR7
SPI_HOLD_L/GEVENT9_LAU11
SPI_WP_L/GPIO161 AU9
LAD1
SPI_DO/GPIO163
LAD2
LAD3
LFRAME_L
APU_SPI_AOSI
APU_SPI_AISO
APU_SPI_HOLD#
APU_SPI_WP#
T51
R110 1
R111 1
2 33_0402_5% APU_SPI_CLK_U
2 33_0402_5% APU_SPI_CS1#_U
R109 1
2 33_0402_5% APU_SPI_AOSI_U
APU_SPI_AISO
LDRQ0_L
X4@
FT3_BGA769
<28>
<28>
<28>
<28>
EC_SPI_AISO
EC_SPI_AOSI
EC_SPI_CLK
EC_SPI_CS1#
C795
6P_0402_50V8
+3VALW
@
R108 1
R614
10K_0402_5%
1
2 APU_SPI_CS1#_U
APU_SPI_AISO_U
1
2 APU_SPI_WP#
R616
10K_0402_5%
2 33_0402_5%
U56
1
2
3
4
CS#
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
8
7
6
5
APU_SPI_HOLD#
APU_SPI_CLK_U
APU_SPI_AOSI_U
APU->EC->ROM must route as

W25Q32FVSSIG SOIC 8P SPI ROM
Daisy Chain for Share ROM quality
APU_SPI_CLK_U 1
(RP12 was request to added for the recoverable solution
as original method--backup)
2012/04/22
1
C635
0.1U_0402_16V4Z
2
R615
10K_0402_5%
4
2
1
2
R617 EMIU@
10_0402_5%
C636 EMIU@
10P_0402_50V8J
Compal Secret Data
Issued Date
C794
6P_0402_50V8
+3VALW
LPC_CLKRUN_L
LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L
4MB SPI ROM

(Current Share mode)
R108 close to ROM
SERIRQ/GPIO48
0_0804_8P4R_5%
USB30_MRX_DTX_P1<27>
USB30_MRX_DTX_N1<27>
R109,R110,R111 close to APU

LPCCLK1
Y20
48MHZ_8PF_X3S048000D81H-W
<27>
USB30_MTX_C_DRX_P0
<27>
USB30_MTX_C_DRX_N0
V2
V1
48M_X1
LPCCLK0
FT3 REV 0.51
<27>
<27>Right
AG7
AG8
SPI_CS1_L/GPIO165 AW9
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
USB20_P0
USB20_N0
X48M_X1
USB_SS_1TXP
48M_X2
AJ4
AJ5
AE8
USB_SS_ZVDD_095_USB3_DUAL
GPP_CLK2N
USB_SS_0RXN
N2
48M_X1
2 11.8K_0402_1%
SATA_TX1P
USB_HSD1N
1 1K_0402_1% SATA_ZVSS
1 1K_0402_1% SATA_ZVDD
R641 1
AY19
BA19
<23> SATA_DTX_C_ARX_N1
<23> SATA_DTX_C_ARX_P1
+0.95VS
USB_HSD0P
USB_ZVSS
SATA_RX0N
USB_HSD0N
<23> SATA_ATX_DRX_P1
<23> SATA_ATX_DRX_N1
ODD
USB_ZVSS
AG4
BA16
AY16
<23> SATA_DTX_C_ARX_N0
<23> SATA_DTX_C_ARX_P0
SATA_TX0N
HDD
W4
USBCLK/14M_25M_48M_OSC
SATA_TX0P
BA14
AY14
<23> SATA_ATX_DRX_P0
<23> SATA_ATX_DRX_N0
2015/04/22
Deciphered Date
Title
FT3 PCIE/SATA/CLK/USB/SPI
Rev
1.0
VAWGA/GB
Date:
Sheet
E
of
48
ACPI/SD/AZ/GPIO/RTC/MISC
LPC_RST_A#
APU_PCIE_RST#_BUF
EC_RSMRST#_R
AY4
AY9
LPC_RST_L
AY5
RSMRST_L
SD_PWR_CTRL
PCIE_RST_L
SD_CLK/GPIO73
SD_CMD/GPIO74
SD_CD/GPIO75
<26>
PBTN_OUT#
PWR_GOOD_APU
T36
APU_PCIE_WAKE#
APU_PCIE_WAKE#
<28>
<28>
PWR_BTN_L
SD_WP/GPIO76
AY3
BA5
TEST0
CS_JTAG_TMS_TEST1
TEST2
AU13
AY10
AY6
AR23
AR31
AN5
AL7
KBRST#
GATEA20
EC_SCI#
EC_SMI#
BA22
AY21
AY24
SD_DATA3/GPIO80 BA24
SYS_RESET_L/GEVENT19_L
SD_DATA0/GPIO77
WAKE_L/GEVENT8_L
SD_DATA1/GPIO78
SLP_S3_L
SD_LED/GPIO45
AY25
TEST1/TMS
SCL0/GPIO43
TEST2
SDA0/GPIO47
AU25
AV25
KBRST_L
SCL1/GPIO227
GA20IN/GEVENT0_L
<11>
VGA_CLKREQ#
<27>
<27>
<31>
T53
1
R578
2
VGA_CLKREQ#_R
0_0402_5%
USB_OC0#
USB_OC1#
T52
T54
HDA_SDIN0
T55
T56
T57
AU29
AW29
AR27
AV27
AY29
AY8
AW1
AV1
AY1
AN2
AN1
AK2
AK1
AM1
AL2
AM2
AL1
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SYNC
HDA_RST#
32K_X1
AJ2
32K_X2
AJ1
C912
150P_0402_50V8J
SDA1/GPIO228
APU_SCLK0
APU_SDATA0
AY11
BA11
LPC_SMI_L/GEVENT23_L
GPIO49
AC_PRES/IR_RX0/GEVENT16_L
GPIO55
IR_TX0/GEVENT21_L
GPIO57
IR_TX1/GEVENT6_L
GPIO58
IR_RX1/GEVENT20_L
GPIO59
IR_LED_L/LLB_L/GPIO184
GPIO64
CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60
GPIO68
CLK_REQ1_L/GPIO61
GPIO69
CLK_REQ2_L/GPIO62
GPIO70
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
GPIO71
CLK_REQG_L/GPIO65/OSCIN
GPIO174
AP27
AY28
BA28
AV23
AP21
BA26
AV19
AY27
BA27
AU21
AY26
AV21
AM21
BA3
R122 1
2 0_0402_5%
R661 1
@
APU_GPIO174
USB_OC2_L/TCK/GEVENT14_L
USB_OC3_L/TDO/GEVENT15_L
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
EC_LID_OUT#
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
GENINT1_L/GPIO32
AZ_SDIN3/GPIO170
GENINT2_L/GPIO33
BA29
AP23
FANIN0/GPIO56
AV31
AU31
RTCCLK
AV11
FANOUT0/GPIO52
If use as SMBUS :
Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
Qty: 1; Value: 2.2 K; Tol: 5%
If no use :
Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
Qty: 1; Value: 10 K; Tol: 5%
BT_OFF#
<26>
WL_OFF#
ODD_EN
<26>
<23>
PXS_RST#
APU_SPKR
PXS_PWREN
<10>
<31>
<12,28,39>
+3VS
UMA@
R911
10K_0402_5%
Board_ID1
Board_ID1
Function
<28,34,4,40>
H_PROCHOT#
PX5.5
UMA
PX@ R912
10K_0402_5%
32.768KMHz CRYSTAL
<28>
EC_LID_OUT#
32K_X1
VGA_PWRGD
AZ_SYNC
AZ_RST_L
<10,24,26>
GEVENT2#
GEVENT2_L
USB_OC1_L/TDI/GEVENT13_L
Board_ID1
2 0_0402_5%
PXS_PWREN
AV17
GEVENT4_L BA4
GEVENT7_L AR15
GEVENT10_L AP17
GEVENT11_L AP11
GEVENT17_L AN8
BLINK/GEVENT18_L AU17
GEVENT22_L BA6
USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
APU_PCIE_RST#
1
<26,8,9>
<26,8,9>
APU_SCLK0
APU_SDATA0
APU_SCLK1
APU_SDATA1
LPC_PME_L/GEVENT3_L
SPKR/GPIO66
LAN_CLKREQ#
WLAN_CLKREQ#
2
R907
33_0402_5%
TEST0
GPIO51
LAN_CLKREQ#
WLAN_CLKREQ#
APU_PCIE_RST#_BUF
SLP_S5_L
GPIO50
AP15
AV13
BA9
BA10
AV15
<24>
<26>
AY23
AY20
BA20
PWR_GOOD
SD_DATA2/GPIO79
SLP_S3#
SLP_S5#
<28>
<28>
<28>
<28>
BA8
AM19
AY7
AW11
<28>
BA23
AY22
2
R602
33_0402_5%
LPC_RST#
UAPUD
C615
150P_0402_50V8J
<28>
<39>
VGA_PWRGD
32K_X2
R914
20M_0402_5%
<26>
BT_DISABLE#
X32K_X1
Y3
32.768KHZ_12.5P_1TJF125DP1A000D
X32K_X2
<28>
RTC_CLK
FT3 REV 0.51
X4@
FT3_BGA769
PU +3VALW + PD
1
C682
22P_0402_50V8J
C686
18P_0402_50V8J
+3VALW
RP13
2 10K_0402_5%
<31>
<31>
<31>
<31>
1
2
3
4
HDA_RST#_AUDIO
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
8
7
6
5
HDA_RST#
HDA_SYNC
HDA_BITCLK
HDA_SDOUT
STRAPS OF APU
33_0804_8P4R_5%
LPC_FRAME#
PU +3VALW
NORMAL POWR
UP/RESET TIMING
(DEFAULT)
EC_RSMRST# , POWER_GOOD
follow CRB
(APU side 1.8V power rail)
+1.8VALW
Must connected to 10 ms RC delay

circuit on +1.8-V S5 power rail.
LPC ROM
BOOT FAIL TIMER

DISABLED
(DEFAULT)
CLKGEN
DISABLED
3.3V SPI ROM

(DEFAULT)
FAST POWER
UP/RESET TIMING
FOR SIMULATION
R345
47K_0402_5%
R685
10K_0402_5%
<28,5>
<28,5>
<5>
RB751V-40TE17_SOD323-2
1U_0402_6.3V6K
C209
@
2 8.2K_0402_5%
WLAN_CLKREQ#
R621 1
R673 1
R674 1
2 8.2K_0402_5%
2 2.2K_0402_5%
2 2.2K_0402_5%
LAN_CLKREQ#
APU_SCLK0
APU_SDATA0
R618 1
2 8.2K_0402_5%
VGA_CLKREQ#_R
R684 1
2 10K_0402_5%
HDA_BITCLK
R688 1
2 10K_0402_5%
HDA_SDIN0
R689 1
2 10K_0402_5%
VGA_CLKREQ#_R
PU +3VALW + PD
1U_0402_6.3V6K
C212
GEVENT2#
RTC_CLK
@
R903
2K_0402_5%
8
7
6
5
@
R927
2K_0402_5%
R926
2K_0402_5%
@
R950
2.2K_0402_5%
R929
2.2K_0402_5%
1K_0804_8P4R_5%
RP10 @
TEST0
CS_JTAG_TMS_TEST1
TEST2
1
2
3
4
8
7
6
5
15K_0804_8P4R_5%
2012/04/22
Issued Date
Compal Secret Data
2015/04/22
Deciphered Date
Title
FT3 GPIO/AZ/MISC
Rev
1.0
VAWGA/GB
Date:
LPC_FRAME#
LPC_CLK0_EC
LPC_CLK1
+3VALW
RP9 @
1
2
3
4
R622 1
+3VS
R949
10K_0402_5%
2
PWR_GOOD_APU
SYS_PWRGD_EC
@
R928
10K_0402_5%
R925
10K_0402_5%
<28>
@
R904
10K_0402_5%
R902
10K_0402_5%
RB751V-40TE17_SOD323-2
PU +3VS
PD
+3VALW
EC_RSMRST#_R
EC_RSMRST#
<28>
EC_LID_OUT#
USB_OC0#
USB_OC1#
D5
RTC_CLK
D3
2 100K_0402_5%
2 100K_0402_5%
2 100K_0402_5%
1.8V SPI ROM
GEVENT2_L
CLKGEN
ENABLE
(DEFAULT)
1
R121
10K_0804_8P4R_5%
APU_SCLK1
APU_SDATA1
APU_PCIE_WAKE#
2
PXS_PWREN
0_0402_5%
R656 1
R650 1
R651 1
8
7
6
5
LPC_CLK1
BOOT FAIL TIMER

ENABLED
RP14
1
2
3
4
+3VALW
+3VS
LPC_CLK0_EC
SPI ROM
(DEFAULT)
APU_GPIO174
2 10K_0402_5%
R686 1
R691 1
Sheet
E
of
48
RTC OF APU
CORE POWER OF APU
VDDBT_RTC_G
+RTCBATT
VDDCR_CPU
+RTCBATT_R
180P_0402_50V8J
W=20mils
R93
1
C166
0.22U_0402_10V6K
2 10K_0402_5%
C190
1U_0402_6.3V6K
C189
1U_0402_6.3V6K
1U_0402_6.3V6K
C188
C187
1U_0402_6.3V6K
C186
1U_0402_6.3V6K
1U_0402_6.3V6K
C184
C183
1U_0402_6.3V6K
1U_0402_6.3V6K
C182
C181
1U_0402_6.3V6K
1U_0402_6.3V6K
C180
C179
+APU_CORE
CLRP1 J@
SHORT PADS
Need OPEN
1
for Clear CMOS
INTEGRATED GPU POWER OF APU
+3VALW/+3VS OF APU
VDDCR_NB
+APU_CORE_NB
+3VALW
+3VS
@
+3VALW_APU
UAPUH
1U_0402_6.3V6K
2
UAPUF
C232
180P_0402_50V8J
1U_0402_6.3V6K
180P_0402_50V8J
1U_0402_6.3V6K
C233
1U_0402_6.3V6K
C240
C239
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C238
C237
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
C236
+0.95VALW
AL10
AL11
+1.5VS
B1
B2
+1.8VALW
AL13
AM13
AR5
AU4
AV7
AW5
C245
C248
AE11
AE13
AJ11
AJ13
+0.95VALW
2
180P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDD_095_USB3_DUAL
1U_0402_6.3V6K
180P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11
VDDIO_MEM_S_12
VDDIO_MEM_S_13
VDDIO_MEM_S_14
VDDIO_MEM_S_15
VDDIO_MEM_S_16
VDDIO_MEM_S_17
VDDIO_MEM_S_18
VDDIO_MEM_S_19
VDDIO_MEM_S_20
VDDIO_MEM_S_21
VDDIO_MEM_S_22
VDDIO_MEM_S_23
L13
VDDCR_NB_2 L17
VDDCR_NB_3 N11
VDDCR_NB_4 N13
VDDCR_NB_5 N17
VDDCR_NB_6 R11
VDDCR_NB_7 R13
VDDCR_NB_8 R17
VDDCR_NB_9 U13
VDDCR_NB_10 U17
VDDCR_NB_11 W13
VDDCR_NB_12 W17
VDDCR_NB_13 AA13
VDDCR_NB_14 AA17
VDDCR_NB_15 AC13
VDDCR_NB_16 AC17
VDDCR_NB_17 AE15
VDDCR_NB_18 AE17
VDDCR_NB_19 AE19
VDDCR_NB_20 AG17
VDDCR_NB_21 AG21
VDDIO_AZ_ALW_1
VDD_18_ALW_1
VDD_18_1
VDD_18_ALW_2
VDD_18_2
VDD_33_ALW_1
VDD_33_1
VDD_33_ALW_2
VDD_33_2
VDD_095_1
VDD_095_USB3_DUAL_2
VDD_095_USB3_DUAL_3
VDD_095_USB3_DUAL_4
VDD_095_ALW_1
VDD_095_ALW_2
VDD_095_ALW_3
VDD_095_ALW_4
VDD_095_GFX_2 W10
AN4
+APU_CORE_NB
+1.8VS
+3VS
+0.95VS
A8
A13
A23
A31
A35
A39
B8
B13
B23
B31
B39
C1
C2
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41
D9
D11
D13
E3
E4
E9
E11
E13
E27
E31
E35
E38
E39
G3
G7
G11
G13
G15
G17
G21
G25
G29
G35
G37
G39
G41
H11
H13
H23
H31
GND
VSS_1
VSS_63
VSS_2
VSS_64
VSS_3
VSS_65
VSS_4
VSS_66
VSS_5
VSS_67
VSS_6
VSS_68
VSS_7
VSS_69
VSS_8
VSS_70
VSS_9
VSS_71
VSS_10
VSS_72
VSS_11
VSS_73
VSS_12
VSS_74
VSS_13
VSS_75
VSS_14
VSS_76
VSS_15
VSS_77
VSS_16
VSS_78
VSS_17
VSS_79
VSS_18
VSS_80
VSS_19
VSS_81
VSS_20
VSS_82
VSS_21
VSS_83
VSS_22
VSS_84
VSS_23
VSS_85
VSS_24
VSS_86
VSS_25
VSS_87
VSS_26
VSS_88
VSS_27
VSS_89
VSS_28
VSS_90
VSS_29
VSS_91
VSS_30
VSS_92
VSS_31
VSS_93
VSS_32
VSS_94
VSS_33
VSS_95
VSS_34
VSS_96
VSS_35
VSS_97
VSS_36
VSS_98
VSS_37
VSS_99
VSS_38
VSS_100
VSS_39
VSS_101
VSS_40
VSS_102
VSS_41
VSS_103
VSS_42
VSS_104
VSS_43
VSS_105
VSS_44
VSS_106
VSS_45
VSS_107
VSS_46
VSS_108
VSS_47
VSS_109
VSS_48
VSS_110
VSS_49
VSS_111
VSS_50
VSS_112
VSS_51
VSS_113
VSS_52
VSS_114
VSS_53
VSS_115
VSS_54
VSS_116
VSS_55
VSS_117
VSS_56
VSS_118
VSS_57
VSS_119
VSS_58
VSS_120
VSS_59
VSS_121
VSS_60
VSS_122
VSS_61
VSS_123
VSS_62
VSS_124
J3
J7
J8
J39
K11
K13
K17
K19
K21
K23
K25
K27
K29
K31
L3
L7
L8
L10
L11
L15
L19
L31
L39
L41
M1
M2
N3
N7
N15
N19
N25
N29
N31
N39
P1
P2
R3
R7
R15
R19
R25
R29
R39
R41
U1
U2
U3
U7
U8
U11
U15
U19
U25
U29
U31
U39
W3
W5
W11
W15
W19
W25
W29
W39
W41
Y1
Y2
AA3
AA7
AA8
AA11
AA15
AA19
AA25
AA29
AA39
AC3
AC7
AC11
AC15
AC19
AC25
AC29
AC31
AC39
AC41
AE3
AE7
AE25
AE29
AE32
AE39
AG3
AG5
AG10
AG11
AG13
AG15
AG19
AG25
AG29
AG31
AG39
AG41
AH1
AH2
AJ3
AJ7
AJ15
AJ17
AJ19
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39
AL3
AL8
AL15
AL17
AL19
AL25
AL29
VSS_188
VSS_127
VSS_189
VSS_128
VSS_190
VSS_129
VSS_191
VSS_130
VSS_192
VSS_131
VSS_193
VSS_132
VSS_194
VSS_133
VSS_195
VSS_134
VSS_196
VSS_135
VSS_197
VSS_136
VSS_198
VSS_137
VSS_199
VSS_138
VSS_200
VSS_139
VSS_201
VSS_140
VSS_202
VSS_141
VSS_203
VSS_142
VSS_204
VSS_143
VSS_205
VSS_144
VSS_206
VSS_145
VSS_207
VSS_146
VSS_208
VSS_147
VSS_209
VSS_148
VSS_210
VSS_149
VSS_211
VSS_150
VSS_212
VSS_151
VSS_213
VSS_152
VSS_214
VSS_153
VSS_215
VSS_154
VSS_216
VSS_155
VSS_217
VSS_156
VSS_218
VSS_157
VSS_219
VSS_158
VSS_220
VSS_159
VSS_221
VSS_160
VSS_222
VSS_161
VSS_223
VSS_162
VSS_224
VSS_163
VSS_225
VSS_164
VSS_226
VSS_165
VSS_227
VSS_166
VSS_228
VSS_167
VSS_229
VSS_168
VSS_230
VSS_169
VSS_231
VSS_170
VSS_232
VSS_171
VSS_233
VSS_172
VSS_234
VSS_173
VSS_235
VSS_174
VSS_236
VSS_175
VSS_237
VSS_176
VSS_238
VSS_177
VSS_239
VSS_178
VSS_240
VSS_179
VSS_241
VSS_180
VSS_242
VSS_181
VSSBG_DAC
VSS_182
VBURN
VSS_183
PSEN
AL39
AL41
AM11
AM27
AM31
AN3
AN7
AN39
AP31
AR3
AR13
AR17
AR21
AR25
AR29
AR39
AR41
AU1
AU2
AU3
AU15
AU19
AU23
AU27
AU39
AV9
AW3
AW7
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW31
AW33
AW35
AW37
AW39
AW41
AY13
AY15
AY18
AY30
BA2
BA7
BA13
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
AL31
AM29
VSS_184
VSS_185
VSS_186
FT3 REV 0.51
FT3 REV 0.51
X4@
X4@
FT3_BGA769
FT3_BGA769
+0.95VS_APU_GFX
FT3_BGA769
Compal Secret Data
2012/04/22
2015/04/22
Deciphered Date
Title
Date:
VSS_187
VSS_126
FT3 REV 0.51
Issued Date
VSS_125
VDD_095_GFX_3 AA10
VDDBT_RTC_G
X4@
VDD_18_ALW
AM15
AM17
AG23
VDD_095_2 AG27
VDD_095_3 AJ21
VDD_095_4 AJ27
VDD_095_5 AL21
VDD_095_6 AL23
VDD_095_7 AL27
VDD_095_8 AM23
VDD_095_9 AM25
VDD_095_USB3_DUAL_1
VDD_095_ALW
A2
A3
B3
C3
VDD_095_GFX_1 U10
+RTCBATT_R
+APU_CORE
VDDIO_AZ_ALW_2
VDD_18_4
C246
C250
C244
C160
C222
VDDIO_MEM_S_5
VDD_18_3
+1.8VALW
C219
C217
C220
C218
C221
C214
VDDIO_MEM_S_4
+3VALW_APU
C216
C938
C937
VDDIO_MEM_S_3
VDD_18
+1.8VS
+0.95VALW
VDDIO_MEM_S_2
VDDCR_NB_1
+0.95VALW
VDDCR_CPU_2 L23
VDDCR_CPU_3 L25
VDDCR_CPU_4 L27
VDDCR_CPU_5 L29
VDDCR_CPU_6 N21
VDDCR_CPU_7 N23
VDDCR_CPU_8 N27
VDDCR_CPU_9 R21
VDDCR_CPU_10 R23
VDDCR_CPU_11 R27
VDDCR_CPU_12 U21
VDDCR_CPU_13 U23
VDDCR_CPU_14 U27
VDDCR_CPU_15 W21
VDDCR_CPU_16 W23
VDDCR_CPU_17 W27
VDDCR_CPU_18 AA21
VDDCR_CPU_19 AA23
VDDCR_CPU_20 AA27
VDDCR_CPU_21 AC21
VDDCR_CPU_22 AC23
VDDCR_CPU_23 AC27
VDDCR_CPU_24 AE21
VDDCR_CPU_25 AE23
VDDCR_CPU_26 AE27
+1.8VALW/+1.8VS OF APU
C933
C203
L22
2
1
FBMA-L11-201209-121LMA50T_0805
GND
VDDCR_CPU_1 L21
VDDIO_MEM_S_1
VDD_095_GFX
1U_0402_6.3V6K
1U_0402_6.3V6K
C255
C254
4.7U_0603_6.3V6K
C256
C161
UAPUG
POWER
J35
L32
L37
N35
R31
R37
U32
U35
W31
W32
W37
AA31
AA35
AC32
AC37
AE31
AE35
AG32
AG37
AJ35
AL32
AL37
AR35
+1.5V
+1.5VS
C936
180P_0402_50V8J
180P_0402_50V8J
C259
180P_0402_50V8J
C258
C231
180P_0402_50V8J
C230
180P_0402_50V8J
180P_0402_50V8J
@
C207
180P_0402_50V8J
1U_0402_6.3V6K
C213
C260
1U_0402_6.3V6K
C206
1U_0402_6.3V6K
1U_0402_6.3V6K
C204
1U_0402_6.3V6K
C205
1U_0402_6.3V6K
10U_0603_6.3V6M
C199
+0.95VS_APU_GFX
VDD_095
C198
10U_0603_6.3V6M
C934
C935
+0.95VALW/+0.95VS OF APU
+0.95VS
180P_0402_50V8J
180P_0402_50V8J
C208
C210
0.1U_0402_16V7K
C211
0.1U_0402_16V7K
C932
C930
0.1U_0402_16V7K
C931
0.1U_0402_16V7K
0.1U_0402_16V7K
C929
C928
0.1U_0402_16V7K
C927
0.1U_0402_16V7K
C926
0.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C923
C949
C925
C924
VDDIO_AZ_ALW
(Could be S0 or S5 power rail)
VDDIO_MEM_S
1
1
0_0603_5%
VDD_33_ALW
PLANE SPLIT
+1.5V
1U_0402_6.3V6K
C253
VDD_33
+1.5V/+1.5VS OF APU
C252
180P_0402_50V8J
C257
1U_0402_6.3V6K
C249
180P_0402_50V8J
1U_0402_6.3V6K
C197
C194
1U_0402_6.3V6K
1U_0402_6.3V6K
C193
C191
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C192
C202
1U_0402_6.3V6K
C201
C200
2
R582
FT3 PWR/GND
Rev
1.0
VAWGA/GB
Sheet
E
of
48
+1.5V
DDRAB_SDQ16
DDRAB_SDQ17
DDRAB_SDQS4#
DDRAB_SDQS4
DDRAB_SDQS4#
DDRAB_SDQS4
DDRAB_SDQ34
DDRAB_SDQ35
DDRAB_SDQ40
DDRAB_SDQ41
DDRAB_SDM5
DDRAB_SDQ42
DDRAB_SDQ43
DDRAB_SDQ48
DDRAB_SDQ49
<4,9>
<4,9>
DDRAB_SDQS6#
DDRAB_SDQS6
DDRAB_SDQS6#
DDRAB_SDQS6
DDRAB_SDQ50
DDRAB_SDQ51
DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDM7
DDRAB_SDQ58
DDRAB_SDQ59
R69
10K_0402_5%
1
2
+3VS
R70
+3VS
2
10K_0402_5%
C135
2.2U_0603_6.3V6K
C136
0.1U_0402_16V4Z
205
G1
G2
DDRAB_SMA6
DDRAB_SMA4
+1.5V
R65
20K_0402_1%
DDRAB_SMA2
DDRAB_SMA0
DDRA_ODT1
VREF for DIMM1,2

+1.5V
DDRA_SCS0#
DDRA_ODT0
DDRAB_SMA11
DDRAB_SMA7
DDRAB_SBS1#
DDRAB_SRAS#
4.7U_0603_6.3V6K
<4,9>
<4,9>
<4>
DDRA_CKE1
DDRAB_SMA15
DDRAB_SMA14
DDRA_CLK1
DDRA_CLK1#
0.1U_0402_16V4Z
DDRAB_SDQ32
DDRAB_SDQ33
C127
DDRAB_SMA13
DDRA_SCS1#
C126
DDRA_SCS1#
0.1U_0402_16V4Z
<4>
0.1U_0402_16V4Z
DDRAB_SWE#
DDRAB_SCAS#
DDRAB_SWE#
DDRAB_SCAS#
C123
<4,9>
<4,9>
DDRAB_SMA10
DDRAB_SBS0#
0.1U_0402_16V4Z
DDRAB_SBS0#
C122
<4,9>
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE1
0.1U_0402_16V4Z
DDRA_CLK0
DDRA_CLK0#
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
C121
<4>
<4>
0.1U_0402_16V4Z
DDRAB_SMA3
DDRAB_SMA1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDRAB_SDQ30
DDRAB_SDQ31
C120
DDRAB_SMA8
DDRAB_SMA5
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
<4,9>
<4,9>
DDRAB_SDQS3#
DDRAB_SDQS3
0.1U_0402_16V4Z
DDRAB_SMA12
DDRAB_SMA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDRAB_SDQS3#
DDRAB_SDQS3
C119
DDRAB_SBS2#
DDRAB_SDQ28
DDRAB_SDQ29
0.1U_0402_16V4Z
DDRAB_SBS2#
DDRA_CKE0
DDRAB_SDQ22
DDRAB_SDQ23
C118
DDRA_CKE0
<4,9>
+0.75VS
0.1U_0402_16V4Z
<4>
2
+1.5V
DDRAB_SDM2
C117
DDRAB_SDQ26
DDRAB_SDQ27
DDRAB_SDQ20
DDRAB_SDQ21
0.1U_0402_16V4Z
DDRAB_SDM3
+1.5V/+0.75VS OF DIMM1
0.1U_0402_16V4Z
DDRAB_SDQ24
DDRAB_SDQ25
<4,9>
MEM_MAB_RST#
DDRAB_SDQ14
DDRAB_SDQ15
C116
DDRAB_SDQ18
DDRAB_SDQ19
DDRAB_SDM1
MEM_MAB_RST#
C115
DDRAB_SDQS2#
DDRAB_SDQS2
DDRAB_SDQ12
DDRAB_SDQ13
C114
<4,9>
<4,9>
DDRAB_SDQS2#
DDRAB_SDQS2
<4,9>
DDRAB_SDQ6
DDRAB_SDQ7
DDRAB_SDQ10
DDRAB_SDQ11
<4,9>
DDRAB_SMA[0..15]
DDRA_CLK1
DDRA_CLK1#
<4>
<4>
DDRAB_SBS1#
DDRAB_SRAS#
<4,9>
<4,9>
DDRA_SCS0#
DDRA_ODT0
<4>
<4>
DDRA_ODT1
<4>
+VREF_DQ
R66
1K_0402_1%
+VREF_CA
DDRAB_SDQS1#
DDRAB_SDQS1
DDRAB_SMA[0..15]
<4,9>
DDRAB_SDQS1#
DDRAB_SDQS1
DDRAB_SDQS0#
DDRAB_SDQS0
DDRAB_SDQ[0..63]
DDRAB_SDM[0..7]
R67
20K_0402_1%
R68
1K_0402_1%
1
<4,9>
<4,9>
<4,9>
<4,9>
DDRAB_SDQ8
DDRAB_SDQ9
DDRAB_SDM[0..7]
DDRAB_SDQS0#
DDRAB_SDQS0
DDRAB_SDQ[0..63]
DDRAB_SDQ4
DDRAB_SDQ5
DDRAB_SDQ2
DDRAB_SDQ3
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
DDRAB_SDM0
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
15mil
+VREF_CA
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDM4
DDRAB_SDQ38
DDRAB_SDQ39
DDRAB_SDQ44
DDRAB_SDQ45
DDRAB_SDQS5#
DDRAB_SDQS5
C167
DDRAB_SDQ0
DDRAB_SDQ1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C134
C142
C176
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
0.1U_0402_16V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
+1.5V
15mil
1000P_0402_50V7K
+VREF_DQ
1
3
DDRAB_SDQS5#
DDRAB_SDQS5
<4,9>
<4,9>
DDRAB_SDQS7#
DDRAB_SDQS7
<4,9>
<4,9>
MEM_MAB_EVENT#
APU_SDATA0
APU_SCLK0
<4,9>
<26,6,9>
<26,6,9>
DDRAB_SDQ46
DDRAB_SDQ47
DDRAB_SDQ52
DDRAB_SDQ53
DDRAB_SDM6
DDRAB_SDQ54
DDRAB_SDQ55
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQS7#
DDRAB_SDQS7
DDRAB_SDQ62
DDRAB_SDQ63
MEM_MAB_EVENT#
+0.75VS
4
206
FOX_AS0A626-U8SN-7F
ME@
2012/04/22
Issued Date
Compal Secret Data
DIMM_A H:8mm
2015/04/22
Deciphered Date
Title
<Address: 00>
Date:
DDR3 SODIMM-I Socket

Rev
1.0
VAWGA/GB
Sheet
E
of
48
+VREF_DQ
+1.5V
DDRAB_SDQS1#
DDRAB_SDQS1
DDRAB_SDQS1#
DDRAB_SDQS1
DDRAB_SDQ10
DDRAB_SDQ11
DDRAB_SDQ16
DDRAB_SDQ17
DDRAB_SDQ40
DDRAB_SDQ41
DDRAB_SDM5
DDRAB_SDQ42
DDRAB_SDQ43
DDRAB_SDQ48
DDRAB_SDQ49
<4,8>
<4,8>
DDRAB_SDQS6#
DDRAB_SDQS6
DDRAB_SDQS6#
DDRAB_SDQS6
DDRAB_SDQ50
DDRAB_SDQ51
DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDM7
DDRAB_SDQ58
DDRAB_SDQ59
R71
10K_0402_5%
1
2
+3VS
1
R72
2
10K_0402_5%
205
G1
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
DDRAB_SDQ34
DDRAB_SDQ35
C158
DDRAB_SDQS4#
DDRAB_SDQS4
C175
DDRAB_SDQS4#
DDRAB_SDQS4
0.1U_0402_16V4Z
<4,8>
<4,8>
0.1U_0402_16V4Z
DDRAB_SDQ32
DDRAB_SDQ33
C172
DDRB_SCS1#
DDRAB_SMA13
DDRB_SCS1#
DDRB_CKE1
0.1U_0402_16V4Z
<4>
DDRAB_SWE#
DDRAB_SCAS#
DDRAB_SWE#
DDRAB_SCAS#
C171
<4,8>
<4,8>
DDRAB_SBS0#
DDRAB_SMA10
DDRAB_SBS0#
<4,8>
<4,8>
DDRAB_SDQS3#
DDRAB_SDQS3
DDRAB_SDQ30
DDRAB_SDQ31
0.1U_0402_16V4Z
<4,8>
DDRB_CLK0
DDRB_CLK0#
DDRAB_SDQS3#
DDRAB_SDQS3
C170
<4>
<4>
DDRB_CLK0
DDRB_CLK0#
DDRAB_SDQ28
DDRAB_SDQ29
0.1U_0402_16V4Z
DDRAB_SMA3
DDRAB_SMA1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDRAB_SDQ22
DDRAB_SDQ23
C169
DDRAB_SMA8
DDRAB_SMA5
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
+0.75VS
0.1U_0402_16V4Z
DDRAB_SMA12
DDRAB_SMA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
+1.5V
+1.5V
DDRAB_SDM2
C168
DDRAB_SBS2#
DDRAB_SDQ20
DDRAB_SDQ21
0.1U_0402_16V4Z
DDRAB_SBS2#
DDRB_CKE0
+1.5V/+0.75VS OF DIMM2
C165
DDRB_CKE0
<4,8>
MEM_MAB_RST#
DDRAB_SDQ14
DDRAB_SDQ15
0.1U_0402_16V4Z
<4>
<4,8>
DDRAB_SDM1
MEM_MAB_RST#
C162
DDRAB_SDQ26
DDRAB_SDQ27
<4,8>
0.1U_0402_16V4Z
DDRAB_SDM3
<4,8>
DDRAB_SMA[0..15]
DDRAB_SDQ12
DDRAB_SDQ13
0.1U_0402_16V4Z
DDRAB_SDQ24
DDRAB_SDQ25
DDRAB_SDM[0..7]
DDRAB_SDQ6
DDRAB_SDQ7
C132
DDRAB_SDQ18
DDRAB_SDQ19
DDRAB_SMA[0..15]
C155
DDRAB_SDQS2#
DDRAB_SDQS2
DDRAB_SDQS0#
DDRAB_SDQS0
C133
<4,8>
<4,8>
DDRAB_SDQS2#
DDRAB_SDQS2
<4,8>
<4,8>
1
C644
DDRAB_SDQ8
DDRAB_SDQ9
DDRAB_SDQ[0..63] <4,8>
DDRAB_SDM[0..7]
DDRAB_SDQS0#
DDRAB_SDQS0
+
2
220U_6.3V_M
DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ[0..63]
DDRAB_SDQ4
DDRAB_SDQ5
<4>
DDRB_CKE1
DDRAB_SMA15
DDRAB_SMA14
DDRAB_SMA11
DDRAB_SMA7
DDRAB_SMA6
DDRAB_SMA4
DDRAB_SMA2
DDRAB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRAB_SBS1#
DDRAB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1
DDRB_CLK1#
<4>
<4>
DDRAB_SBS1#
DDRAB_SRAS#
<4,8>
<4,8>
DDRB_SCS0#
DDRB_ODT0
<4>
<4>
DDRB_ODT1
<4>
15mil
+VREF_CA
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDM4
DDRAB_SDQ38
DDRAB_SDQ39
DDRAB_SDQ44
DDRAB_SDQ45
DDRAB_SDQS5#
DDRAB_SDQS5
C174
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C139
DDRAB_SDM0
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
0.1U_0402_16V4Z
DDRAB_SDQ0
DDRAB_SDQ1
C143
C177
+1.5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1000P_0402_50V7K
<4,8>
<4,8>
1000P_0402_50V7K
0.1U_0402_16V4Z
1
JDIMM2
15mil
1
3
DDRAB_SDQS5#
DDRAB_SDQS5
<4,8>
<4,8>
DDRAB_SDQS7#
DDRAB_SDQS7
<4,8>
<4,8>
MEM_MAB_EVENT#
APU_SDATA0
APU_SCLK0
<4,8>
<26,6,8>
<26,6,8>
DDRAB_SDQ46
DDRAB_SDQ47
DDRAB_SDQ52
DDRAB_SDQ53
DDRAB_SDM6
DDRAB_SDQ54
DDRAB_SDQ55
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQS7#
DDRAB_SDQS7
DDRAB_SDQ62
DDRAB_SDQ63
MEM_MAB_EVENT#
+0.75VS
4
206
G2
FOX_AS0A626-U4SN-7F
ME@
2012/04/22
Issued Date
Compal Secret Data
DIMM_B H:4mm
2015/04/22
Deciphered Date
Title
Custom
<Address: 10>
Date:
DDR3 SODIMM-II Socket

Rev
1.0
VAWGA/GB
Sheet
E
of
48
UV1A
LVDS Interface
PART 1 0F 9
UV1D
PCIE_ATX_C_GRX_P0
PCIE_ATX_C_GRX_N0
<5>
<5>
PCIE_ATX_C_GRX_P1
PCIE_ATX_C_GRX_N1
<5>
<5>
PCIE_ATX_C_GRX_P2
PCIE_ATX_C_GRX_N2
<5>
<5>
PCIE_ATX_C_GRX_P3
PCIE_ATX_C_GRX_N3
AA38
Y37
Y35
W36
W38
V37
V35
U36
U38
T37
T35
R36
R38
P37
P35
N36
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
PCIE_RX6P
PCIE_RX6N
PCIE_TX6P
PCIE_TX6N
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
Y33
Y32
PCIE_GTX_ARX_P0
PCIE_GTX_ARX_N0
CV1 PX@
CV2 PX@
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_ARX_P0 <5>
PCIE_GTX_C_ARX_N0 <5>
W33 PCIE_GTX_ARX_P1
W32 PCIE_GTX_ARX_N1
CV3 PX@
CV4 PX@
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
U33 PCIE_GTX_ARX_P2
U32 PCIE_GTX_ARX_N2
CV5 PX@
CV6 PX@
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
U30 PCIE_GTX_ARX_P3
U29 PCIE_GTX_ARX_N3
CV7 PX@
CV8 PX@
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PART 7 0F 9
RSVD/VARY_BL
RSVD/DIGON
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
T33
T32
TX5P_DPB0P
TX5M_DPB0N
T30
T29
NC#AF35
NC#AG36
P33
P32
TXCAP_DPA3P
TXCAM_DPA3N
P30
P29
TX0P_DPA2P
TX0M_DPA2N
M35
L36
L38
K37
K35
J36
J38
H37
H35
G36
G38
F37
F35
E37
NC
NC
NC
NC
PCI EXPRESS INTERFACE
N38
M37
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AK27
AJ27
LVDS CONTROL
LVTMDP
<5>
<5>
N33
N32
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
N30
N29
NC
NC
L33
L32
L30
L29
MARS@
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36
SUN NC
AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
AP37
MARS-XT M2_FCBGA962
K33
K32
J33
J32
UV1
SUN@
K30
K29
S IC 216-0841000-00 A0 SUN PRO M2 FCBGA 962P C38

H33
H32
SA00006BA20
+3VGS
CLOCK
AB35
AA36
PCIE_REFCLKP
PCIE_REFCLKN
CLK_PEG_VGA
CLK_PEG_VGA#
<6>
CALIBRATION
2 PX@
1
AH16
1K_0402_5%
GPU_RST#
AA30
TEST_PG
PCIE_CALR_RX
Y29 RV3
1 PX@
1 PX@
2 1.69K_0402_1%
2 1K_0402_1%
+0.95VGS
PXS_RST#
<24,26,6>
APU_PCIE_RST#
2
1
+0.95VGS
Y
A
GPU_RST#
PX@
UV2
MC74VHC1G08DFT2G SC70 5P
PERSTB
RV2
Y30 RV1
PCIE_CALR_TX
CLK_PEG_VGA
CLK_PEG_VGA#
<5>
<5>
MARS-XT M2_FCBGA962
PX@
MARS@
RV4
100K_0402_5%
2012/07/03
Issued Date
Compal Secret Data
2013/07/03
Deciphered Date
Title
ATI_MarsXTX_M2_PCIE/LVDS
Custom
Date:
Rev
1.0
VAWGA/GB
Sheet
E
10
of
48
AD29
AC29
AJ21
AK21
SWAPLOCKA
SWAPLOCKB
NC
NC
NC
NC
DPA
NC
NC
NC
NC
NC
NC
NC
NC
DPB
NC
NC
NC
NC
NC
NC
NC
NC
DPC
NC
NC
NC
NC
NC
NC
NC
NC
DPD
NC
NC
NC
NC
SCL
SDA
<28,35>
<39>
DV1
RB751V_SOD323 @
1
2
ACIN
GPU_VID5
<39>
AH20
AH18
AN16
GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
VGA_CLKREQ#
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB
GPU_VID3
GPU_VID4
AG32
AG33
GPU_GPIO0
GPU_GPIO0
GPU_GPIO5
GPU_VID5
GPU_VID1
GPU_VID1
THM_ALERT#
@ RV12 1
<39>
2 10K_0402_5%
GPU_VID2
GPU_VID2
VGA_CLKREQ#
<39>
<39>
GPU_VID3
GPU_VID4
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
R
AVSSN
G
AVSSN
B
AVSSN
DAC1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
NC
NC
NC
NC
NC
NC
NC
GPIO_29
GPIO_30
NC_SVI2
NC_SVI2
NC_SVI2
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
PS_0
AC30
+1.8VGS
+VREFG_GPU
1 499_0402_1%
+VREFG_GPU
AH13
PX_EN
AL21
T29
PS_1[5]
PCIE Transmitter De-emphasis Enable

0:Tx de-emphasis disabled
1:Tx de-emphasis enabled
1 100K_0402_5%
1 2.2K_0402_5%
BIF_GEN3_EN_A
PS_1[1]
PCIE Gen3 Enable

(NOTE:RESERVED for Thames/Seymour and should
be strapped to 0)
AV31
AU30
HPD1
MLPS
DBG_VREFG
PS_1
PS_2
AT33
AU32
VGA control
0:VGA controller capacity enabled
1:VGA controller capacity disabled (for multi-GPU)
BIF_VGA DIS
PS_2[4]
ROMIDCFG[2:0]
PS_0[3..1]
+3VGS
AU14
AV13
AT15
AR14
JTAG_TRSTB
JTAG_TDI
JTAG_TMS
RV7
RV8
RV9
2
2
2
@
@
@
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
JTAG_TCK
RV10 2
1 10K_0402_5%
AT17
AR16
AU20
AT19
BIOS_ROM_EN
PS_2[3]
AUD[1]
NA
AUD[0]
NA
001
256MB
Enable external BIOS ROM device

0:Disabled
1:Enabled
AT21
AR20
AU22
AV21
Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture size
If PS_2[3]=1, defines ROM type
100 - 512Kbit M25P05A
(ST)
101 - 1Mbit M25P10A
(ST)
101 - 2Mbit M25P20
(ST)
101 - 4Mbit M25P40
(ST)
101 - 8Mbit M25P80
(ST)
100 - 512Kbit Pm25LV010 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
AU16
AV15
00 - No audio function
01 - Audio for DP only
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
AT23
AR22
NC
HDMI must only be enabled on systems that are

legally entitled. It isthe responsibility of the system
designer to ensure that the system is entitled to
support this feature.
AD39
AD37
VGA_R
AE36
AD35
VGA_G
AF37
AE38
VGA_B
AC36
AC38
HSYNC
VSYNC
T24
CEC_DIS
AVDD
MarsCRB
120ohm
1
0.1u
1
1u
1
10u
1
T25
T26
T4
T6
+AVDD
AB34
RV11 1 PX@
AD34
AE34
+AVDD
(1.8V@70mA AVDD)
AC33
AC34
+VDD1DI
(1.8V@117mA VDD1DI)
2 499_0402_1%
V13
U13
AF33
AF32
AA29
AG21
AC32
LV1
2 0_0402_5%
AM34
PS_0
AD31
PS_1
PS_0[4]
RESERVED
PS_1[3]
Reserved
RESERVED
PS_1[2]
Reserved
RESERVED
NA
Reserved
RESERVED
NA
Reserved (for Thames/Whistler/Seymour only)
AUD_PORT_CONN_PINSTRAP[2]
PS_3[5]
PS_3[4]
PS_0[5]
0
1
NA
NA
STRAPS TO INDICATE THE NUMBER OF AUDIO

CAPABLE DISPLAY OUTPUTS
111 = 0 usable endpoints
000 = all endpoints are usable
+1.8VGS
1
Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE
RESERVED STRAPS BUT DO NOT INSTALL
RESISTOR
IF THESE GPIOS ARE USEED, THEY MUST KEEP
LOW AND NOT CONFLICT DURING RESET
LV2
Design
1
1
1
1
+1.8VGS
+VDD1DI
AC31
AD30
AD32
AG31
0:GEN3 not support at power-on

1:GEN3 supported at power-on
AR32
AT31
111
2 0_0402_5%
VDD1DI
120ohm
0.1u
1u
10u
MarsCRB
1
1
1
1
Design
1
1
1
1
MLPS Strap
Bits[5:4]
Bits[3:1]
PS_0[5:1]
11
001
Capacitor
NC
R_pu
8.45K
R_pd
2K
PS_1[5:1]
01
010
82 nF
4.53K
2K
PS_2[5:1]
00
000
680 nF
NC
4.75K
PS_3[5:1]
11
XXX
NC
PS_2
BACO
PX_EN
PS_3
AK32
AL31
+TSVDD
(1.8V@13mA TSVDD)
2 0_0402_5%
CV32
CV31
2
PX@
1U_0402_6.3V6K
CV30
10U_0603_6.3V6M
Design
1
1
1
1
+TSVDD
PX@
MarsCRB
1
1
1
1
PX@
0.1U_0402_16V4Z
+1.8VGS
AJ32
AJ33
NC
NC
GPIO_28_FDO
NC
NC
TS_A
DDCVGACLK
DDCVGADATA
TSVDD
TSVSS
MARS@
AN21
AM21
@
CV26
AK30
AK29
VGA_SMB_DA2
QV3A @
DMN66D0LDW-7_SOT363-6
4
AJ30
AJ31
EC_SMB_CK2
<28,29,4>
EC_SMB_DA2
<28,29,4>
1 PX@
CV27
2
PX@ 1 @
CV29
CV28
2
1
2
1
2
X76@ RV27
PX@RV28
PX@
RV28
4.75K_0402_1%
4.75K_0402_1%
PX@RV29
PX@
RV29
2K_0402_1%
PX@RV30
PX@
RV30
2K_0402_1%
Place CLOSE VGA CHIP
QV3B @
MARS-XT M2_FCBGA962
Compal Secret Data
Issued Date
2012/07/03
Deciphered Date
2013/07/03
Title
ATI_MarsXTX_M2_Main_MSIC
Size
C
Date:
1
1
VGA_SMB_CK2
DPLUS
DMINUS
+3VGS
@
RV25
10K_0402_5%
AF29
AG29
THERM_D+
THERM_D2 GPIO_28_FDO
10K_0402_5%
2
10K_0402_5%
@
RV24
10K_0402_5%
PS_0
PS_1
PS_2
PS_3
+3VGS
2 0_0402_5%
2 0_0402_5%
1
@
RV26
1 PX@
RV31
AL29
AM29
PX@RV23
PX@
RV23
8.45K_0402_1%
@
@
AL30
AM30
X76@ RV20
@ RV21
PX@RV22
PX@
RV22
8.45K_0402_1%
8.45K_0402_1%
4.53K_0402_1%
RV16 1
RV17 1
REMOTE1+
REMOTE1-
NC
NC
+3VGS
AN20
AM20
NC
NC
THERMAL
AM19
AL19
AUX2P
AUX2N
DDC2CLK
DDC2DATA
+1.8VGS
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
T27
T28
0.01U_0402_25V7K
AUX1P
AUX1N
AM23
AN23
AK23
AL24
AM24
AM27
AL27
0.082U_0402_16V7K
Enable
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
VGA_CLK
VGA_DAT
0.68U_0402_10V6K
DDC1CLK
DDC1DATA
TESTEN
AM26
AN26
0.01U_0402_25V7K
AD28
DDC/AUX
DEBUG
PS_3
Disable
AD33
2
TESTEN
5.11K_0402_5%
2
1K_0402_5%
T11
TSVDD
120ohm
0.1u
1u
10u
CEC_1
MLPS
LV3
TX_DEEMPH_EN
Default Setting
Mapping to VRAM type please refer to page 45

1
@
RV18
1 PX@
RV19
+3VGS
<29>
<29>
Transmitter Power Savings Enable

0:50% Tx output swing
1:Full Tx output swing
1 249_0402_1%
2
1 0.1U_0402_16V7K
CV23
PX@
GPIO_28_FDO
AK24
RV6
PX@
2 RV13
PX@
2 RV14
0.60 V level, Please

VREFG Divider ans
cap close to ASIC
RV5
THM_ALERT#
<6>
DESCRIPTION OF DEFAULT SETTINGS
PS_1[4]
I2C
<39>
GPU_GPIO5
1U_0402_6.3V6K
@
CV18
AK26
AJ26
SMBCLK
SMBus
SMBDATA
MLPS
TX_PWRS_ENB
AR30
AT29
10U_0603_6.3V6M
@
CV19
AJ23
AH23
STRAPS
+3VGS
AT27
AR26
0.1U_0402_16V7K
@
CV17
VGA_SMB_CK2
VGA_SMB_DA2
AU26
AV25
10U_0603_6.3V6M
@
CV22
NC
NC
DBG_CNTL0
NC
NC
NC
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23
STRAPS
AT25
AR24
1U_0402_6.3V6K
@
CV21
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
AU24
AV23
0.1U_0402_16V7K
@
CV20
GENLK_CLK
GENLK_VSYNC
MUTI GFX
GENLK_CLK
GENLK_VSYNC
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
PART 2 0F 9
T1
T2
CONFIGURATION STRAPS
UV1B
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
11
of
48
UV1C
PART 9 0F 9
+MPV18
@
LV4
(MPLL_PVDD:1.8V@130mA )
2
XTALIN
1
XTALOUT
+MPV18
H7
H8
+SPV18
AM10
XO_IN
+SPLL_VDDC AN9
AN10
AF30
AF31
(SPLL_VDDC:0.95V@100mA )
+3VS
1
AK10
CLKTESTA AL10
CLKTESTB
NC_XTAL_PVDD
NC_XTAL_PVSS
MARS-XT M2_FCBGA962
MARS@
@
CV41
0.1U_0402_16V7K
@
RV33
51.1_0402_1%
PX@
CV46
@
CV47
20K_0402_5%
PX@
QV6
2N7002H_SOT23-3
2
G
@
QV7
2N7002H_SOT23-3
PX@
CV52
0.1U_0402_16V4Z
+1.8VALW
PXS_PWREN#
+1.5VGS
UV4
AO4304L_SO8
VIN2
VIN2
VOUT2
VOUT2
+1.8VGS_LS
1
PX@
2200P_0402_50V7K
2
C28
1
PX@
2200P_0402_50V7K
2
C27
11
10
9
8
1
+0.95VGS
J95VG
J@
1
+0.95VGS_LS
15
2
PAD-OPEN 4x4m 2
@ C31
1@
CV50
0.1U_0402_16V4Z
@
RV39 @
470_0603_5%
C30
PX@
PX@
CV53
0.1U_0402_25V6
@ QV1
2N7002H_SOT23-3
S
2
G
PXS_PWREN#
PX@
QV157A
1
2012/07/03
Issued Date
Compal Secret Data
PX@
R276
100K_0402_5%
2013/07/03
Deciphered Date
Title
ATI_MarsXTX_M2_BACO POWER
Custom
Date:
2
PAD-OPEN 4x4m 2
@ C32
RV42 @
0_0402_5%
PX@ PXS_PWREN# 2
QV157B
PXS_PWREN
1 PX@
CV49
4.7U_0603_6.3V6K
B+
RV41
240K_0402_5%
2
1
PX@
CT2
12
TPS22966DPUR_SON14_2X3
PX@
R286
100K_0402_5%
ON2
14
13
+3VALW
CT1
GND
GPAD
PX@
6
7
+0.95VALW
VBIAS
VOUT1
VOUT1
1U_0402_6.3V6K
PXS_PWREN
ON1
360mil(9A)
1
2
3
VL
VIN1
VIN1
0.1U_0402_16V4Z
8
7
6
5
PXS_PWREN
0.1U_0402_16V4Z
+1.5V
1U_0402_6.3V6K
AO4430: Rdson: 5.5mohm @ VGS=10V
360mil(9A)
+1.8VGS
J18VG
J@
U1895V
1
2
1 C29
+1.5V TO +1.5VGS
VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
PX@
CV48
4.7U_0603_6.3V6K
@
RV34
51.1_0402_1%
+1.8VALW TO +1.8VGS
+0.95VALW TO +0.95VGS
Load switch
1
RV38 PX@
20K_0402_5%
RV37 PX@
@
RV36
470_0603_5%
2
G
@
CV42
0.1U_0402_16V7K
1U_0603_10V6K
1
+5VALW
PXS_PWREN
CV37 PX@
10P_0402_50V8J
4.7U_0603_6.3V6K
QV8
LP2301ALT1G_SOT23-3
PX@
PXS_PWREN
+3VGS
3
<28,39,6>
SPLL_PVSS
+3VS TO +3VGS
PX@
AW35
XO_IN2
NC
27MHZ 10PF +-20PPM X3G027000DA1H
AW34
2
@
LV6
0_0402_5%
SPLL_VDDC
XTALOUT
+SPLL_VDDC
1
SPLL_PVDD
0.1U_0402_16V7K
PX@
CV40
PX@CV36
PX@
CV36
10P_0402_50V8J
+0.95VGS
Design
1
1
1
1
OSC
OSC
XTALOUT
MPLL_PVDD
MPLL_PVDD
(SPLL_PVDD:1.8V@75mA )
1U_0402_6.3V6K
PX@
CV39
10U_0603_6.3V6M
PX@
CV38
2
@
LV5
0_0402_5%
0.1U_0402_16V7K
PX@
CV45
MarsCRB
1
1
1
1
1U_0402_6.3V6K
PX@
CV44
SPLL_VDDC
120ohm
0.1u
1u
10u
+SPV18
Design
1
1
1
1
10U_0603_6.3V6M
PX@
CV43
MarsCRB
1
1
1
1
AU34
NC
XTALIN
+1.8VGS
SPLL_PVDD
120ohm
0.1u
1u
10u
2 1M_0402_5%
PX@
YV1
RV32 1
XTALIN
AV33
0_0603_5%
PLLS/XTAL
1U_0402_6.3V6K
PX@
CV34
Design
1
1
1
1
10U_0603_6.3V6M
PX@
CV33
MarsCRB
1
1
1
1
0.1U_0402_16V7K
PX@
CV35
+1.8VGS
MPLL_PVDD
220ohm
0.1u
1u
10u
Rev
1.0
VAWGA/GB
Sheet
E
12
of
48
UV1G
PART 6 0F 9
GND
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MARS@
UV1F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
PART 8 0F 9
+1.8VGS
MarsCRB
1
1
1
+DP_VDDR
RV43 1
Design
1
1
1
AP20
AP21
AP22
AP23
AU18
AV19
(DP_VDDR:1.8V@237mA/link )
2 0_0402_5%
+DP_VDDR
AH34
AJ34
AF34
AG34
AM37
AL38
AM32
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
AW28
AW18
RV44 2
PX@ 1 150_0402_1%
AM39
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
AP13
AT13
AP14
AP15
NC
NC
DP_CALR
MARS@
MarsCRB
1
1
1
Design
1
1
1
AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32
MARS-XT M2_FCBGA962
AG22
VSS_MECH
VSS_MECH
VSS_MECH
A39
AW1
AW39
MECH#1
MECH#2
MECH#3
TV12
TV13
TV14
PAD
PAD
PAD
2012/07/03
Issued Date
Compal Secret Data
2013/07/03
Deciphered Date
Title
ATI_MarsXTX_M2_PWR_GND
Custom
MARS-XT M2_FCBGA962
Date:
DP_VDDC
0.1u
1u
10u
DP GND
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
CALIBRATION
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31
10U_0603_6.3V6M
PX@
CV56
DP_VDDR
0.1u
1u
10u
AN24
AP24
AP25
AP26
AU28
AV29
+0.95VGS
(DP_VDDC:0.95V@280mA/link )
DP_VDDC
1U_0402_6.3V6K
PX@
CV55
DP_VDDR
0.1U_0402_16V7K
PX@
CV54
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
0.1U_0402_16V7K
PX@
CV59
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1U_0402_6.3V6K
PX@
CV58
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10U_0603_6.3V6M
PX@
CV57
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
Rev
1.0
VAWGA/GB
Sheet
E
13
of
48
Design
0
0
3
1
+3VGS
Design
1
1
1
0
0.1U_0402_16V7K
PX@
CV91
2
@
LV8
0_0402_5%
1U_0402_6.3V6K
@
CV90
10U_0603_6.3V6M
PX@
CV89
Design
1
1
3
1
(VDD_CT:1.8V@13mA )
CORE
2
+VDDC_CT
+VDDR3
1
2
@
LV9
0_0402_5%
+VDDR3
( VDDR4:1.8V@300mA)
0_0603_5%
I/O
AF23
VDDR3
AF24 VDDR3
AG23
VDDR3
AG24
VDDR3
AD12
AF11
AF12
AF13
+VDDR4
@
LV10
1
(VDDR3:3.3V@25mA)
+VDDR4
DVP
VDDR4
VDDR4
VDDR4
VDDR4
VOLTAGE
SENESE
AF28 FB_VDDC
VCCSENSE_VGA
AG28
TV15
<39>
VSSSENSE_VGA
AH29
ISOLATED
CORE I/O
<39>
FB_VDDCI
FB_GND
MARS@
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
AF15
VDDR4
AG11
VDDR4
AG13 VDDR4
AG15
VDDR4
Route as differential pair
BIF_VDDC
BIF_VDDC
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
10U_0603_6.3V6M
PX@
CV65
0_0603_5%
+0.95VGS
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
+0.95VGS
N27
T27
+0.95VGS
(PCIE_VDDC:0.95V@2.5A_GEN3.0 )
PCIE_VDDR
0.1u
1u
10u
MarsCRB
0
2
1
Design
2
3
1
PCIE_VDDC
1u
10u
MarsCRB
7
2
Design
5
1
10U_0603_6.3V6M
PX@
CV85
LEVEL
TRANSLATION
VDD_CT
VDD_CT
VDD_CT
VDD_CT
BACO
1U_0402_6.3V6K
PX@
CV64
AF26
AF27
AG26
AG27
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
+1.8VGS
1U_0402_6.3V6K
@
CV84
1U_0402_6.3V6K
PX@
CV83
+0.95VGS
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
(BIF_VDDC:0.95V@1.4A)
10U_0603_6.3V6M
PX@
CV88
0.1U_0402_16V7K
PX@
CV63
1U_0402_6.3V6K
PX@
CV82
1U_0402_6.3V6K
PX@
CV81
AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37
1U_0402_6.3V6K
PX@
CV87
NC
NC
NC
NC
NC
NC
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD
0.01U_0402_25V7K
PX@
CV62
MEM I/O
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
1U_0402_6.3V6K
PX@
CV80
0.1U_0402_16V7K
PX@
CV79
0.1U_0402_16V7K
PX@
CV78
0.1U_0402_16V7K
PX@
CV77
0.1U_0402_16V7K
PX@
CV97
MarsCRB
1
1
1
1
+VDDC_CT
+1.8VGS
VDDR4
220ohm
0.1u
1u
10u
1U_0402_6.3V6K
PX@
CV95
MarsCRB
1
1
2
0
1U_0402_6.3V6K
PX@
CV94
VDDR3
120ohm
0.1u
1u
10u
1U_0402_6.3V6K
PX@
CV96
MarsCRB
1
1
1
1
Design
0
5
5
0
5
1
+1.8VGS
VDD_CT
120ohm
0.1u
1u
10u
0.1U_0402_16V7K
PX@
CV61
0.1U_0402_16V7K
PX@
CV76
1U_0402_6.3V6K
PX@
CV75
1U_0402_6.3V6K
PX@
CV74
1U_0402_6.3V6K
PX@
CV171
1U_0402_6.3V6K
PX@
CV73
1U_0402_6.3V6K
PX@
CV71
10U_0603_6.3V6M
PX@
CV70
10U_0603_6.3V6M
PX@
CV69
1U_0402_6.3V6K
@
CV93
MarsCRB
5
5
0
5
3
0
10U_0603_6.3V6M
PX@
CV92
VDDR1
0.01u
0.1u
1u
2.2u
10u
220u
10U_0603_6.3V6M
@
CV68
10U_0603_6.3V6M
@
CV67
+
2
10U_0603_6.3V6M
@
CV60
220U_B2_2.5VM_R35
CV66
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
LV7
2
+PCIE_VDDR
PART 5 0F 9
+1.5VGS
(PCIE_VDDR:1.8V@100mA ) +PCIE_VDDR
UV1E
For GDDR5, MVDDQ = 1.5V

(VDDR1:1.5V@3A,GDDR5:1125MHz )
1U_0402_6.3V6K
PX@
CV86
+1.5VGS
PCIE
+VGA_CORE
VGA_CORE Cap in power side sheet
AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
+VGA_CORE
3
(VDDCI:0.9~1.15V@8.8A)
MARS-XT M2_FCBGA962
Issued Date
Compal Secret Data
2012/07/03
Deciphered Date
2013/07/03
Title
ATI_MarsXTX_M2_Power
Size
C
Date:
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
14
of
48
UV1H
UV1I
PART 3 0F 9
+VDD_MEM15_REFDA
+VDD_MEM15_REFSA
PART 4 0F 9
GDDR5/DDR3
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7
DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B
1 PX@
RV47
2
120_0402_1%
C34
D29
D25
E20
E16
E12
J10
D7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
A34
E30
E26
C20
C16
C12
J11
F8
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
MDA[0..63]
MDA[0..63]
MAA[0..15]
A_BA[0..2]
DQMA[0..7]
QSA[0..7]
QSA#[0..7]
CLKA1
CLKA1B
J14 CLKA1
H14 CLKA1#
B_BA[0..2]
DQMB[0..7]
QSB[0..7]
QSB#[0..7]
K23 RASA0#
K19 RASA1#
K20 CASA0#
K17 CASA1#
ODTA0
ODTA1
<16>
<17>
CLKA0
CLKA0#
<16>
<16>
CLKA1
CLKA1#
<17>
<17>
RASA0#
RASA1#
<16>
<17>
CASA0#
CASA1#
<16>
<17>
K24 CSA0#_0
K27
CSA0#_0
<16>
CSA1B_0
CSA1B_1
M13 CSA1#_0
K16
CSA1#_0
CKEA0
CKEA1
K21 CKEA0
J20 CKEA1
WEA0B
WEA1B
K26 WEA0#
L15 WEA1#
<16,17>
A_BA[0..2]
<16,17>
DQMA[0..7]
<16,17>
QSA[0..7]
<16,17>
QSA#[0..7]
<16,17>
MDB[0..63]
MAB[0..15]
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
<16,17>
MAA[0..15]
MDB[0..63]
CSA0B_0
CSA0B_1
<18,19>
MAB[0..15]
<18,19>
B_BA[0..2]
<18,19>
DQMB[0..7]
<18,19>
QSB[0..7]
<18,19>
QSB#[0..7]
<18,19>
<17>
CKEA0
CKEA1
<16>
<17>
WEA0#
WEA1#
<16>
<17>
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
+VDD_MEM15_REFDB Y12
+VDD_MEM15_REFSB AA12
GDDR5/DDR3
DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7
DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
MVREFDB
MVREFSB
WEB0B
WEB1B
H23 MAA13
J19 MAA14
M21 MAA15
M20
MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD
M12
NC
AH12 NC
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
H27 CLKA0
G27 CLKA0#
CASA0B
CASA1B
M27 MEM_CALRP0
A32
C32
D23
E22
C14
A14
E10
D9
CLKA0
CLKA0B
RASA0B
RASA1B
L27 NC
N12
NC
AG12
NC
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
J21 ODTA0
G19 ODTA1
ADBIA0/ODTA0
ADBIA1/ODTA1
L18
MVREFDA
L20 MVREFSA
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
MEMORY INTERFACE B
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
MEMORY INTERFACE A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD
DRAM_RST
MARS-XT M2_FCBGA962
MARS@
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
H3
H1
T3
T5
AE4
AF5
AK6
AK5
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
T7
W7
ODTB0
ODTB1
L9
L8
CLKB0
CLKB0#
AD8 CLKB1
AD7 CLKB1#
T10 RASB0#
Y10 RASB1#
W10 CASB0#
AA10 CASB1#
ODTB0
ODTB1
<18>
<19>
CLKB0
CLKB0#
<18>
<18>
CLKB1
CLKB1#
<19>
<19>
RASB0#
RASB1#
<18>
<19>
CASB0#
CASB1#
<18>
<19>
P10 CSB0#_0
L10
CSB0#_0
<18>
AD10 CSB1#_0
AC10
CSB1#_0
<19>
CKEB0
CKEB1
<18>
<19>
WEB0#
WEB1#
<18>
<19>
U10 CKEB0
AA11 CKEB1
N10 WEB0#
AB11 WEB1#
T8
MAB13
W8 MAB14
U12 MAB15
V12
AH11 DRAM_RST#_R
MARS-XT M2_FCBGA962
MARS@
2
10_0402_5%
DRAM_RST#_R
+VDD_MEM15_REFSB
RV58
100_0402_1%
PX@
RV57
4.99K_0402_1%
PX@
CV100
120P_0402_50V9
PX@
CV99
1U_0402_6.3V6K
2 PX@
RV56
100_0402_1%
PX@
CV98
1U_0402_6.3V6K
2 PX@
1
+VDD_MEM15_REFDB
1
1 PX@
RV54
CV101
1U_0402_6.3V6K
2 PX@
RV59
100_0402_1%
PX@
CV102
1U_0402_6.3V6K
2 PX@
2
51.1_0402_1%
1 PX@
RV53
RV52
40.2_0402_1%
PX@
1
2
DRAM_RST#
+1.5VGS
1
2
<16,17,18,19>
RV51
40.2_0402_1%
PX@
+VDD_MEM15_REFSA
+VDD_MEM15_REFDA
RV55
100_0402_1%
PX@
+1.5VGS
RV48
4.7K_0402_5%
@
RV50
40.2_0402_1%
PX@
2
RV49
40.2_0402_1%
PX@
+1.5VGS
1
+1.5VGS
+1.5VGS
Ball to RV57 < 1"

CV100 to RV57 < 200 mil
CV100 to RV53 < 1"
DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2
Issued Date
Compal Secret Data
2012/07/03
Deciphered Date
2013/07/03
Title
ATI_MarsXTX_M2_MEM IF
Size
C
Date:
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
15
of
48
UV6
UV5
M8
H1
+VREFC_A1
M8
H1
+VREFC_A0
<15>
MDA[0..31]
<15,17>
MAA[15..0]
<15>
DQMA[3..0]
<15>
QSA[3..0]
<15>
QSA#[3..0]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
MDA[0..31]
<15,17>
<15,17>
<15,17>
<15>
<15>
<15>
<15>
<15>
<15>
CKEA0
DQMA2
DQMA0
E7
D3
QSA#2
QSA#0
G3
B7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT/ODT0
CS/CS0
RAS
CAS
WE
F3
C7
QSA2
QSA0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
<15,17,18,19>
DQSL
DQSU
T2
DRAM_RST#
RESET
L8
MDA23
MDA19
MDA22
MDA18
MDA21
MDA17
MDA20
MDA16
D7
C3
C8
C2
A7
A2
B8
A3
MDA0
MDA5
MDA1
MDA6
MDA3
MDA4
MDA2
MDA7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
B2
D9
G7
K2
K8
N1
N9
R1
R9
A_BA0
A_BA1
A_BA2
M2
N8
M3
CLKA0
CLKA0#
CKEA0
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
K1
L2
J3
K3
L3
QSA3
QSA1
F3
C7
DQMA3
DQMA1
E7
D3
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
QSA#3
QSA#1
G3
B7
DRAM_RST# T2
L8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
RV85
240_0402_1%
MARS@
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA24
MDA30
MDA27
MDA29
MDA25
MDA28
MDA26
MDA31
D7
C3
C8
C2
A7
A2
B8
A3
MDA12
MDA10
MDA14
MDA11
MDA13
MDA9
MDA15
MDA8
+1.5VGS
BA0
BA1
BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
X76@
96-BALL
SDRAM DDR3
X76@
CLKA0 1 MARS@ 2
RV60
40.2_0402_1%
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
1
MARS@
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
RV84
240_0402_1%
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
+1.5VGS
ZQ/ZQ0
J1
L1
J9
L9
VREFCA
VREFDQ
+1.5VGS
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
J7
K7
K9
CLKA0
CLKA0#
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
A_BA0
A_BA1
A_BA2
<15>
<15>
VREFCA
VREFDQ
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VGS
CV195
0.01U_0402_25V7K
MARS@
+1.5VGS
MARS@
RV63
4.99K_0402_1%
+VREFC_A1
1
1
2
CV103
0.1U_0402_16V7K
MARS@
RV65
4.99K_0402_1%
MARS@
CV104
0.1U_0402_16V7K
+VREFC_A0
MARS@
RV64
4.99K_0402_1%
15mil
15mil
MARS@
RV62
4.99K_0402_1%
MARS@
CLKA0# 1 MARS@ 2
RV61
40.2_0402_1%
+1.5VGS
+1.5VGS
CV125
@
0.1U_0402_16V7K
CV153
@
0.1U_0402_16V7K
CV164
@
0.1U_0402_16V7K
CV122
@
0.1U_0402_16V7K
CV152
MARS@
1U_0402_6.3V6K
CV120
MARS@
1U_0402_6.3V6K
CV119
MARS@
1U_0402_6.3V6K
CV118
MARS@
1U_0402_6.3V6K
CV117
MARS@
1U_0402_6.3V6K
CV116
MARS@
10U_0603_6.3V6M
CV151
@
10U_0603_6.3V6M
CV114
@
0.1U_0402_16V7K
CV113
@
0.1U_0402_16V7K
CV112
@
0.1U_0402_16V7K
CV111
@
0.1U_0402_16V7K
CV110
MARS@
1U_0402_6.3V6K
CV109
MARS@
1U_0402_6.3V6K
CV108
MARS@
1U_0402_6.3V6K
CV107
MARS@
1U_0402_6.3V6K
CV106
MARS@
1U_0402_6.3V6K
CV105
MARS@
10U_0603_6.3V6M
+1.5VGS
Compal Secret Data
Issued Date
2010/08/25
Deciphered Date
2012/08/25
Title
Size
C
Date:

ATI_Whistler_M2_VRAM_A
Document Number
Rev
1.0
VAWGA/GB
Sheet
1
16
of
48
UV7
UV8
M8
H1
+VREFC_A2
<15>
MDA[32..63]
<15,16>
MAA[15..0]
<15>
DQMA[7..4]
<15>
QSA[7..4]
<15>
QSA#[7..4]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
MDA[32..63]
<15,16>
<15,16>
<15,16>
<15>
<15>
<15>
CLKA1
CLKA1#
CKEA1
<15>
<15>
<15>
<15>
<15>
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
M2
N8
M3
A_BA0
A_BA1
A_BA2
A_BA0
A_BA1
A_BA2
J7
K7
K9
K1
L2
J3
K3
L3
QSA4
QSA5
F3
C7
DQMA4
DQMA5
E7
D3
QSA#4
QSA#5
G3
B7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA38
MDA36
MDA39
MDA34
MDA35
MDA33
MDA37
MDA32
D7
C3
C8
C2
A7
A2
B8
A3
MDA42
MDA44
MDA40
MDA46
MDA43
MDA45
MDA41
MDA47
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
+1.5VGS
BA0
BA1
BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M8
H1
+VREFC_A3
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A_BA0
A_BA1
A_BA2
M2
N8
M3
CLKA1
CLKA1#
CKEA1
J7
K7
K9
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
K1
L2
J3
K3
L3
QSA6
QSA7
F3
C7
DQMA6
DQMA7
E7
D3
QSA#6
QSA#7
G3
B7
L8
J1
L1
J9
L9
MARS@
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
RV87
240_0402_1%
MARS@
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DRAM_RST# T2
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RV86
240_0402_1%
RESET
DRAM_RST#
DQSL
DQSU
96-BALL
SDRAM DDR3
X76@
E3
F7
F2
F8
H3
H8
G2
H7
MDA49
MDA51
MDA48
MDA52
MDA50
MDA53
MDA55
MDA54
D7
C3
C8
C2
A7
A2
B8
A3
MDA60
MDA57
MDA63
MDA56
MDA61
MDA59
MDA62
MDA58
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
<15,16,18,19>
DRAM_RST# T2
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
DML
DMU
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
C
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
X76@
+1.5VGS
B
+VREFC_A3
1
MARS@
CV127
0.1U_0402_16V7K
MARS@
RV71
4.99K_0402_1%
MARS@
RV70
4.99K_0402_1%
+VREFC_A2
1
15mil
15mil
CV126
0.1U_0402_16V7K
CV196
0.01U_0402_25V7K
MARS@
MARS@
RV68
4.99K_0402_1%
CLKA1# 1 MARS@ 2
RV69
40.2_0402_1%
MARS@
RV67
4.99K_0402_1%
CLKA1 1 MARS@ 2
RV66
40.2_0402_1%
+1.5VGS
MARS@
+1.5VGS
+1.5VGS
CV148
@
0.1U_0402_16V7K
CV147
@
0.1U_0402_16V7K
CV146
@
0.1U_0402_16V7K
CV145
@
0.1U_0402_16V7K
CV144
MARS@
1U_0402_6.3V6K
CV143
MARS@
1U_0402_6.3V6K
CV142
MARS@
1U_0402_6.3V6K
CV141
MARS@
1U_0402_6.3V6K
CV140
MARS@
1U_0402_6.3V6K
CV139
MARS@
10U_0603_6.3V6M
CV138
@
10U_0603_6.3V6M
CV137
@
0.1U_0402_16V7K
CV136
@
0.1U_0402_16V7K
CV135
@
0.1U_0402_16V7K
CV134
@
0.1U_0402_16V7K
CV133
MARS@
1U_0402_6.3V6K
CV132
MARS@
1U_0402_6.3V6K
CV131
MARS@
1U_0402_6.3V6K
CV130
MARS@
1U_0402_6.3V6K
CV129
MARS@
1U_0402_6.3V6K
CV128
MARS@
10U_0603_6.3V6M
+1.5VGS
Compal Secret Data
Issued Date
2010/08/25
Deciphered Date
2012/08/25
Title
Size
C
Date:

Document Number
Rev
1.0
VAWGA/GB
Sheet
1
17
of
48
UV9
<15>
MDB[0..31]
<15,19>
MAB[15..0]
<15>
DQMB[3..0]
<15>
QSB[3..0]
<15>
QSB#[3..0]
MDB[0..31]
<15,19>
<15,19>
<15,19>
<15>
<15>
M2
N8
M3
B_BA0
B_BA1
B_BA2
J7
K7
K9
CLKB0
CLKB0#
<15>
<15>
<15>
<15>
<15>
<15>
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CKEB0
K1
L2
J3
K3
L3
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
QSB2
QSB0
F3
C7
DQMB2
DQMB0
E7
D3
QSB#2
QSB#0
G3
B7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
PX@ 2
40.2_0402_1%
<15,16,17,19>
T2
DRAM_RST#
L8
1
CV197
0.01U_0402_25V7K
PX@
J1
L1
J9
L9
RV88
240_0402_1%
PX@
D7
C3
C8
C2
A7
A2
B8
A3
MDB0
MDB4
MDB1
MDB6
MDB3
MDB7
MDB2
MDB5
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
M2
N8
M3
CLKB0
CLKB0#
CKEB0
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
K1
L2
J3
K3
L3
QSB3
QSB1
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMB3
DQMB1
E7
D3
QSB#3
QSB#1
G3
B7
DRAM_RST# T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
B_BA0
B_BA1
B_BA2
+1.5VGS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M8
H1
+VREFC_B1
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CLKB0# 1
RV73
PX@ 2
40.2_0402_1%
MDB19
MDB20
MDB22
MDB16
MDB23
MDB17
MDB21
MDB18
+1.5VGS
BA0
BA1
BA2
CLKB0 1
RV72
E3
F7
F2
F8
H3
H8
G2
H7
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
UV10
VREFCA
VREFDQ
RV89
240_0402_1%
PX@
J1
L1
J9
L9
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
96-BALL
SDRAM DDR3
X76@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB26
MDB30
MDB24
MDB29
MDB27
MDB28
MDB25
MDB31
D7
C3
C8
C2
A7
A2
B8
A3
MDB15
MDB10
MDB14
MDB11
MDB12
MDB9
MDB13
MDB8
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
+1.5VGS
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
M8
H1
+VREFC_B0
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
X76@
+1.5VGS
1
+1.5VGS
1
PX@
RV75
4.99K_0402_1%
15mil
PX@
RV74
4.99K_0402_1%
15mil
PX@
PX@
RV77
4.99K_0402_1%
1
2
1
2
CV150
0.1U_0402_16V7K
CV149
0.1U_0402_16V7K
PX@
RV76
4.99K_0402_1%
+VREFC_B1
+VREFC_B0
PX@
+1.5VGS
+1.5VGS
CV72
@
0.1U_0402_16V7K
CV170
@
0.1U_0402_16V7K
CV169
@
0.1U_0402_16V7K
CV168
@
0.1U_0402_16V7K
CV167
PX@
1U_0402_6.3V6K
CV166
PX@
1U_0402_6.3V6K
CV165
PX@
1U_0402_6.3V6K
CV123
PX@
1U_0402_6.3V6K
CV163
PX@
1U_0402_6.3V6K
CV162
PX@
10U_0603_6.3V6M
CV161
@
10U_0603_6.3V6M
CV160
@
0.1U_0402_16V7K
CV159
@
0.1U_0402_16V7K
CV158
@
0.1U_0402_16V7K
CV157
@
0.1U_0402_16V7K
CV156
PX@
1U_0402_6.3V6K
CV155
PX@
1U_0402_6.3V6K
CV191
PX@
1U_0402_6.3V6K
CV124
PX@
1U_0402_6.3V6K
CV121
PX@
1U_0402_6.3V6K
CV115
PX@
10U_0603_6.3V6M
+1.5VGS
Compal Secret Data
Issued Date
2010/08/25
Deciphered Date
2012/08/25
Title
Size
C
Date:

ATI_Whistler_M2_VRAM_B
Document Number
Rev
1.0
VAWGA/GB
Sheet
1
18
of
48
UV11
MDB[32..63]
<15,18>
MAB[15..0]
<15>
DQMB[7..4]
<15>
QSB[7..4]
<15>
QSB#[7..4]
MDB[32..63]
<15,18>
<15,18>
<15,18>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
M2
N8
M3
B_BA0
B_BA1
B_BA2
B_BA0
B_BA1
B_BA2
J7
K7
K9
CLKB1
CLKB1#
CKEB1
K1
L2
J3
K3
L3
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
<15,16,17,18>
QSB4
QSB5
F3
C7
DQMB4
DQMB5
E7
D3
QSB#4
QSB#5
G3
B7
DRAM_RST# T2
DRAM_RST#
L8
J1
L1
J9
L9
RV90
240_0402_1%
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDB33
MDB37
MDB35
MDB39
MDB32
MDB36
MDB34
MDB38
D7
C3
C8
C2
A7
A2
B8
A3
MDB44
MDB41
MDB47
MDB43
MDB45
MDB40
MDB46
MDB42
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
M2
N8
M3
CLKB1
CLKB1#
CKEB1
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
K1
L2
J3
K3
L3
QSB6
QSB7
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMB6
DQMB7
E7
D3
QSB#6
QSB#7
G3
B7
DRAM_RST# T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
B_BA0
B_BA1
B_BA2
+1.5VGS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
M8
H1
+VREFC_B3
+1.5VGS
BA0
BA1
BA2
PX@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<15>
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
UV12
VREFCA
VREFDQ
J1
L1
J9
L9
RV91
240_0402_1%
PX@
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
96-BALL
SDRAM DDR3
X76@
E3
F7
F2
F8
H3
H8
G2
H7
MDB55
MDB50
MDB54
MDB51
MDB53
MDB49
MDB52
MDB48
D7
C3
C8
C2
A7
A2
B8
A3
MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60
+1.5VGS
BA0
BA1
BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
M8
H1
+VREFC_B2
96-BALL
SDRAM DDR3
X76@
+1.5VGS
2
2
PX@
PX@
RV82
4.99K_0402_1%
1
2
PX@
RV83
4.99K_0402_1%
+VREFC_B3
+VREFC_B2
CV173
0.1U_0402_16V7K
CV198
0.01U_0402_25V7K
PX@
15mil
15mil
CV172
0.1U_0402_16V7K
PX@
RV80
4.99K_0402_1%
PX@ 2
40.2_0402_1%
PX@
RV78
4.99K_0402_1%
PX@ 2
40.2_0402_1%
CLKB1# 1
RV81
CLKB1 1
RV79
+1.5VGS
PX@
+1.5VGS
+1.5VGS
+1.5VGS
CV194
@
0.1U_0402_16V7K
CV193
@
0.1U_0402_16V7K
CV192
@
0.1U_0402_16V7K
CV154
@
0.1U_0402_16V7K
CV190
PX@
1U_0402_6.3V6K
CV189
PX@
1U_0402_6.3V6K
CV188
PX@
1U_0402_6.3V6K
CV187
PX@
1U_0402_6.3V6K
CV186
PX@
1U_0402_6.3V6K
CV185
PX@
10U_0603_6.3V6M
CV184
@
10U_0603_6.3V6M
CV183
@
0.1U_0402_16V7K
CV182
@
0.1U_0402_16V7K
CV181
@
0.1U_0402_16V7K
CV180
@
0.1U_0402_16V7K
CV179
PX@
1U_0402_6.3V6K
CV178
PX@
1U_0402_6.3V6K
CV177
PX@
1U_0402_6.3V6K
CV176
PX@
1U_0402_6.3V6K
CV175
PX@
1U_0402_6.3V6K
CV174
PX@
10U_0603_6.3V6M
Compal Secret Data
Issued Date
2010/08/25
Deciphered Date
2012/08/25
Title
Size
C
Date:

Document Number
Rev
1.0
VAWGA/GB
Sheet
1
19
of
48
+5V_Display
U73
+3VS
+5VS
OUT
1
C543
GND
<4>
<4>
DP2_TXP1
DP2_TXN1
<4>
<4>
DP2_TXP2
DP2_TXN2
<4>
<4>
DP2_TXP3
DP2_TXN3
HDMI_TX2P
HDMI_TX2N
DP2_TXP1
DP2_TXN1
C53 HDMI@ 1
C54 HDMI@ 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX1P
HDMI_TX1N
DP2_TXP2
DP2_TXN2
C55 HDMI@ 1
C56 HDMI@ 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX0P
HDMI_TX0N
DP2_TXP3
DP2_TXN3
C57 HDMI@ 1
C5888 HDMI@ 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_CLKP
HDMI_CLKN
HDMI_CLKP
WCM-2012HS-900T
3
4
3
HDMI_CLKN
HDMI_TX0P
HDMI_TX0N
1
L30
HDMI_TX1N
2
3
HDMI_CLK-_CONN
HDMI_TX0-_CONN
2
3
2
EMIP@
JHDMI1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_DET_R
+5V_Display
HDMIDAT_R
HDMICLK_R
Close to HDMI connector
HDMI_CLK-_CONN
D1 ESDU@
HDMI_TX2+_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN
HDMI_TX2-_CONN
HDMI_TX1+_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX1-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN
HDMI_TX2-_CONN
1
4
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
C
SUYIN_100042GR019M23DZL
ME@
TVWDF1004AD0_DFN9
D2 ESDU@
L39
1
R1471 HDMI@
2.2K_0402_5%
HDMI_TX2+_CONN
HDMI_TX0+_CONN
1
L31
HDMI@ R1470
2.2K_0402_5%
WCM-2012HS-900T
3
4
3
EMIP@
HDMI_TX1P
2
EMIP@
HDMI_CLK+_CONN
@
R894
200K_0402_5%
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI@
R898
100K_0402_5%
C51 HDMI@ 1
C52 HDMI@ 1
HDMI_DET
DP2_TXP0
DP2_TXN0
1
2
150K_0402_5%
1
DP2_TXP0
DP2_TXN0
0.1U_0402_16V7K 2
AP2330W-7_SC59-3
1
3
2
B
E
<4>
<4>
HDMI@
R434
HDMI@ C
Q87
MMBT3904_NL_SOT23-3
<4>
IN
C544
0.1U_0402_16V7K 2
W=40mils
HDMI_TX0+_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX0-_CONN
HDMI_CLK+_CONN
HDMI_CLK+_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_CLK-_CONN
HDMI_CLK-_CONN
R432 1 HDMI@ 2 499_0402_1%
HDMI_CLK+_CONN
R433 1 HDMI@ 2 499_0402_1%
HDMI_TX1-_CONN
R435 1 HDMI@ 2 499_0402_1%
HDMI_TX1+_CONN
R436 1 HDMI@ 2 499_0402_1%
HDMI_TX0-_CONN
R439 1 HDMI@ 2 499_0402_1%
HDMI_TX0+_CONN
R440 1 HDMI@ 2 499_0402_1%
HDMI_TX2-_CONN
R441 1 HDMI@ 2 499_0402_1%
HDMI_TX2+_CONN
R442 1 HDMI@ 2 499_0402_1%
HDMI_CLK-_CONN
WCM-2012HS-900T
HDMI_TX2N
2
3
2
3
1
4
HDMI_TX2+_CONN
TVWDF1004AD0_DFN9
HDMI_TX2-_CONN
HDMICLK_R
WCM-2012HS-900T
HDMIDAT_R
3
+3VS
HDMI CLK DATA Pull high

in Page 22 for 8P4R
HDMI_CLK
HDMI_CLK
<22,4>
HDMI_DATA
HDMI_DATA
HDMICLK_R
2
G
Q76
2N7002K_SOT23-3
HDMI@
<22,4>
+3VS
Q75A
HDMI@
1
D69
L30ESDL5V0C3-2_SOT23-3
ESDU@
HDMI_TX2P
L40
EMIP@
HDMIDAT_R
Q75B
HDMI@
Issued Date
Compal Secret Data
2012/04/22
Deciphered Date
2015/04/22
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
Date:
HDMI CONN
Document Number
Rev
1.0
VAWGA/GB
Sheet
1
20
of
48
LCD POWER CIRCUIT

CMOS Camera
+3VS
@
W=60mils
2
R694
+LCDVDD_CONN
W=60mils
1
0_0402_5%
U72
VOUT
+LCDVDD_CONN
GND
(40 MIL)
10U
1
R1458 CMOS@
150K_0402_5%
<28>
CMOS@
C1152
0.1U_0402_16V4Z
R02
@
C1153
10U_0603_6.3V6M
CMOS_ON#
1
APU_ENVDD
2
<4>
APL3512ABI-TRG_SOT23-5
(40 MIL)
+3VS_CMOS
EN
CMOS@
Q70
PMV65XP_SOT23-3
S
SS
1
C16
1500P_0402_50V7K
VIN
4.7U_0603_6.3V6K
C522
+3VS
C1155 CMOS@
0.1U_0402_16V4Z
R652
100K_0402_5%
VGA LCD/PANEL BD. Conn.

+LEDVDD
B+
C1158
680P_0402_50V7K
EMIU@
1
R813
2
0_0805_5%
C1159
4.7U_0805_25V6-K
JLVDS1
Add for protect BKOFF# damage
Use APU control for WIN8

<4>
R1463 1
APU_INVT_PWM
R1466 1
BKOFF#
INVT_PWM
<4>
<4>
LVDS_ACLK
LVDS_ACLK#
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
+3VS
1
BKOFF#
R826
100K_0402_5%
1
BKOFF#
R899
10K_0402_5%
LVDS_A2
LVDS_A2#
LVDS_A1
LVDS_A1#
LVDS_A0
LVDS_A0#
EDID_DATA
EDID_CLK
1
680P_0402_50V7K
C1160 EMIU@
<5>
<5>
USB20_P3
USB20_N3
2 0_0402_5%
2 0_0402_5%
<28>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
(60 MIL)
+3VS
2
0_0402_5%
2
1 R696
@
2
1 R695
@
0_0402_5%
USB20_P3
USB20_N3
+LCDVDD_CONN
+3VS_CMOS
USB20_P3_R
USB20_N3_R
CMOS
USB20_P3_R
USB20_N3_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
G1
G2
G3
G4
ACES_88341-3001 ME@
L58 EMIU@
USB20_P3
USB20_N3
USB20_P3_R
USB20_N3_R
A
WCM-2012-900T_4P
2012/04/22
Issued Date
Compal Secret Data
2015/04/22
Deciphered Date
Title
Size
B
Date:
LVDS CONN / Camera

Document Number
Rev
1.0
VAWGA/GB
Sheet
1
21
of
48
C1094
6P_0402_50V8
C1103
6P_0402_50V8
C1104
6P_0402_50V8
BLUE
C1107
6P_0402_50V8
DAC_BLU
DAC_GRN
DAC_RED
1
2
3
4
RP22
8
7
6
5
GREEN
DAC_BLU
RED
DAC_BLU
<4>
DAC_GRN
DAC_GRN
<4>
FCM1608CF-121T03 0603
2
EMIP@ 1
L36
FCM1608CF-121T03 0603
2
EMIP@ 1
L37
FCM1608CF-121T03 0603
2
EMIP@ 1
L38
DAC_RED
DAC_RED
<4>
C1105
6P_0402_50V8
C1106
6P_0402_50V8
150_0804_8P4R_1%
+3VS
2
RP1
<20,4>
<20,4>
1
2
3
4
HDMI_CLK
HDMI_DATA
CRT_DDC_DAT_CONN
CRT_DDC_CLK_CONN
HDMI_CLK
HDMI_DATA
+5V_Display
8
7
6
5
4.7K_8P4R_5%
1
+5VS
ESDP@
C600
1000P_0402_50V7K
+5V_Display
1
U10
+3VS
VCC_SYNC
7
1
C537
0.1U_0402_16V7K
<4>
CRT_DDC_DATA
<4>
CRT_DDC_CLK
<4>
CRT_VSYNC
<4>
CRT_HSYNC
10
11
13
15
6
BYP
VCC_VIDEO
VIDEO1
VCC_DDC
VIDEO2
DDC_IN1
VIDEO3
DDC_IN2
DDC_OUT1
SYNC_IN1
DDC_OUT2
SYNC_IN2
SYNC_OUT1
GND
SYNC_OUT2
1
C23
2
0.22U_0402_10V6K
JCRT1
RED
GREEN
CRT_DDC_DAT_CONN
GREEN
BLUE
JVGA_HS
BLUE
CRT_DDC_DAT_CONN
JVGA_VS
12
CRT_DDC_CLK_CONN
CRT_DDC_CLK_CONN
14
JVGA_VS_U R106 1 EMIP@ 2 22_0402_5%
16
JVGA_HS_U R107 1 EMIP@ 2 22_0402_5%
T58
R106 R107 for EMI
+3VS
R693 1
2 4.7K_0402_5%
CRT_DDC_DATA
R697 1
2 4.7K_0402_5%
CRT_DDC_CLK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
T49
RED
@
C411
TPD7S019-15DBQR_SSOP16
2012/04/22
Deciphered Date

2015/04/22
Title
Date:
16
17
JVGA_HS
1
B
A
G
G
CONTE_80431-5K1-152
ME@
Compal Secret Data
Issued Date
JVGA_VS
10P_0402_50V8J
C412
10P_0402_50V8J
C529
0.1U_0402_16V7K
CRT CONN
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
22
of
48
SATA HDD Conn.

JHDD1
<5>
<5>
<5>
<5>
0.01U_0402_25V7K 2
0.01U_0402_25V7K 2
SATA_ATX_DRX_P0
SATA_ATX_DRX_N0
SATA_DTX_C_ARX_N0 C596 1
SATA_DTX_C_ARX_P0 C597 1
SATA_DTX_C_ARX_N0
SATA_DTX_C_ARX_P0
1 C137
1 C138
1
2
3
4
5
6
7
SATA_ATX_C_DRX_P0
SATA_ATX_C_DRX_N0
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_ARX_N0
SATA_DTX_ARX_P0
GND
RX+
RXGND
TXTX+
GND
+3VS
1
R551
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
+3V_HDD
0_0805_5%
@
+5VS
1
R550
2
0_0805_5%
+5V_HDD
@
+5V_HDD
R02
1
EMIP@
2
10U
1
C598
1000P_0402_50V7K
1
C599
0.1U_0402_16V4Z
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
GND
GND
23
24
SUYIN_127043FB022G278ZR
C602
10U_0603_6.3V6M
FOR 15"
SATA ODD FFC Conn.

JODD2
CAP in Small Board

<5>
<5>
<5>
<5>
SATA_ATX_DRX_P1
SATA_ATX_DRX_N1
SATA_DTX_C_ARX_N1
SATA_DTX_C_ARX_P1
1
2
3
4
5
6
7
8
9
10
SATA_ATX_DRX_P1
SATA_ATX_DRX_N1
SATA_DTX_C_ARX_N1
SATA_DTX_C_ARX_P1
1
2
R710 ZODD@ 0_0402_5%
<28>
ODD_DETECT#
+5V_ODD
ODD_DA#
ODD_DA#
R02
1
2
3
4
5
6
7
8
9
10
GND
GND
11
12
HB_A051020-SAHR21
ME@
Co-lay
ODD Power Control
J@ J6
1
+5VALW
+5VS
FOR 14"
JODD1
JUMP_43X79
+5V_ODD
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_ATX_C_DRX_P1_14
SATA_ATX_C_DRX_N1_14
SATA_DTX_C_ARX_N114@ C614 1
SATA_DTX_C_ARX_P114@ C613 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_ARX_N1_14
SATA_DTX_ARX_P1_14
1
2
3
4
5
6
7
14@ C619 1
14@ C616 1
SATA_ATX_DRX_P1
SATA_ATX_DRX_N1
Q90
3
ZODD@
LP2301ALT1G_SOT23-3
2
R930
10K_0402_5%
R1110
ZODD@
ODD_EN
IN
<6>
GND
OUT
200K_0402_5%
ZODD@
2
2
C641
10U_0603_6.3V6M
ODD_DA#
R02
0.1U_0402_16V4Z
ZODD@
+3VS
DP
+5V
+5V
MD
GND
GND
1
R555 2
10K_0402_5%
GND
GND
15
14
ALLTO_C18518-11305-L
ME@
ZODD@
ZODD@
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
ODD_DETECT#
+5V_ODD
C642
2
SATA ODD Conn.
Need OPEN
Q91
DTC124EKAT146_SC59-3
Issued Date
Compal Secret Data
2012/04/22
2015/04/22
Deciphered Date
Title
Size
B
HDD/ODD/FAN/SCREW
Document Number
Date:
Rev
1.0
VAWGA/GB
G
Sheet
23
H
of
48
+3V_LAN
+3VALW
+LX
Close together
J10
J@
LL2
1
2
<10,6>
APU_PCIE_RST#
CL6
CL5
UL1
8172@
+3V_LAN
2 4.7K_0402_5%
1
AR8172-AL3A-R
LAN_PERST#
CL10
2
0_0402_5%
UL1
<28>
2
3
LAN_WAKE#
25
26
28
27
7
8
LAN_XTALO
LAN_XTALI
TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3
RX_P
REFCLK_N
REFCLK_P
PERST#
Near
Pin13
Near
Pin19
Near
Pin6
0.1U_0402_16V7K
CL20
CL19
CL18
0.1U_0402_16V7K
0.1U_0402_16V7K
CL17
0.1U_0402_16V7K
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL
13
19
31
34
6
41
Place close to Pin16

12
11
15
14
18
17
21
20
MDI0MDI0+
MDI1MDI1+
SMCLK
SMDATA
RBIAS
10
LAN_RBIAS
<25>
<25>
<25>
<25>
MDI0MDI0+
MDI1MDI1+
Place Close to PIN1
NC
TESTMODE
VDD33
LX
XTLO
XTLI
CLKREQ#
DVDDL/PPS
DVDDL_REG/DVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG/AVDDL
1
RL8
+3V_LAN
2
2.37K_0402_1%
Place Close to PIN1
+3V_LAN
40
+LX
+1.7_VDDCT
24
37
+LX_R
16
22
9
+3V_LAN
+2.7_AVDDH
+2.7_AVDDH
+LX
RL10
1
30K_0402_5%
2
+3V_LAN
10U
+2.7_AVDDH
AVDDH/AVDD33
AVDDH
AVDDH_REG
CL22
LAN_CLKREQ#
1U_0402_6.3V4Z
CL21
<6>
3
W AKE#
VDDCT/ISOLAN
4
RL12 if use LDO modue
CL16
10U_0603_6.3V6M
LAN_PERST#
AR8151/AR8161
RX_N
RL12
10K_0402_5%
2 LDO@ 1
mount
CL15
10U_0603_6.3V6M
32
33
TX_P
38
39
23
CL14
1U_0402_6.3V4Z
CLK_PCIE_LAN#
CLK_PCIE_LAN
LED_0
LED_1
LED_2
Atheros
CL13
0.1U_0402_16V7K
PCIE_ATX_C_DRX_P1
35
TX_N
CL12
1000P_0402_50V7K
1
2
<5>
<5>
<5>
30
36
PCIE_ATX_C_DRX_N1
GND
AR8162-AL3A-R_QFN40_5X5
8162@
Near
Pin9
Near
Pin31
Near
Pin22
1U_0402_6.3V4Z
PCIE_DTX_ARX_P1
29
CL25
2 0.1U_0402_16V7K
PCIE_DTX_ARX_N1
0.1U_0402_16V7K
CL26
2 0.1U_0402_16V7K
CL24
CL11 1
PCIE_DTX_C_ARX_P1
<5>
0.1U_0402_16V7K
<5>
CL9
PCIE_DTX_C_ARX_N1
1U_0402_6.3V4Z
<5>
0.1U_0402_16V7K
CL23
Place Close to Chip
Place close to Pin34
Close to
Pin40
RB751V-40TE17_SOD323-2
R577
SWR@SWR@SWR@
D4
1U_0402_6.3V4Z
RL4
10U
@
CL7
0.1U_0402_16V7K
LAN Chip Vendor recommand reserve the

PU resistor close LAN chip
AMD recommand reserve Diode
+3V_LAN
Note: Place Close to LAN chip

LL1 DCR< 0.15 ohm
Rate current > 1A
SWR@
4.7U_0603_6.3V6K
10K_0402_5%
CL8
LAN_PWR_ON#
LAN_PWR_ON#
0.1U_0402_16V7K
<28>
QL1
PMV65XP_SOT23-3~D
RL3
1U_0402_6.3V4Z
@
1
LL3
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
1
2
1
2
+1.1_AVDDL
+LX_R
+1.1_AVDDL_L
CL4
JUMP_43X79
LL1 SWR@
1
2 +LX
4.7UH_SIA4012-4R7M_20%
+LX_R
0.1U_0402_16V7K
10U_0603_6.3V6M
CL3
CL2
0.1U_0402_16V7K
CL1
1000P_0402_50V7K
Layout Notice : Place as close

chip as possible.
Near
Pin37
LAN_XTALI
LAN_XTALO
YL1
4
1
CL28
15P_0402_50V8J
NC
OSC
OSC
NC
3
2
1 25MHZ_20PF_FSX3M-25.M20FDO 1
CL29
15P_0402_50V8J
2
Issued Date
Compal Secret Data
2012/04/22
2015/04/22
Deciphered Date
Title
LAN-AR8151
Custom
Date:
Rev
1.0
VAWGA/GB
Sheet
E
24
of
48
Place Close to TL1
ESDU@
DL1
AZC099-04S.R7G_SOT23-6
1
4
I/O1
I/O3
MDI1+
DL1
1'S PN:SC300001G00
2'S PN:SC300002E00
GND
VDD
I/O2
I/O4
Reserve gas tube for EMI go rural solution

MDI0+
5
1
MDI0-
MDI1RL14
1
CL30
1
2
CHASSIS1_GND
75_0805_5%
EMIP@
10P_0603_50V
EMIP@
TL1
<24>
<24>
MDI0+
MDI0-
<24>
CL31
<24>
0.01U_0402_25V7K
MDI1+
MDI1-
1
EMIP@
2
1
2
3
4
5
6
7
8
MDI0+
MDI0-
MDI1+
MDI1-
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
DLL1
BS4200N-C-LV_SMB-F2
EMIGASP@
MDO0+
MDO0MCT
Place Close to TL1
MCT
MDO1+
MDO1-
MHPC_NS681612A
EMIP@
2 0.1U_0603_50V7K
CL63 1
CL61 1
2 0.1U_0603_50V7K
EMIP@
CHASSIS1_GND
JLAN1
MDO0+
MDO0-
MDO1+
MCT
MCT
MDO1-
MCT
MCT
PR1+
PR1PR2+
PR3+
PR33
PR2PR4+
GND
GND
9
10
PR4SANTA_130456-121
ME@
ESDP@ C173
0.1U_0402_16V7K
CHASSIS1_GND
C178 ESDP@
0.1U_0402_16V7K
Issued Date
Compal Secret Data
2012/04/22
Deciphered Date
2015/04/22
Title
B
Date:
LAN_Transformer
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
25
of
48
+3VS
1 TS@
@
2 100K_0402_5%
1
C1331
0.1U_0402_16V4Z
@
+3VS_TS
EC_TS_ON#
JTS1
0_0402_5%
<28>
R5583
R5581 1
+3VS_TS
Q156
PMV65XP_SOT23-3~D
@
2
<5>
<5>
USB20_N1
USB20_P1
EC_TS_ON#
R726 1
TS@ 2 0_0402_5% TS_RST#
8
7
6
5
4
3
2
1
0.1U_0402_16V4Z
C1322
GND
GND
6
5
4
3
2
1
ACES_50208-00601-P01
ME@
TS@
+1.5VS
+3VS_WLAN
Mini-Express Card(WLAN/WiMAX)
JWLN1
<6>
R1500 1
APU_PCIE_WAKE#
<6>
2 0_0402_5%
BT_DISABLE#
<6>
WLAN_CLKREQ#
<5>
<5>
APU_PCIE_WLAN_WAKE#
WLAN_CLKREQ#
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
<5>
<5>
PCIE_DTX_C_ARX_N2
PCIE_DTX_C_ARX_P2
<5>
<5>
PCIE_ATX_C_DRX_N2
PCIE_ATX_C_DRX_P2
+3VS_WLAN
<28>
<28>
EC_TX
EC_RX
EC_TX
EC_RX
1
1
100_0402_1%
R1498
2
2
R1499
100_0402_1%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
<6>
<10,6>
WL_OFF#
APU_PCIE_RST#
APU_PCIE_RST#
+3VS
+3VS_WLAN
+3VS_WLAN
J7
APU_SCLK0_W R1496 1
APU_SDATA0_W R1497 1
2 @ 0_0402_5%
2 @ 0_0402_5%
APU_SCLK0
APU_SDATA0
USB20_N5
USB20_P5
<6,8,9>
<6,8,9>
J@
2
JUMP_43X79
<5>
<5>
USB20_N5
USB20_P5
54
BELLW_80003-8041
ME@
<6>
BT_OFF#
R1520
2 BT_OFF#_R
1K_0402_5%
For EC to detect
debug card insert.
R1501
100K_0402_5%
Compal Secret Data
Issued Date
2012/04/22
Deciphered Date
2015/04/22
Title
MINI1 CARD (WLAN) / MINI2 CARD (Option)
B
Date:
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
26
of
48
Right Ext.USB Conn.
USB20_N6
1 R567@ 2 U2DN0_L
0_0402_5%
<5>
USB20_P6
1 R569@ 2U2DP0_L
0_0402_5%
<5>
USB30_N8
1 R574
2
0_0402_5%
<5>
USB30_P8
1 R575
2
0_0402_5%
<5>
+5VALW
+USB_VCCB
R02
U36
1
2
3
4
C713 0.1U_0402_16V4Z
2
1
<28>
USB_ON#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
RIGHT USB PORT X1
8
7
6
5
8
7
W=80mils
+USB_VCCB
EMIUSB2RU@
1
1 0_0402_5%
R900 2
1
USB20_N0
+ <5>
1 0_0402_5%
R896 2
<5>
USB20_P0
C715
EMIUSB2RU@
470P_0402_50V7K
2
2
EMIUSB2RP@
USB2R@
WCM-2012-900T_4P
L66
2 USB20_N0_C
USB20_N0 1
1
2
6
5
4
3
2
1
USB20_N0_C
USB20_P0_C
6.3 * 5.9
SF000001500
EMIP@
3
2
U2DN0
U2DP0
WCM-2012-900T_4P
1 R562
2
0_0402_5%
EMIU@
JUSB3 ME@
USB2R@
C714
USB2R@
220U_6.3V_M
L51
4
4
G547I2P81U_MSOP8
USB2R@
+USB_VCCB
EMIU@
1 R566
2
0_0402_5%
Colay with USB2.0 only
<6>
USB_OC0#
WCM-2012HS-900T
GND
GND
<5>
USB30_MRX_DTX_N0
6
5
4
3
2
1
<5>
USB30_MRX_DTX_P0
EMIP@
+USB3_VCCA
2
U3RXDN0
U3RXDP0
W=80mils
L50
U3TXDN0
U2DP0
U2DN0
U3RXDP0
ACES_88058-060N
<5> USB30_MTX_C_DRX_N0
C858
0.1U_0402_16V7K
1
2
U3TXDN0_L
WCM-2012HS-900T
1
U3RXDN0
2
U3TXDN0
U3TXDP0
USB20_P0_C
<5> USB30_MTX_C_DRX_P0
1
D25 ESDU@
PJDLC05_SOT23-3
U3TXDP0_L
C859
0.1U_0402_16V7K
1 R570@ 2 U2DN1_L
0_0402_5%
<5>
USB20_P7
1 R571@ 2U2DP1_L
0_0402_5%
2A/Active Low
+USB3_VCCA
U3RXDN0 9 10
C704
0.1U_0402_16V4Z
1
2
R02
U35
USB_ON#
1
2
3
4
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
W=80mils
8
7
6
5
<6>
USB_OC1#
ESDU@ D27
1
U3RXDN0
U3RXDP0 8
U3RXDP0
U3TXDN0 7
U3TXDN0
U3TXDP0 6
U3TXDP0
<5>
USB30_N9
1 R572
2
0_0402_5%
<5>
USB30_P9
1 R573
2
0_0402_5%
U2DP1
Colay with USB2.0 only
I/O4
GND
VDD
+5VALW
U3RXDN1 9 10
U3RXDP1 8
1
+USB3_VCCA
I/O1
I/O3
U2DN0
U2DN1
U2DP1
WCM-2012HS-900T
<5>
USB30_MRX_DTX_N1
<5>
USB30_MRX_DTX_P1
4
EMIP@
L54
+USB3_VCCA
2
U3RXDN1
U3RXDP1
W=80mils
U3RXDN1
U3RXDP1
U3TXDN1 7
U3TXDP1 6
7
6
ESDU@
I/O2
I/O4
GND
VDD
I/O1
I/O3
U2DN1
U3RXDP1
U3TXDN1
U3TXDP1
<5> USB30_MTX_C_DRX_N1
<5> USB30_MTX_C_DRX_P1
C856
0.1U_0402_16V7K
1
2 U3TXDN1_L
WCM-2012HS-900T
U3TXDP1_L
C857
0.1U_0402_16V7K
1
4
L53
U3RXDN1
2
U3TXDN1
U3TXDP1
LP2 Port1
JUSB2
U3TXDP1
U3TXDN1
U2DP1
ESDU@ D30
1
U2DN1
D22
YSCLAMP0524P_SLP2510P8-10-9
2
EMIP@
ESDU@
I/O2
WCM-2012-900T_4P
1 R721
2
0_0402_5%
EMIU@
G547I2P81U_MSOP8
D34
EMIU@
1 R728
2
0_0402_5%
L55
+5VALW
10
11
12
13
GND
GND
GND
GND
L49 EMIP@
USB20_N7
<5>
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
TAITW_PUBAU1-09FNLSCNN4H0
ME@
USB20_P0
LP1 Port0
JUSB1
9
1
8
3
7
2
6
4
5
U3TXDP0
9
1
8
3
7
2
6
4
5
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
GND
GND
GND
GND
10
11
12
13
TAITW_PUBAU1-09FNLSCNN4H0
ME@
3
EMIP@
1
+
C736
220U_6.3V_M
SF000002Y00 2
2
1 C735
YSCLAMP0524P_SLP2510P8-10-9
+5VALW
U2DP0
Issued Date
Compal Secret Data
470P_0402_50V7K
2
2012/04/22
Deciphered Date
2015/04/22
Title
USB2.0 / USB3.0 / BT
B
Date:
Document Number
Rev
1.0
VAWGA/GB
Sheet
1
27
of
48
EC_SCI#
BATT_LEN#
KSO[0..17]
KSI[0..7]
KSO[0..17]
<30>
KSI[0..7]
<30>
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
<34,35>
<34,35>
<11,29,4>
<11,29,4>
Pull high in APU side
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
12
13
37
20
38
77
78
79
80
<6>
<6>
<6>
<21>
<39>
Pull high in ODD side<23>
<33>
<29>
<24>
<26>
<26>
<6>
<30>
R836 1
RTC_CLK
PXS_PWREN
SLP_S3#
SLP_S5#
EC_SMI#
CMOS_ON#
EC_VGA_EN
ODD_DA#
ADP_ID_CLOSE
EC_TACH
LAN_WAKE#
EC_TX
EC_RX
SYS_PWRGD_EC
NOVO#
EC_VGA_EN
ODD_DA#
ADP_ID_CLOSE
EC_TACH
LAN_WAKE#
EC_TX
EC_RX
SYS_PWRGD_EC
NOVO#
2 0_0402_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
XCLKO
PXS_PWREN
+3V_EC
+EC_VCCA
R1266
USB_ON# 1
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
1
2
C1271
20P_0402_50V8
@
R1587
100K_0402_5%
KB9012QF-A3_LQFP128_14X14
Part Number = SA00004OB30
V
V
V
typ
V
V
V
VAD_BID
0 V
0.289
0.538
0.875
max
MP
PVT
DVT
EVT
V
V
V
+5VS
67
1
@
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
PWM Output
BATT_TEMP/AD0/GPIO38
AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
IMON/AD5/GPIO43
AD
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
GPIO
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
21
23
26
27
63
64
65
66
75
76
68
70
71
72
ADP_65
BEEP#
EC_FAN_PWM
ACOFF
BATT_TEMP
GPU_IMON
ADP_I
ADP_ID
BRDID
ENBKL
ADP_90
83
84
85
86
87
88
EC_MUTE#
USB_ON#
ADP_135
97
98
99
109
EC_TS_ON#
TP_CLK
TP_DATA
095VS_PWR_EN
NTC_V
119
120
126
128
EC_SPI_AISO
EC_SPI_AOSI
EC_SPI_CLK
EC_SPI_CS1#
73
74
89
90
91
92
93
95
121
127
APU_IMON
VGATE
LAN_PWR_ON#
BATT_CHG_LED#
CAPS_LED#
PWR_LED#
BATT_LOW_LED#
SYSON
VR_ON
095_18ALW_PWR_EN
100
101
102
103
104
105
106
107
108
EC_RSMRST#
EC_LID_OUT#
Turbo_V
110
112
114
115
116
117
118
ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
124
ADP_65
BEEP#
EC_FAN_PWM
ACOFF
<34>
<31>
<29>
<35>
MP
BATT_TEMP
GPU_IMON
ADP_I
ADP_ID
<34>
<39>
<34,35>
<33>
ENBKL
<4>
ADP_90
<34>
R1562
100K_0402_5%
TP_CLK
R1568 1
2 4.7K_0402_5%
TP_DATA
R1570 1
2 4.7K_0402_5%
+3VS
BRDID
R1564
0_0402_5%
EC_FAN_PWM
R1561 1
EC_TACH
R1581 1
EC_SMB_DA2
R1579 1
2 2.2K_0402_5%
EC_SMB_CK2
R1578 1
2 2.2K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
+3V_EC
BKOFF#
PBTN_OUT#
2 2.2K_0402_5%
R1574 1
2 2.2K_0402_5%
TP_CLK
TP_DATA
<30>
<30>
EC_TS_ON#
<26>
EC_MUTE#
R1565 1
095VS_PWR_EN
NTC_V
<32>
<34>
LAN_WAKE#
R1566 1
2 10K_0402_5%
EC_SPI_AISO
EC_SPI_AOSI
EC_SPI_CLK
EC_SPI_CS1#
<5>
<5>
<5>
<5>
LID_SW#
R344 1
2 47K_0402_5%
APU_IMON
VGATE
LAN_PWR_ON#
BATT_CHG_LED#
CAPS_LED#
PWR_LED#
BATT_LOW_LED#
SYSON
VR_ON
095_18ALW_PWR_EN
<40>
<40>
<24>
<30>
<30>
<30>
<30>
<32,37>
<40>
<37,38>
EC_RSMRST#
EC_LID_OUT#
<6>
<6>
BKOFF#
PBTN_OUT#
<21>
<6>
ACIN
EC_ON
ON/OFF
<11,35>
<36>
<30>
+V18R
+3VALW
@
2 10K_0402_5%
For share ROM need

1
2
100K_0402_5%
095_18ALW_PWR_EN 1
R1575
2
100K_0402_5%
2
100K_0402_5%
SYS_PWRGD_EC
R208
+3VLP
@
EC_RSMRST#
R1576
R343
47K_0402_5%
1
BATT_TEMP
2
100P_0402_50V8J
2
100P_0402_50V8J
C1265
<34>
<34>
<36>
Turbo_V
PROCHOT
MAINPWON
ACIN
C1266
1
ACIN
R1573
095VS_PWR_EN
R207
ENBKL
<30>
LID_SW#
ESDP@
R1577 1
EC_SMB_CK1
<31>
<27>
<34>
SUSP#
EC_SMB_DA1
EC_MUTE#
USB_ON#
ADP_135
R206
<32,37>
2
4.7K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
C601
1000P_0402_50V7K
H_PROCHOT#
C823
4.7U_0603_6.3V6K
PROCHOT
20mil
2
G
Q82
2N7002H_SOT23-3
<34,4,40,6>
C1269
47P_0402_50V8J
ECAGND
2012/04/22
Issued Date
Compal Secret Data
Deciphered Date
2015/04/22
Title
EC ENE KB930/9012
Custom
Rev
1.0
VAWGA/GB
Date:
+3VALW
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
EC_MUTE#/GPIO4A
KSI4/GPIO34
USB_EN#/GPIO4B
KSI5/GPIO35
CAP_INT#/GPIO4C
PS2
Interface
KSI6/GPIO36
EAPD/GPIO4D
KSI7/GPIO37
TP_CLK/GPIO4E
KSO0/GPIO20
TP_DATA/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
CPU1.5V_S3_GATE/GPXIOA00
KSO4/GPIO24
WOL_EN/GPXIOA01
KSO5/GPIO25 Int. K/B
ME_EN/GPXIOA02
KSO6/GPIO26 Matrix
VCIN0_PH/GPXIOD00
SPI
Device
Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/GPIO5B
KSO10/GPIO2A
SPIDO/GPIO5C
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#/GPIO5A
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
ENBKL/AD6/GPIO40
KSO16/GPIO48
PECI_KB930/AD7/GPIO41
KSO17/GPIO49
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO
EC_SMB_CK1/GPIO44
PWR_LED#/GPIO54
EC_SMB_DA1/GPIO45
BATT_LOW_LED#/GPIO55
SM Bus
EC_SMB_CK2/GPIO46
SYSON/GPIO56
EC_SMB_DA2/GPIO47
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
XCLKI/GPIO5D
XCLKO/GPIO5E
V AD_BID
0 V
0.250
0.503
0.819
10K_0402_5%
DA Output
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
min
<6>
<12,39,6>
SLP_S3#
SLP_S5#
EC_SMI#
CMOS_ON#
VAD_BID
0 V
0.216
0.436
0.712
LPC_CLK0_EC
LPC_RST#
EC_RST#
EC_SCI#
BATT_LEN#
LPC_RST#
1
2
3
4
5
7
8
10
+5VALW
+3V_EC
<6>
1
47K_0402_5%
<6>
1
<34>
0.1U_0402_16V4Z
U44
C1254
100P_0402_50V8J
AGND/AGND
GATEA20
KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
GATEA20
KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_CLK0_EC
2
R818
2
C819
@2
69
R1560
2 EMIU@ 1
10_0402_5%
@2
C1259
1000P_0402_50V7K
EMIU@
1 22P_0402_50V8J
JUMP_43X79
+3V_EC
C1261
1000P_0402_50V7K
<5,6>
<6>
<6>
<5>
<5,6>
<5>
<5>
<5>
<5>
C1258
0.1U_0402_16V4Z
C1263
C1260
1000P_0402_50V7K
C1257
0.1U_0402_16V4Z
C1262
0.1U_0402_16V4Z
2 ECAGND
1
2
L43
FBM-11-160808-601-T_0603
+EC_VCCA
C1256
0.1U_0402_16V4Z
C1255
0.1U_0402_16V4Z
+3V_EC
EC_VDD/AVCC
JUMP_43X79
J@
9
22
33
96
111
125
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
J12
J@
GND/GND
GND/GND
GND/GND
GND/GND
GND0
11
24
35
94
113
J11
1
L44
FBM-11-160808-601-T_0603
1
2
3.3V +/- 5%
Vcc
R1562 100K +/- 5%
Board ID
R1564
0
0
8.2K +/- 5%
1
18K +/- 5%
2
33K +/- 5%
3
+3VLP
+3VALW
Sheet

1
28
of
48
+3VGS
SMSC thermal sensor

placed near APU
C329
0.1U_0402_16V4Z
@
U9 THERMAL@
<11>
REMOTE1+
1
C587
2200P_0402_50V7K
<11>
REMOTE1-
REMOTE1+
REMOTE1-
THERMAL@
2
1 R335
+3VGS
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2
<11,28,4>
EC_SMB_DA2
<11,28,4>
6
5
4.7K_0402_5%
EMC1402-2-ACZL-TR MSOP 8P
Address is 1001100xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
H18
HOLEA
FD1
FD2
FD3
FD4
H_3P3
FAN1 Conn
H_3P3
H_2P8
C591
10U_0603_6.3V6M
H_2P8
H_2P8
H_2P8
H_2P8
H_2P8
H16
HOLEA
H17
HOLEA
1
2
3
4
G5
G6
H11
HOLEA
1
2
3
4
5
6
H10
HOLEA
+5VS_FAN
H8
HOLEA
1 0_0603_5%
EC_TACH
EC_FAN_PWM
H7
HOLEA
2
<28>
<28>
H6
HOLEA
JFAN1
R581
C
B
+5VS
@
HDD
H_3P8
H5
HOLEA
H_3P8
VGA_R
H4
HOLEA
H_3P8
VGA_L
H3
HOLEA
H2
HOLEA
CPU
H1
HOLEA
ACES_85205-04001
ME@
H_3P0N
2P8 * 9 pcd
10U
H_2P5X3P5N
M/B
M/B
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
B
Fintek-Thermal IC/FAN/screw
Document Number
Date: Thursday, March 28, 2013
Rev
1.0
VAWGA/GB
Sheet
1
29
of
48
+3VLP
SMT1-05_4P SWP1 @
1
KSI[0..7]
R643
100K_0402_5%
6
5
+3VALW
KSI[0..7]
<28>
KSO[0..17]
<28>
JKB1
@
2 R630
1
0_0402_5%
R642
100K_0402_5%
R701
100K_0402_5%
<28>
6
5
DAN202UT106_SC70-3
<28>
ON/OFF
NOVO_BTN#
ON/OFF
ON/OFF
D26
2
NOVO#
NOVO#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
+3VLP
2
SMT1-05_4P SWP0 @
1
KSO[0..17]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ME@
JKB2 ME@
26
25
31
32
GND
GND
GND2
GND1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88514-2401
ACES_88514-3001
WCM-2012-900T_4P
2
2
L67
USB20_N4
USB20_P4
1
4
EMICP@
USB20_N4_R
USB20_P4_R
+3VS
JCR1
<5>
<5>
R692 2 EMICU@1
EMICU@ 0_0402_5%
R687 2 EMICU@
EMICU@1 0_0402_5%
USB20_N4
USB20_P4
USB20_N4
USB20_P4
1
2
3
4
USB20_N4_R
USB20_P4_R
1
2
3
4
5
6
GND
GND
+5VS
CVILU_CF06041H0RB-NH
ME@
JTP1 ME@
C696
TP_CLK
TP_DATA
TP_3
TP_2
TP_1
TP_CLK
TP_DATA
6
5
4
3
2
1
6
5
4
3
2
1
ESDP@ C185
0.1U_0402_16V7K
JPWRB1
ACES_88058-060N
<28>
TP_3
LID_SW#
LED1 14@
<28>
2 R629
1 14@ TP_1
0_0402_5%
PWR_LED#
PWR_LED#
2 R623
1
649_0402_1%
7
8
ESDP@
+5VALW
D24
14@
19-213A-T1D-CP2Q2HY-3T_WHITE
SW4
14@
TJG-533-V-T/R_6P
SW5
14@
TJG-533-V-T/R_6P
5
6
5
6
R
4
TP_3
15/17"
ME@
14"
VCC
VCC
CLK
CLK
DAT
DAT
GND
<28>
BATT_LOW_LED#
BATT_LOW_LED#
2 R764
1
470_0402_5%
+3VALW
JLED1
14@
HT-191UD5_AMBER
+5VALW
+3VALW
+5VS
LID_SW#
5
6
5
6
LED5 14@
SW7
15@
TJG-533-V-T/R_6P
BATT_CHG_LED#
BATT_CHG_LED#
2 R765
1
649_0402_1%
+5VALW
14@
PWR_LED#
BATT_LOW_LED#
BATT_CHG_LED#
CAPS_LED#
1
2
3
4
5
6
7
8
9
10
11
12
GND
LED6 14@
TP_1
3
<28>
TP_2
3
GND
GND
LED2 14@
TP_2
SW6
15@
TJG-533-V-T/R_6P
1
2
3
4
5
6
ACES_88058-060N
PJSOT24C 3P C/A SOT-23
1
2
3
4
5
6
NOVO_BTN#
ON/OFF
3
15@
2 R628
1
0_0402_5%
<28>
<28>
+3VALW
GND
GND
8
7
0.1U_0402_16V4Z
<28>
CAPS_LED#
CAPS_LED#
2 R303
1
649_0402_1%
1
2
3
4
5
6
7
8
9
10
GND
GND
HB_A091020-SAHR21
ME@
+5VS
14@
Issued Date
Compal Secret Data
2012/04/22
Deciphered Date
2015/04/22
Title
BIOS, I/O Port & K/B CONN/TP CONN/PBTN
Size
B
Date:
Document Number
Rev
1.0
VAWGA/GB
Sheet
30
of
48
+VREF_1V65
CA3 vendor suggest

change to 2.2U
Sense resistors must be

connected same power
that is used for VAUX_3.3
0.1U_0402_16V7K
2.2U_0603_6.3V6K
CA4
CA3
CA1
0.1U_0402_16V7K
AVDD_3.3 pinis output of

internal LDO. NOT connect
to external supply.
RA7
RA8
+3VS
mount RA6 on the Jack Sense circuit

to configure Port-C for mono MIC.
10K_0402_1%
1
1
1
2 20K_0402_1%
2 39.2K_0402_1%
Don't support LINE_IN function

RA7 could be @
PLUG_IN
0.1U_0402_16V7K
30
31
25
26
APPLE_MIC
NOKIA_MIC
HGNDA
HGNDB
22
23
HP_L
HP_R
APU_SPKR
4.7U_0603_6.3V6K
CA23
4.7U_0603_6.3V6K
Headphone
2
1U_0603_10V6K
RA17 1
2 100_0402_1%
MICB_R
RA18 1
2 100_0402_1%
RA20 1
2 3K_0402_5%
RA19 1
2 3K_0402_5%
+MICBIASB
CA36
1
2
2.2U_0402_6.3V6M
CA46
1
2
2.2U_0402_6.3V6M
HP_L
HP_R
ESD
1
2
33_0402_5%
HPOUT_L
HPOUT_R
HPOUT_R
HGNDB
HGNDB
HGNDA
HGNDA
PC_BEEP
EMIP@
LA1
0_0603_5%
LA2 EMIP@
0_0603_5%
EMIP@
LA3
0_0603_5%
LA4 EMIP@
0_0603_5%
RA22
10K_0402_5%
HPOUT_L
LA1~LA4 vendor suggest mount 0 ohm first~

Bead reserve for EMI if needed
DA1
ESDP@
1
CA29
MICB_L
RA492
PLUG_IN
SINGA_2SJ2352-000131F
ME@
EMIU@
2 0.1U_0603_50V7K
CA66 1
4
3
1
2
CA31
2
1
BEEP#
HGNDB
HGNDA
HPOUT_L
HPOUT_R
For Universal jack
CX20751-11Z_QFN40
1
2
CA37 0.1U_0402_16V7K
1
2
CA45 0.1U_0402_16V7K
2 2.2U_0402_6.3V6M
2 2.2U_0402_6.3V6M
21
19
20
CA28 1
CA27 1
100_0402_1%
100_0402_1%
15_0402_5%
15_0402_5%
DA2
AVEE
FLY_P
FLY_N
RIGHT+
RIGHT-
2
2
2
2
External MIC
LEFT+
LEFT-
41
<28>
<6>
EMIP@
EMIP@
EMIP@
EMIP@
CA30 vendor suggest

change to 2.2U
EC Beep
ICH Beep
1
1
1
1
Universal Jack
PC Beep
EMIU@
2 0.1U_0603_50V7K
0.1U_0402_16V7K
CA22
CA20
+MICBIASB
+MICBIASC
MICB_L
MICB_R
RA16
RA12
RA13
RA14
AZ5125-02S.R7G_SOT23-3
32
33
APPLE_MIC
NOKIA_MIC
HP_L
HP_R
MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L
GPIO1/PORTC_R_MIC
PORTA_R
JSENSE
34
35
PORTB_L_LINE
PORTB_R_LINE
PORTD_A_MIC
PORTD_B_MIC
DMIC_DAT/GPIO1
HGNDA
DMIC_CLK / MUSIC_REQ/GPIO0
HGNDB
using wide copper bridge

under codec (100 mils or more)
EMIU@
2 0.1U_0603_50V7K
0.1U_0402_16V7K
CA21
4.7U_0603_6.3V6K
CA19
CA26
MICBIASB
MICBIASC
PC_BEEP
SPKR_MUTE#
38
17
15
JSENSE
AZ5125-02S.R7G_SOT23-3
SPK_R2+
SPK_R1-
HGNDA, HGNDB 80mils
100P_0402_50V8J
12
14
Combo Jack
(Normal Open)
Please bypass caps very close to device.
JHP1
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
GND
Internal SPEAKER
SPK_L2+
SPK_L1-
100P_0402_50V8J
CA34
2
1
36
37
MIC_IN
Internal analog MIC
100P_0402_50V8J
CA33
2
1
1
40
100P_0402_50V8J
CA32
2
1
EC_MUTE#
2.2U_0603_6.3V6K
10
39
PC_BEEP
RESET#
13
16
11
CA30
5
8
6
4
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
2 33_0402_5% HDA_SDIN0_R
HDA_SDOUT_AUDIO
LPWR_5.0
RPWR_5.0
CLASS-D_REF
CA35
RA9
HDA_RST#_AUDIO
2
1
0.1U_0402_16V7K
HDA_BITCLK_AUDIO
+5VS
1
0.1U_0402_16V7K
UA1
27
28
24
EMIU@
1 RA21
2
29
3
7
2
18
AVDD_3.3
AVDD_5V
AVDD_HP
HDA_RST#_AUDIO
<6>
CA18
10 mils
VREF_1.65V
<6>
HDA_SYNC_AUDIO
HDA_SDIN0
HDA_SDOUT_AUDIO
CA65 1
2 5.11K_0402_1%
Layout Note:Path from +5VS to LPWR_5.0

RPWR_5.0 must be very low
resistance (<0.01 ohms)
FILT_1.8
VDD_IO
VDDO_3.3
DVDD_3.3
22P_0402_50V8J 33_0402_5%
CA64 1
RA6
+5VS
0.1U_0402_16V7K
EMIU@
CA7
RA5
+LDO_1.8V
4.7U_0603_6.3V6K
CA25
CA24
CA17
For EMI
<28>
0.1U_0402_16V7K
CA6
CA15
0.1U_0402_16V7K
<6>
<6>
<6>
2 0_0402_5%
JSENSE
+3VS
0.1U_0402_16V7K
4.7U_0603_6.3V6K
CA16
RA4
CA9
CA8
Should be same supply rail as used for

PCH HDA bus controller section
+1.5VS
1U_0603_10V6K
+3VS
CA10
0_0402_5%
1U_0603_10V6K
RA10
4.7U_0603_6.3V6K
+3VALW
0.1U_0402_16V7K
+AVDD_HP
CA5
+3VLP
2 0_0402_5%
1U_0603_10V6K
CA2
+LDO_OUT_3.3V
RA11 1
ESDP@
+5VS
ESD
JSPK1
I/O1
LA1
LA2
LA3
LA4
1
2
EMIU@
FBMA-L11-160808-121LMT_0603
1
2
EMIU@
FBMA-L11-160808-121LMT_0603
1
2
EMIU@
FBMA-L11-160808-121LMT_0603
1
2
EMIU@
FBMA-L11-160808-121LMT_0603
wide 30MIL
vendor suggest
change to 1000p
SPK_L1-_CONN
CA44
0.1U_0402_16V7K
1
2
3
4
5
6
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
1000P_0402_50V7K
MIC_IN_C
1U_0603_10V6K
2
MIC_IN
I/O3
SPK_R1SPK_R2+
SPK_L1SPK_L2+
GNDA
CA42
0.1U_0402_16V7K
1
2
WM-64PCY_2P
45@
CA41
GND
SPK_L2+_CONN
1000P_0402_50V7K
CA43
EMIP@
MIC1
SPK_R2+_CONN
VDD
1000P_0402_50V7K
CA40
EMIP@
5
RA23
2.2K_0402_5%
I/O2
CA38
+MICBIASC
I/O4
EMIP@
DA3
6
SPK_R1-_CONN
1000P_0402_50V7K
CA39
EMIP@
Place colose to Codec chip
ME@
ACES_85205-04001
ESDU@
CA41 vendor suggest

change to 1U
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
Custom
CX20751 Codec
Rev
1.0
VAWGA/GB
Date: Thursday, March 28, 2013
1
2
3
4
G5
G6
Sheet
1
31
of
48
+5VALW TO +5VS
+3VALW TO +3VS
Load switch
+5VALW
VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
1 C12
VL
SUSP#
6
7
+3VALW
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
ON2
VIN2
VIN2
GND
CT2
VOUT2
VOUT2
GPAD
14
13
+5VS
1
+5VS_LS
12
9
8
PAD-OPEN 4x4m 2
@ C13
C10
1
180P_0402_50V8J
2
@
C9
1
330P_0402_50V7K
2
@
J3V J@
1
11
10
+3VS_LS
15
1
+3VS
2
PAD-OPEN 4x4m 2
@ C14
1U_0402_6.3V6K
C11
+1.8VALW
<28>
VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+1.8VS
J18V J@
U1895P
1
2
1 C24
SUSP#
VL
2
095VS_PWR_EN
095VS_PWR_EN
6
7
+0.95VALW
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
14
13
+1.8VS_LS
C21
1
12
180P_0402_50V8J
2
@
PAD-OPEN 4x4m 2
@ C26
11
330P_0402_50V7K
2
@
J95V J@
1
+0.95VS_LS
C15
1
10
9
8
15
+0.95VS
2
PAD-OPEN 4x4m 2
@ C25
+1.5V
+1.5VS
Q20
1
R1461
220_0603_5%
R1627
470_0603_5%
@
1
2
0_0402_5%
Q26
2N7002K_SOT23-3
+RTCBATT_3V
1.5VS_GATE_R
+5VALW
R1636
100K_0402_5%
1
C462
0.1U_0402_16V4Z
R339
@
SUSP
@
R1638
100K_0402_5%
2
2
1
100K_0402_5%
R337
1.5VS_GATE
2 SUSP
G
Q23
2N7002K_SOT23-3
2 SUSP
G
Q95
2N7002K_SOT23-3
@
SYSON#
OUT
SYSON
SYSON
IN
R1640
100K_0402_5%
Q102
@
R1639 @
100K_0402_5%
<28,37>
IN
SUSP#
1
<28,37>
GND
OUT
Q101
GND
2 SYSON#
G
Q93
2N7002K_SOT23-3
@
SUSP# 2
G
+5VALW
R1629
470_0603_5%
@
C463
1U_0603_10V6K
2
1 2
@
C469
10U_0603_6.3V6M
1
LP2301ALT1G_SOT23-3
1 2
+0.75VS
Vgs=-4.5V,Id=-2.8A,Rds=110mohm
1
+1.5V
+1.5V to +1.5VS
C470
10U_0603_6.3V6M
1U_0402_6.3V6K
C22
0.1U_0402_16V4Z
@
0.1U_0402_16V4Z
1U_0402_6.3V6K
+1.8VALW TO +1.8VS
+0.95VALW TO +0.95VS
Load switch
0.1U_0402_16V4Z
@
0.1U_0402_16V4Z
1U_0402_6.3V6K
SUSP#
J5V J@
U35P
1
2
@
2012/04/22
Issued Date
Compal Secret Data
2015/04/22
Deciphered Date
Title
Size
B
Date:
DC Interface
Document Number
Rev
1.0
VAWGA/GB
Sheet
E
32
of
48
VIN
JDCIN1
1
2
3
4
5
PF101
7A_24VDC_429007.WRML
1
2
APDIN1
PQ102A
2N7002KDW-2N_SOT363-6
1
100K_0402_1%
PR104
PC104
2
1
1000P_0402_50V7K
100P_0402_50V8J
PC103
2
1
PC102
2
1
<28>
ADP_ID_CLOSE
<28>
PQ102B
2N7002KDW-2N_SOT363-6
PR105
1
100K_0402_1%
VIN
ADP_ID
750_0402_1%
PC109
680P_0603_50VK
PC108
0.1U_0402_16V7K
PR102
2
100P_0402_50V8J
ACES_50312-00541-001
@
+3VALW
PL101
SMB3025500YA_2P
1
2
1000P_0402_50V7K
APDIN
PC101
2
1
1
2
3
4
5
+CHGRTC
PR103
1K_0603_5%
1
2
+RTCBATT_3V
Vin
AP2138N-1.5TRG1_SOT23-3
GND
PC111
0.1U_0603_25V7K
1
2
Vout
PC110
680P_0603_50VK
PD101
S SCH DIO BAS40CW SOT-323
2
+RTCBATT_3V 1
3
PU102
3
+RTCBATT
+3VLP
+CHGRTC_R
PR101
1K_0603_5%
1
2
JRTC1 @
1
2 1
3 2
4 GND
GND
ACES_50271-0020N-001
RTC Battery
Need use+3.3V transfer to +1.5V LDO to APU side for Kaibini
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PWR-DCIN / RTC Battery
Date:
Rev
1.0
VAWGA/B
Sheet
1
33
of
48
VMB2
PF201
12A_65V_451012MRL
1
2
PL201
SMB3025500YA_2P
1
2
2
1
PR204
100_0402_1%
PC203
0.01U_0402_25V7K
EC_SMB_CK1
<28>
EC_SMB_DA1
<28>
2
1
1
2
PR228
5.9K_0402_1%
1
1
PQ207
2N7002KW_SOT323-3
PR227
9.31K_0402_1%
PQ208
2N7002KW_SOT323-3
2
G
ECAGND
ECAGND
ECAGND
1
1
PR205
1N4148WS-7-F_SOD323-2
+3VLP
@ PR218
47K_0402_1%
1.5M_0402_5%
+5VALW
BATT_LEN#
D
PQ209
2N7002KW_SOT323-3
@ PR223
1N4148WS-7-F_SOD323-2
PU201B
AS393MTR-E1 SO 8P OP
PD203
2
@ PC210
0.068U_0402_16V7K~N
1
2
2
<28>
G
1
2
P
O
-
PR220
100K_0402_1%
8
6
@ PC213
100P_0402_50V8J
2
1
BATT_OUT
PQ202B
2N7002KDW-2N_SOT363-6
1.5M_0402_5%
@ PR208
75K_0402_1%
1
2
1
<35>
<28>
PD201
VL
PC207
100P_0402_50V8J
+3V_LDO
@ PR217
100K_0402_1%
PR222
100K_0402_1%
1
2
PU201A
AS393MTR-E1 SO 8P OP
VMB
2
G
PQ205
2N7002KW_SOT323-3
@ PU202
5
OUT
+3V_LDO
GND
SHDN#
IN
BYP
G9191-330T1U_SOT23-5
PC211 @
1U_0402_16V6K
@ PC214
4.7U_0402_6.3V6M
Compal Secret Data
Issued Date
@ PC212
22U_0603_6.3V6M
2
1
PH201
100K_0402_1%_TSM0B104F4251RZ
2
PR213
100K_0402_1%
NTC_V
<28>
2
8
P
ADP_135
PQ202A
2N7002KDW-2N_SOT363-6
2
PC208
0.068U_0402_16V7K
6 1
BATT_TEMP3
BATT_OUT <28>
2
G
ADP_90
100K_0402_1%
100K_0402_1%
PR211
PR210
47K_0402_1%
<28>
PR214
VL
2
G
ADP_65
<28>
+3VALW
VL
PR216
0_0402_5%
2
@
<28>
PR225
25.5K_0402_1%
PROCHOT
PR221
8.45K_0402_1%
Turbo_V
2
ADP_OCP_1
G
S 2N7002KW_SOT323-3
PQ206
2N7002KW_SOT323-3
PQ201
@ PR229
10K_0402_1%
1
2
PROCHOT
<28>
2
1
PR226
12.7K_0402_1%
ADP_I
2
PR215
D
H_PROCHOT#
100K_0402_1%
A/D
<28,4,40,6>
+EC_VCCA
<28,35>
<28>
BATT_TEMP
+3VS
PC202
20120314
Change to +EC_VCCA from +3VLP
+3VALW
1
2
PR207
10K_0402_5%
0.01U_0402_25V7K
PR202
75K_0402_1%
90W(DIS) : 6.65K 100W active 90W recovery

65W(UMA): 1.65K 70W active 65W recovery
PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
2
1
PR201
100_0402_1%
@
1
2
3
4
5
6
7
8
9
PC201
1000P_0402_50V7K
SUYIN_200082GR007M229ZR
BATT+
+3VLP
1
2
@ PR209
6.49K_0402_1%
JBATT2
EC_SMCA
EC_SMDA
1
2
PR206
6.49K_0402_1%
1
2
3
4
5
6
7
GND
GND
VMB
@
JBATT1
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
GND 9
GND
SUYIN_200082GR007M229ZR
2011/06/15
2012/07/11
Deciphered Date
Title

PWR-BATTERY CONN/OTP
Date:
Rev
1.0
VAWGA/B
Sheet
1
34
of
48
B+
P3
P2
PQ301
AO4407AL_SO8
PQ302
AO4423L_SO8
PR301
0.01_1206_1%
CHG_B+
1
2
3
PC319
2200P_0402_50V7K
PC316
10U_0805_25V6K
DISCHG_G
VIN
2
1
2ACOFF-1
1SS355_SOD323-2
DH_CHG
ILIM
BTST
17
PR320
PC317
2.2_0603_5%
0.047U_0603_16V7K
1
2
2
1
BST_CHG
PD301
16
REGN
4
1
15
14
13
2
1
PR318
10_0402_5%
11
6.8_0402_5%
1
12
PR317
RB751V-40_SOD323-2
PC312
1U_0603_25V6K
CHG1
SRP
BATT+
SRN
1
PC305
0.1U_0402_25V6
@
2
PACIN
DL_CHG
PC306
0.1U_0402_25V6
2
1
BQ24737VDD
SCL
124737_SN
2
18
2
G
S
PL302
PR324
10UH_PCMB104T-100MS_6A_20% 0.01_1206_1%
LX_CHG
HIDRV
PR316
100K_0402_1%
3
2
1
1U_0603_25V6K
19
PR323
4.7_1206_5%
PHASE
PU301
BQ24727RGRR_VQFN20_3P5X3P5
5
6
7
8
SDA
2N7002KW _SOT323-3
PC322
10U_0805_25V6K
2
1
3
2
0_0402_5%
PQ309
MDS1525URH 1N SO8
ACN
5
6
7
8
PR319
10_1206_5%
2
2
ACP
3
CMPOUT
CMPIN
IOUT
BM
+3VALW
10
BQ24737VCC
PQ313
D
PC320
680P_0603_50V7K
PR315
316K_0402_1%
1
2
20
PQ310
MDS1521URH 1N SO8
EC_SMB_CK1
PR311
1
3
2
1
<34>
3
21
PC314
LODRV
EC_SMB_DA1
3
1
PQ314
2N7002KW _SOT323-3
2
G
TP
GND
100P_0402_50V8J
8
10K_0402_1%
BATT_OUT
P2
VCC
SRP
0.1U_0402_25V6
5
PC304
1
2
ACDET
SRN
PC303
1
2
<28>
ACOK
1
PR309
392K_0402_1%
ACOFF
ADP_I
PR308
<28,34>
64.9K_0402_1%
1
2
<28>
2ACOFF-12
<28>
VIN
PR313
1
PD303
1SS355_SOD323-2
PC324
0.1U_0402_25V6
2
1
1
PQ305
DTC115EUA_SC70-3
PR305
150K_0402_1%
2
3
P2-2
1
0.1U_0402_25V6
2
PR325
200K_0402_1%
PC308
2N7002KDW-2N_SOT363-6
PQ307B
PR303
47K_0402_1%
1
2
PACIN
1 2
3
6
1
C
0.1U_0402_25V6
PQ306
2N7002KW _SOT323-3
2
BATT_OUT
G
ACPRN
PR306
20K_0402_1%
PQ311
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PC311
PD302
1DISCHG_G-1
1
PC307
0.1U_0402_25V6
P2-1
PR321
47K_0402_1%
ACN
PQ307A
2N7002KDW -2N_SOT363-6
PR322
200K_0402_1%
1
2
ACP
PQ303
8
7
6
5
PC323
10U_0805_25V6K
2
1
PC301
5600P_0402_25V7K
2
1
PC302
0.1U_0603_25V7K
2
1
PR304
200K_0402_1%
DTA144EUA_SC70-3
1
PR302
47K_0402_5%
PQ304
PQ312
AO4407AL_SO8
PC315
10U_0805_25V6K
1
2
2
PL301
1UH_PCMB061H-1R0MS_7A_20%
PC313
@ 10U_0805_25V6K
8
7
6
5
PC310
@ 10U_0805_25V6K
1
2
3
1
2
3
8
7
6
5
VIN
PC309
0.1U_0402_25V6
PR314
10K_0402_1%
1
2
BQ24737VDD
PR310
10K_0402_1%
<11,28>
PQ308
1
2N7002KW _SOT323-3
PR312
2
2
G
3
ACPRN
ACIN
PACIN
PR307
47K_0402_1%
12K_0402_1%
Compal Secret Data
2011/06/15
Issued Date
2012/07/11
Deciphered Date
Title
Size
Date:

PWR-CHARGER
Document Number
Rev
1.0
VAWGA/B
Sheet
1
35
of
48
PC432
0.047U_0402_25V6
2
1
3V5V_EN_R
3V5V_EN
PR402
499K_0402_1%
2
1
PR414
0_0402_5%
@ PR415
2
1
0_0402_5%
PU401
3V5V_EN_R
PC439
1
2
3
2
PC436
1
2
PC435
470P_0402_50V8J
PR413
1
1K_0402_5%
PU402
3V5V_EN
PC421
0.1U_0603_25V7K
1
2
PR405
0_0402_5%
VL
1
2@
PC438
470P_0402_50V8J
LDO
+5VALWP
1
PG
SY8208CQNC_QFN10_3X3
1.5UH_PCMC063T-1R5MN_9A_20%
OUT
PL404
1
LX_5V
PC429 @
PR406 @
2
1 5V_SN
2
1
VCC
10
680P_0603_50V7K 4.7_1206_5%
LX
PC430
4.7U_0603_6.3V6M
5
2
PC422
4.7U_0603_6.3V6M
5V_VCC
GND
PC437
470P_0402_50V8J
2
1
PC433
150U_D2_6.3VY_R15M
PC428 @
22U_0805_6.3V6M
BST_5V
PC427 @
22U_0805_6.3V6M
2
1
PC426
22U_0805_6.3V6M
2
1
PC425
22U_0805_6.3V6M
2
1
BS
PC424
22U_0805_6.3V6M
2
1
EN2
EN1
IN
PC423
22U_0805_6.3V6M
2
1
6800P_0402_25V7K
PC418
0.1U_0402_25V6
2
1
PC417
2200P_0402_50V7K
2
1
PC416
10U_0805_25V6K
2
1
PC420
10U_0805_25V6K
2
1
5V_VIN
PL403
HCB2012KF-121T50_0805
1
2
PC419
68P_0402_50V8J
2
1
B+
PR412
+3VALWP
PC434
470P_0402_50V8J
2
1
1 ENLDO_3V5V
2
1
PR410
100K_0402_1%
@
PC413 @
22U_0805_6.3V6M
2
1
+3VLP
PC414
4.7U_0603_6.3V6M
PC412 @
22U_0805_6.3V6M
2
1
+3VALWP
PC410
22U_0805_6.3V6M
2
1
LDO
SY8208BQNC_QFN10_3X3
1.5UH_PCMC063T-1R5MN_9A_20%
1
PG
OUT
@
1
GND
PL402
1
LX_3V
0_0402_5%
1K_0402_5%
0.1U_0603_25V7K
10
0.01U_0402_25V7K
PC409
22U_0805_6.3V6M
2
1
1
BST_3V
PR416
2
PC408
22U_0805_6.3V6M
2
1
PC402
1
2
PC415 @
PR404
2
13V_SN
2
EN2
PR401
0_0402_5%
+3VLP
IN
LX
SPOK
EN1
BS
2
1
PR417
100K_0402_1%
<37>
PC406
10U_0805_25V6K
2
1
PC405
10U_0805_25V6K
2
1
PC404
2200P_0402_50V7K
2
1
PC403
0.1U_0402_25V6
2
1
PC401
68P_0402_50V8J
2
1
3V_VIN
IN
680P_0603_50V7K
4.7_1206_5%
PL401
HCB2012KF-121T50_0805
1
2
B+
PC407
1U_0603_25V6K
2
1
2 ENLDO_3V5V
PR403
150K_0402_1%
2
1
B+
PR411
10K_0402_1%
PC411
22U_0805_6.3V6M
2
1
@PJ401
@
PJ401
1
+3VALWP
<28>
EC_ON
<28>
MAINPWON
EC_ON
MAINPWON
PR407
2.2K_0402_5%
2
1
1
+3VALW
JUMP_43X118
@PJ402
@
PJ402
1
+5VALWP
PR408
0_0402_5%
+5VALW
JUMP_43X118
1
2
PR409
1M_0402_1%
PC431
4.7U_0402_6.3V6M
3V5V_EN
Compal Secret Data
2011/06/15
Issued Date
2012/07/11
Deciphered Date
Title

PWR-3VALWP/5VALWP
Date:
Rev
1.0
VAWGA/GB
Sheet
E
36
of
48
PL502
1
2
HCB2012KF-121T50_0805
UG_1.5V
Off
LX_1.5V
PR503
0_0402_5%
BST_1.5V
PC513
2200P_0402_50V7K
@
PC517
680P_0603_50V7K
PC521
PC522
330U_2.5V_M 2
2 220U_6.3V_M
16
12
11
2
1
PR514
5.1_0603_5%
+3VALW
10
PGOOD
PR511
6.65K_0402_1%
2
1
3
2
1
BOOT
TON
S5
S3
7
S3_1.5V
13
+5VALW
+1.5VP
OCP min 20A
OVP min 1.65V
PC511
1U_0603_10V6K
PGOOD_1.5V
PR507
5.6K_0402_1%
2
1
PJ504
2
@
VDD
LG_1.5V
PR515
4.7_1206_5%
0_0402_5%
@ PC508
0.1U_0402_16V7K
PJ505
2
+1.5VP
PR506
5.76K_0402_1%
JUMP_43X118
@ PC526
1
2
+1.5VP
PR509
887K_0402_1%
2
1 1.5V_B+
1
<28,32>
PC503
0.1U_0402_16V6K
PL501
1UH_PCMB104T-1R0MH_18A_20%
2
1
14
S5_1.5V
<28,32>
PR505
SYSON
PHASE
17
18
VDDQ
FB
1
2
VDDP
6
PR502
49.9K_0402_1%
1
2
SUSP#
CS
RT8207MZQW _W QFN20_3X3
VTTREF
PC506
0.033U_0402_16V7K
PGND
15
GND
+1.5VP
LGATE
VTTSNS
+VTT_REFP
19
VTTGND
UGATE
PAD
VLDOIN
20
PU501
21
VTT
PC505
10U_0805_25V6K
PC504
10U_0805_25V6K
+0.75VSP
PR501
PC512
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.5V-1
1
2
Note: S3 - sleep ; S5 - power off
3
2
1
Off
B+
Off
PC510
1U_0603_10V6K
2
1
Lo
2
1
PR510
10K_0402_5%
Lo
S4/S5
1
PC509
0.1U_0402_25V6
+1.5VP
On
Off
(Hi-Z)
On
On
On
On
Hi
Hi
Lo
Hi
S3
S0
0.75VSP
PC501
10U_0805_25V6K
VTT_REFP
1.5VP
PQ501
MDU1516URH_POWERDFN56-8-5
S5
PQ502
MDU1511RH_POWERDFN56-8-5
S3
STATE
PC520
4.7U_0805_25V6-K
1.5V_B+
68P_0402_50V8J
+1.5V
JUMP_43X118
PJ506
2
+0.75VSP
+0.75VS
JUMP_43X79
@
3
PU502
SY8033BDBC_DFN10_3X3
2
2
095_18ALW_PWR_EN
<28>
PC524
0.1U_0402_10V7K
PC519
0.1U_0402_25V6
1
2
PC518
68P_0402_50V8J
1
2
PC516
2200P_0402_50V7K
PC515
22U_0805_6.3VAM
1
2
PC514
22U_0805_6.3VAM
PG
PR512
20K_0402_1%
PC525
68P_0402_50V8J
2
1
PR508
4.7_1206_5%
1
1 2
NC
+1.8VALWP
PJ507
+1.8VALW P
+1.8VALW
@ JUMP_43X79
1.8VSP_FB
1
PR504
1M_0402_5%
PR611
FB=0.6Volt
11
<36,38>
FB
EN
PC523
680P_0603_50V7K
0_0402_5%
EN_1.8VSP
PC507 @
0.1U_0402_10V7K
@ PR516
1
SPOK
LX
SVIN
TP
PVIN
1.8VSP_LX
PC502
22U_0805_6.3VAM
LX
@ JUMP_43X79
PVIN
NC
10
1.8VSP_VIN
PL503
1UH_PH041H-1R0MS_3.2A_20%
1
2
PJ502
2
+3VALW
0_0402_5%
PR513
10K_0402_1%
4
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

PWR-+1.5VP/+1.8VALWP
Custom
Date:
Rev
1.0
VAWGA/GB

D
Sheet
37
of
48
PL601
HCB2012KF-121T50_0805
1
2
3
2
1
DH_0.95V
0.95V_RF
EN
SW
VFB
V5IN
LX_0.95V
RF
DRVL
TP
7
6
11
+5VALW
DL_0.95V
PC608
1U_0603_10V6K
4
TPS51212DSCR_SON10_3X3
VFB=0.7V
3
2
1
3.48K_0402_1%
PR608
10K_0402_1%
PC605
2
1
PC604
2
1
1
+
PC607
220U_6.3V_M
+0.95VALWP OCP(min)=15.6A
+0.95VALWP
PR604
4.7_1206_5%
DRVH
0.95V_FB
TRIP
PL661
1UH_PCMC063T-1R0MN_12A_20%
1
2
0.95V_EN
PR606 2
PR602
PC606
2.2_0603_5%
0.22U_0603_16V7K
1
2BST_0.95V-11
2
BST_0.95V
470K_0402_1%
PR607
1
2
@ PC601
.1U_0402_16V7K
@ PR605
47K_0402_5%
PR605 reserve
0.95V_TRIP
VBST
PC609
680P_0603_50V7K
SPOK
PGOOD
5
6
7
8
@ PR601
0_0402_5%
1
2
10
PU601
1
PR603
40.2K_0402_1%
PQ602
MDS1521URH 1N SO8
2
0_0402_5%
<37>
PR610
1
095_18ALW_PWR_EN
<28>
B+
2200P_0402_50V7K
2
0_0402_5%
0.1U_0402_25V6
PR609
1
PC603
10U_0805_25V6K
2
1
PQ601
MDS1525URH 1N SO8
5
6
7
8
PC602
10U_0805_25V6K
2
1
0.95V_B+
PJ602
2
@
+0.95VALWP
JUMP_43X118
PJ603
2
@
+0.95VALW
1
JUMP_43X118
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

PWR-+0.95VALWP
Document Number
Rev
1.0
VAWGA/B
Sheet
1
38
of
48
PR808 @ 10K_0402_1%
1
2
10K_0402_1%
2
10K_0402_1%
2
10K_0402_1%
2
10K_0402_1%
2
PR809
1
GPU_VID4
GPU_VID3
PR810
1
GPU_VID2
PR811
1
GPU_VID1
PR812
1
GPU_VID0
1
2
PR807 @ 10K_0402_1%
1
2
GPU_VID5
B+
@ PC804
10U_0805_25V6K
2
1
PR806 @ 10K_0402_1%
1
2
GPU_VID0
10K_0402_1%
2
10K_0402_1%
2
PR805 @ 10K_0402_1%
1
2
GPU_VID1
PR804
1
GPU_VID2
@ PC803
10U_0805_25V6K
EC_VGA_EN
2 VRON_VGA
@ PC802
2200P_0402_50V7K
2
1
<28>
PL801
HCB4532KF-800T90_1812
1
2
PC801 @
0.1U_0402_25V6
2
1
PXS_PWREN
+VGA_B+
<12,28,6>
GPU_VID3
GPU_VID5
@ PR813
0_0402_5%
1
PR802
1
GPU_VID4
10K_0402_1%
2
GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0

1
1
0
1
0
NA
PR801
1
VBOOT
0.85V
PR803 @ 10K_0402_1%
1
2
+3VGS
+
2
1
+
2
PC810
330U_D2_2V_Y
PC809
330U_D2_2V_Y
ISEN1_VGA
VSUM-_VGA
PC808
330U_D2_2V_Y
PC807
330U_D2_2V_Y
1
@ PR837
2
10K_0402_1%
@ PR829
1_0402_1%
2
1
@ PR828
10K_0402_1%
ISEN2_VGA
VSUM+_VGA
@ PR827
3.65K_0402_1%
2
1
PR826 @
4.7_1206_5%
2
1
PC837
2.2U_0402_6.3V6M
2
1
PC838
2.2U_0402_6.3V6M
2
1
PC856
0.1U_0402_10V7K
2
1
PC857
0.1U_0402_10V7K
2
1
PC839
2.2U_0402_6.3V6M
PC836
2.2U_0402_6.3V6M
2
1
PC830
2.2U_0402_6.3V6M
2
1
PC846
10U_0603_6.3V6M
PC855
0.1U_0402_10V7K
2
1
PC829
2.2U_0402_6.3V6M
2
1
PC845
10U_0603_6.3V6M
2
1
PC835
2.2U_0402_6.3V6M
2
1
PC828
2.2U_0402_6.3V6M
2
1
PC844
10U_0603_6.3V6M
2
1
PC834
2.2U_0402_6.3V6M
2
1
PC827
2.2U_0402_6.3V6M
2
1
PC843
10U_0603_6.3V6M
2
1
PC833
2.2U_0402_6.3V6M
2
1
PC826
2.2U_0402_6.3V6M
2
1
PC842
10U_0603_6.3V6M
2
1
PC832
2.2U_0402_6.3V6M
2
1
PC825
2.2U_0402_6.3V6M
2
1
PC841
10U_0603_6.3V6M
2
1
PC831
2.2U_0402_6.3V6M
2
1
PC824
2.2U_0402_6.3V6M
2
1
PC854
1U_0402_6.3V6K
2
1
PC853
1U_0402_6.3V6K
2
1
PC852
1U_0402_6.3V6K
2
1
PC851
1U_0402_6.3V6K
2
1
1
<28>
+VGA_B+
PR852
2.2_0603_5%
2
1
BOOT1_1_VGA
PQ802
CSD87351Q5D_SON8-7
PC881
10U_0805_25V6K
2
1
@
PC858
0.22U_0603_10V7K
1
2
PC880
10U_0805_25V6K
PC879
2200P_0402_50V7K
2
1
PC878
0.1U_0402_25V6
2
1
UGATE1_VGA
PL803
0.22UH_PCME064T-R22MS_28A_20%
SW1_VGA
@
VSUM-_VGA
+VGA_CORE
V1N_VGA
1_0402_1%
10K_0402_1%
PR858
2
1
VSUM-_VGA
Layout Note:
Place near Phase1 Choke
PR857
10K_0402_1%
1
LF1_VGA
ISEN1_VGA
PR855
4.7_1206_5%
2
1
8
LGATE1_VGA
PR856
3.65K_0402_1%
2
1
ISEN2_VGA
PHASE1_VGA
@ PR838
2
7
6
5
PH802
10K_0402_1%_TSM0A103F34D1RZ
2
PC860
0.1U_0603_25V7K
2
1
PC861
0.033U_0603_25V7K
2
1
PR859
11K_0402_1%
2
1
V2N_VGA
VSSSENSE_VGA
PR862
887_0402_1%
1
2
PC866
0.1U_0402_16V7K
Sun Pro
OCP:42A
+5VS
VSUM+_VGA
+VGA_CORE
PC865
680P_0402_50V7K
2
1 SNUB1_VGA
0_0402_5%
PR861
10_0402_1%
1
2
VSSSENSE_VGA
PC864 @
0.01U_0402_25V7K
<14>
PR860
PC863 @
330P_0402_50V7K
2
1
PC862
1000P_0402_50V7K
PC859
330P_0402_50V7K
0_0402_5%
VSUM_VGA_N001
PC811 @
680P_0402_50V7K
2
1
SNUB2_VGA
+5VS
GPU_IMON
0_0402_5%
PR853
2.61K_0402_1%
2
1
NTC_VGA
PR854
PC840
10U_0603_6.3V6M
2
1
1
+VGA_B+
PR851 @
82.5_0402_5%
VCCSENSE_VGA
8
1_0402_5%
PC877
0.22U_0603_25V7K
PC876
1U_0603_10V6K
2
1
1
@
PR850
10_0402_1%
<14>
<11>
<11>
GPU_VID0
<11>
2
2
0_0402_5%
PR848
1
2
1
2
@ 0_0402_5%
2
PR865
2
BOOT1_VGA
<11> GPU_VID1
1
2
VIN_VGA
VSUM+_VGA
1
+VGA_CORE
LF2_VGA
PC872
1U_0603_10V6K
ISEN1_VGA
VSUM-_VGA
SW2_VGA
+5VS
PR845
ISEN2_VGA
PR849
30K_0402_1%
+VGA_CORE
30
29
28
27
26
25
24
23
22
21
PR844
VSEN_VGA
For 15W one phase
PL802
0.22UH_PCME064T-R22MS_28A_20%
7
6
5
PR863
0_0402_5%
1
2
PQ801
CSD87351Q5D_SON8-7
2
PHASE2_VGA
ISL62883CHRTZ-T_TQFN40_5X5
+5VS
PR846
267K_0402_1%
PR864
0_0402_5%
1
2
PC848
150P_0402_50V8J
PR843
1.69K_0402_1%
1
2
2FB2_VGA
1
PR842
499_0402_1%
PC874
2FB1_VGA1
2
AGND
390P_0402_50V7K
PC847
33P_0402_50V8J
1
2
41
PC850
0.22U_0402_10V6K
1
2
PC873
1000P_0402_50V7K
PR841
5.9K_0402_1%
1
2
PR840 @
249K_0402_1%
1
2
@ PC871
22P_0402_50V8J
PC806
0.22U_0603_10V7K
1
2
UGATE2_VGA
PC812
1U_0603_10V6K
1
2
0.047U_0402_16V7-K
1
2
PR847
6.65K_0402_1%
COMP_VGA
FB_VGA
2ISEN3_VGA
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
PC849
2
1
1
2
3
4
5
6
7
8
9
10
VW_VGA
1
BOOT2_2_VGA
GPU_VID6
@
PU801
VDD_VGA
2 PR836 1
147K_0402_1%
40
39
38
37
36
35
34
33
32
31
GPU_GPIO0
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PR833
2.2K_0402_1%
1
2
@
1 PR834 2
0_0402_5%
@ PR835
1
2
2.2K_0402_1%
+3VS
PR817
P
R817
2.2_0603_5%
2
1
BOOT2_VGA
LGATE2_VGA
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
0_0402_5%
CLK_ENABLE#_VGA
PC875
0.22U_0402_10V6K
PR831
2
1
1.91K_0402_1%
PR832
1
VGA_PWRGD
DPRSLPVR_VGA-1
2.2K_0402_1%
PR830 @
1.91K_0402_1%
1
2
+3VS
11
12
13
14
15
16
17
18
19
20
0_0402_5%
PR819
1
2
<11> GPU_VID2
RTN_VGA
ISUM-_VGA
GPU_GPIO0
<11>
PC805 @
1
2
100P_0402_25V8K
RBIAS_VGA
PSI#_VGA
@ PR818
1
GPU_VID5
PR816
2.2K_0402_1%
1
2
@
+3VS
GPU_VID3
PR814
0_0402_5%
2
0_0402_5%
GPU_VID4
PR820
1
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
PWR-VGA_CORE
Size
C
Date:

Document Number
Rev
1.0
VAWGA/GB
D
Sheet
39
of
48
0_0402_5%
PHASE_NB1
PC1032
2200P_0402_50V7K
2
1
PC1030
0.1U_0402_25V5K
2
1
PC1029
10U_0805_25V6K
2
1
680P_0603_50V7K
2
1 2
PR912
3.65K_0402_1%
1
VSUMP_NB 2
@ PC1040
PR914
1_0402_1%
1
VSUMN_NB 2
<28>
0_0402_5%
3
2
1
PR932
ISEN2
PHASE1
PC1052
2200P_0402_50V7K
2
1
PR955
UGATE1
VGATE
PC1051
0.1U_0402_25V5K
2
1
PC6601
1000P_0402_50V7K
PC1050
10U_0805_25V6K
2
1
PR929
100K_0402_1%
PC1048
10U_0805_25V6K
2
1
CPU_B+
PC1049
10U_0805_25V6K
2
1
+3VS
PQ903
BOOT1
UGATE1
21
3
2
1
PHASE1
22
PGOOD
23
20
COMP
19
FB
18
RTN
17
16
NTC
11
VSEN
BOOT1
ISUMN
IMON
LGATE1
PQ907
UGATE1
24
PWROK
PR924
2
1
1_0603_5%
25
PHASE1
26
PC1046
1U_0603_25V6K
LGATE1
ENABLE
+5VALW
27
32
33
34
35
36
31
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PGOOD_NB
37
SVT
28
29
+APU_CORE_NB
30
+5VS
PH903
470K_0402_5%_TSM0B474J4702RE
2
1
2012/10/30
Load Line:VDD-->4m
VDDNB-->4.0m
PC1045
1U_0603_25V6K
VDD
20K_0402_1%
1 PR931
VDDP
ISL62771HRTZ-T_TQFN40_5X5
VDDIO
10
PR930 27.4K_0402_1%
2
1
38
LGATE2
SVD
FB_NB
39
VR_HOT_L
15
2
1
PC1073
1
2
0.1U_0402_25V6
1 PR928 2
133K_0402_1%
PC1047
1000P_0402_50V7K
1
2
ISUMP
APU_SVD
1 PR953 2
0_0402_5%
1<4>
12
+1.5VS
APU_SVT
@ PR952
0_0402_5% <28>
PC1044
VR_ON
PC6602 1000P_0402_50V7K 0.1U_0402_25V6
2
1 PR951 2
<4>
APU_PWRGD
0_0402_5%
+1.8VS
PHASE2
14
1 <4>
SVC
ISEN1
PR919
133K_0402_1%
<28,34,4,6>
100K_0402_1% @ PR922
2
+3VS
UGATE2
ISEN2
APU_SVC
BOOT2
IMON_NB
13
<4>
H_PROCHOT#
APU_IMON
NTC_NB
2
0_0402_5%
2 SVC
0_0402_5%
2
0_0402_5%
2 SVD
0_0402_5%
2 VDDIO
0_0402_5%
2 SVT
0_0402_5%
2 ENABLE
0_0402_5%
2 PWROK
COMP_NB
1
PR918
1
PR920
1
PR921
1
PR923
1
PR925
1
PR926
1
PR927
1
VSEN_NB
470K_0402_5%_TSM0B474J4702RE
PH902
40
PU901
ISUMN_NB
41
PC1043
1000P_0402_50V7K
2
1
BOOT_NB1
PR917
UGATE_NB1
TP
@ PR910
4.7_1206_5%
20K_0402_1%
ISUMP_NB
27.4K_0402_1%
2
1
12
PR916
+ PC1031
220U_25V_M
LGATE_NB1
B+
PL902
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PR913
324_0402_1%
2
1
2011/10/21
NTC near NB_CORE H/S mos
LGATE_NB1
@ PR915
@ PC1042
100_0402_1% 220P_0402_50V7K
2
1
2
1
PC1041
0.1U_0603_50V7K
3
2
1
PC1039
0.15U_0603_16V7K
2
1
PC1038
0.022U_0402_25V7K
1
2
1
2
PR911
11K_0402_1%
PL901
HCB2012KF-121T50_0805
1
2
SH00000N900 (DCR 1.1+-5%)
PR908
PC1036
2.2_0603_1% 0.22U_0603_25V7K
2
1 2
1
BOOT_NB1
PC1037
0.01U_0402_50V7K
VSUMN_NB
PH901
10K_0402_5%_ERTJ0ER103J
2
12
1
PR909
2.61K_0402_1%
VSUMP_NB
PHASE_NB1
PQ906
2011/10/21
NTC near phase 1 choke
PC1035
47P_0402_50V8J
2
1
PR906
PC1034
PR907
0_0402_5% 1000P_0402_50V7K 499_0402_1%
1
2
2
1
2
1
PC1028
10U_0805_25V6K
2
1
PC1027
10U_0805_25V6K
2
1
3
2
1
PR903
1.54K_0402_1%
2
1
PQ902
PR902
10_0402_5%
2
1
+APU_CORE_NB
PR954
UGATE_NB1
150P_0402_50V8J
PC1033
PR904
@ PR905
267K_0402_1%
41.2K_0402_1%
2
1
2
1
2
1
3
2
1
APU_VDDNB_SEN
PQ901
PC901
PR901
330P_0402_50V7K 2K_0402_1%
2
1
2
1
<4>
3
2
1
PQ905
CPU_B+
SH00000GH00 (DCR 1.25+-7%)

PL903
0.36UH_FDUE1030D-H-R36M=P3_32A_20%
+APU_CORE
0_0402_5%
LGATE1
PR945
487_0402_1%
2
1
PR946
10_0402_5%
2
1
PC1063@
@ PR948
820P_0402_50V7K
100_0402_1%
2
1
2
1
PR947
0_0402_5%
1
2
2011/10/21
NTC near phase 1 choke
PR949
0_0402_5%
1
2
PR950
10_0402_5%
2
1
3
2
1
PR944
PC1061
2K_0402_1% 330P_0402_50V7K
2
1
2
1
1 2
2
PR940
PC1058
267K_0402_1% 150P_0402_50V8J
2
1
2
1
@ PR935
4.7_1206_5%
VSUM+
PQ904
PR939
1.54K_0402_1%
2
1
PR938 @
32.4K_0402_1%
2
1
3
2
1
PC1055
47P_0402_50V8J
2
1
PQ908
PC1056
330P_0402_50V7K
PC1060
0.15U_0603_16V7K
2
1
PC1059
0.01U_0402_50V7K
1
2
2
1
PR943
11K_0402_1%
PC1062
0.1U_0603_50V7K
PC1054
PR937
1000P_0402_50V7K 499_0402_1%
2
1
2
1
VSUM-
VSUM+
PH904
10K_0402_5%_ERTJ0ER103J
2
12
1
PR942
2.61K_0402_1%
2011/10/21
NTC near CPU_CORE H/S mos
PR933
PC1053
2.2_0603_1%
0.22U_0603_25V7K
1
2
1
BOOT12
ISEN1
1
PR934
10K_0402_1%
PC1064
0.01U_0402_50V7K
@ PC1057
680P_0603_50V7K
VSUM-
PR936
3.65K_0402_1%
2
1
PR941
1_0402_1%
2
1
+APU_CORE
APU_VDD_SEN
<4>
APU_VDD_RUN_FB_L <4>
Compal Secret Data
Issued Date
2011/07/08
Deciphered Date
2015/07/08
Title

APU_CORE/APU_CORE_NB
Custom
Date:
Rev
1.0
VAWGA/B

1
Sheet
40
of
48
10U_0603 *3
PC1019
2
1
1
PC1071
1
PC1072
1
PC1069
1
PC1070
1
PC1013
1
PC1014
1
PC1015
1
PC1016
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
0.01U_0402_25V7K~N
1
PC1009
1
PC1010
1
PC1011
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
0.01U_0402_25V7K~N
PC1020
2
1
0.1U_0402_25V7K~N
1
PC1067
1
PC1068
1
PC1065
1
PC1066
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
1
22U_0603_6.3V6MPC1005
2
1
22U_0603_6.3V6MPC1006
2
1
22U_0603_6.3V6MPC1007
2
1
22U_0603_6.3V6MPC1008
1
PC1001
1
PC1002
1
PC1003
1
PC1004
PC1018
2
1
+APU_CORE_NB
0.1U_0402_25V7K~N
10U_0603 * 4
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
2
22U_0603_6.3V6M
PC1017
2
1
+APU_CORE
1
+
2
1
+
2
1
+
2
1
+
PC1026
330U_D2_2V_Y
PC1025
330U_D2_2V_Y
PC1024
330U_D2_2V_Y
PC1023
330U_D2_2V_Y
PC1022
330U_D2_2V_Y
PC1021
330U_D2_2V_Y
2@
2011/07/08
Issued Date
Compal Secret Data
2015/07/08
Deciphered Date
Title
PWR-PROCESSOR DECOUPLING
Rev
1.0
VAWGA/B
Date:
Sheet
E
41
of
48
Version change list (P.I.R. List)

Item
Page 1 of 1
for PWR
Reason for change
PG#
Modify List
Date
Phase
1
D
2
3
4
5
6
7
8
C
9
10
11
12
13
14
B
15
16
17
A
2011/06/15
Issued Date
Compal Secret Data
Deciphered Date
2012/07/11
Title
Custom
PIR (PWR)
Rev
C38-G series Chief River Schematic1.0
Date:
Sheet
1
42
of
48
Page 1 of 1
for HW
Item
Reason for change
PG#
Modify List
Date
Phase
For share rom
28
Change SYS_PWRGD_EC from pin 86 to pin 32
12/17
DVT
For 095VS_PWR_EN pull down
28
Add R207
12/17
DVT
For VBIAS first raise up
12,
32
Change U1895V, U35P, U1895P VBIAS from +5VALW to VL
12/17
DVT
For follow VIWGP design
27
Change JUSB3 pin define
12/18
DVT
For Audio Precision
31
Change CA36, CA46 from 1U to 2.2U
12/21
DVT
For SYS_PWRGD_EC pull down
28
Add R208
12/24
DVT
For share rom
28
Change R1575, R1576 to 100K
12/24
DVT
For reserve EC +3VL
28
05
Add J11, J12 and modify +3VALW to +3V_EC
12/24
DVT
For share ROM
05
modify ROM net-name & resistor value
12/24
DVT
10
For common VIWGP design
22
modify R106, R107 to 22ohm
12/24
DVT
11
For power S3 reduction
28
Change EC_INVT_PWM to ADP_ID_CLOSE
12/25
DVT
12
For common VIWGP design
23
Change JODD1 symbol
12/27
DVT
13
For reserve wake on wlan function
26
Add R1500
12/27
DVT
14
For 1.5VS discharge
32
Change R339 to 0ohm, mount Q23 & R1461
12/29
DVT
15
For AMD suggest
Change R576 to 0ohm
12/29
DVT
16
For VGA sequence
12
Delete R123 & C40, change C28, C27 to 2200P
12/29
DVT
17
For +3VALW APU Power Consumption
Add R582
01/03
DVT
18
For ESD request
22
28
40
Add C600, C601, PC6601, PC6602
01/03
DVT
19
For no support DC wake & LID function
28
Pull high only SMB & RST use +3V_EC, other use +3VALW
01/04
DVT
20
For reserve cost down experiment
30
Add R630, R643
01/04
DVT
21
For Common VIWGP
30
Change SW4,SW5,SW6,SW7 footprint
01/04
DVT
22
For instant plug/unplug AC has beep sound 31
@RA22
01/04
DVT
23
5
6
12
Modify C794,C795,C682,C686,CV36,CV37 value
01/09
DVT
For Crystal Capactance fine tune
2011/06/15
Issued Date
Compal Secret Data
Deciphered Date
2012/07/11
Title
Custom
PIR (PWR)
Rev
Date:
Sheet
1
43
of
48

Item
Page 1 of 1
for HW
Reason for change
PG#
For EMI request
30
Change L67 to EMICP@, Change R692,R687 to EMICU@
02/02
PVT
For Share ROM recoverable solution as

original method
05
Add RP12
02/02
PVT
For BIOS post time
06
Pull high PXS_PWREN to +3VS by RP14
02/02
PVT
For ZiZi noise
31
Change AVDD_HP from +3VS to +3VLP
02/02
PVT
For follow KABINI latest CRB
04
@ R576,C164,C342
02/02
PVT
For APU control PWM only
21
Delete R1465
02/02
PVT
For Corret Net-name to prevet confuse
04
21
Change TL_INVT_PWM, TL_ENVDD to APU_INVT_PWM, APU_ENVDD
02/02
PVT
For Reserve DDC CLK DATA pull high
22
Add R693, R697
02/02
PVT
For Common Intel project
30
Change R623,R765,R303 to 620ohm
02/02
PVT
10
23
Reserve R551
02/02
PVT
11
For reduce BOM
31
Delete RA3, and Change RA4 to short-pad
02/05
PVT
12
For reduce BOM
26
Change R1498,R1499 from 0 ohm to 100 ohm
02/05
PVT
13
For reduce BOM
Change RV43,LV1,LV2,LV3,LV4,LV5,LV6,RV16,RV17,LV7,LV8,LV9,LV10
to short-pad
02/05
PVT
14
For better location
CV72 <-> CV171 ; CV60 <-> CV70 ; CV154 <-> CV191
02/05
PVT
15
For reduce BOM
21
Change R1463 from 0 ohm to short-pad
02/06
PVT
16
For better audio precision performance
31
Change CA27,CA28 from 1U to 2.2U
02/08
PVT
17
For reduce BOM & layout concern
07
Delete C195
02/16
PVT
18
For test point request
22
Add T49, T58 on JCRT1
02/18
PVT
19
For ESD request
25
Add C173, C178
02/18
PVT
20
For reduce BOM
05
Change R112, R115, R116, R119, R125, R126 to short-pad
02/18
PVT
21
For Crystal timming
06
Change C682 from 18P to 22P
02/20
PVT
22
For ESD request
30
Change D24 from ESDU@ to ESDP@, Part number from SCA00000E00

to SCA00001G00
02/23
PVT
23
For EMI request
21
27
30
Change L58,L51,L55,L66,L67 from SM070000K00 to SM070000Z00
02/23
PVT
11
12
13
14
14
18
19
Modify List
Date
Phase
2011/06/15
Issued Date
Compal Secret Data
Deciphered Date
2012/07/11
Title
Custom
PIR (PWR)
Rev
Date:
Sheet
1
44
of
48

Item
Page 1 of 1
for PWR
Reason for change
PG#
Modify List
Date
Phase
30
Change R623,R765,R303 to 649ohm
03/05
PreMP
For VGA Clock Request
06
Reserve R578,R689
03/05
PreMP
For Reduce BOM
05
Change R103, R104 to short-pad
03/11
PreMP
For Reduce BOM
21
Change R696, R695, R813 to short-pad
03/11
PreMP
For Reduce BOM
23
Change R550 to short-pad
03/11
PreMP
For Reduce BOM
28
03/11
PreMP
For Reduce BOM
29
03/11
PreMP
For Reduce BOM
31
Change RA11 to short-pad
03/11
PreMP
For Reduce BOM
32
03/11
PreMP
10
For Reduce BOM
06
03/11
PreMP
11
For Reduce BOM
07
03/11
PreMP
12
For ESD require
30
Add C185
03/25
PreMP
13
For Module Design
22
Change R693, R697 from 10k to 4.7k
03/25
PreMP
14
For ESD require
04
Add C195
03/26
PreMP
15
For Reduce BOM
04
@ RP11
03/26
PreMP
16
For Board ID
28
@ R1562 and change R1564 to 0ohm
03/28
PreMP
17
2011/06/15
Issued Date
Compal Secret Data
Deciphered Date
2012/07/11
Title
Custom
PIR (PWR)
Rev
Date:
Sheet
1
45
of
48
Power-Up/Down Sequence
Mars XT VRAM STRAP
Vendor
PS_3[ 2 ] PS_3[ 1 ] PS_3[ 0 ]
K4W2G1646E-BC1A
SA000068U00
MT41J128M16JT-093G:K
SA000067500
R_pu
R_pd
RV20
RV27
NC
0
4.75K
RV20
RV27
8.45K
2G
H5TQ2G63DFR-N0C
SA000065300
1G
H5TC2G63FFR-11C
SA00006H400
K4W1G1646G-BC11
SA00004GS00
H5TQ1G63EFR-11C
SA000041SB0
MS2G@
MM2G@
OLDMH2G@
NEWMH2G@
MS1G@
MH1G@
RV20
2K
RV20
RV27
4.53K
4.99K
RV20
RV27
6.98K
4.99K
RV27
4.53K
2K
"Mars" has the following requirements with regards to power-supply

sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/s.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
RV20
RV27
4.75K
NC
VDDR3(3.3VGS)
PCIE_VDDC(0.95VGSV)
VDDR1(1.5VGS)
X7646738L01
X7646738L02
X7646738L09
X7646738L10
X7646738L03
X7646738L04
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PERSTb
SUN PRO VRAM STRAP

REFCLK
Vendor
2G
PS_3[ 2 ] PS_3[ 1 ] PS_3[ 0 ]
K4W4G1646B-HC11
SA000068R00
MT41K256M16HA-107G:E
SA000065D00
H5TQ4G63MFR-11C
SA00006DG00
K4W2G1646E-BC1A
SA000068U00
1G
R_pd
RV20
RV27
NC
RV20
8.45K
MT41J128M16JT-093G:K
SA000067500
R_pu
RV20
4.53K
H5TC2G63FFR-11C
SA00006H400
H5TQ2G63DFR-N0C
SA000065300
Straps Reset
4.75K
Straps Valid
RV27
2K
Global ASIC Reset
RV27
T4+16clock
2K
RV20
RV27
6.98K
4.99K
RV20
RV27
3.4K
10K
RV20
RV27
4.53K
4.99K
RV20
RV27
4.75K
NC
SS2G@
SM2G@
SH2G@
SS1G@
SM1G@
NEWSH1G@
OLDSH1G@
X7646738L05
X7646738L06
TBD
X7646738L07
X7646738L08
X7646738L13
X7647538L01
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
Title
VGA Notes List
Custom
Date:
Rev
1.0
VAWGA/GB
Sheet
1
46
of
48
EC_ON
B+
+3VLP
PU401
SY8208BQKC
+3VALW
+EC_VCCA
LAN_PWR_ON#
+3V_LAN
P-CHANNEL
PMV65XP
1
SUSP#
U35P
TPS22966DPUR
+3VS
PXS_PWREN
U315V
TPS22966DPUR
+3VGS
SPOK
PU502
SY8033BDBC
+1.8VALW
SUSP#
U1895P
TPS22966DPUR
+1.8VS
PXS_PWREN
U1895V
TPS22966DPUR
+1.8VGS
EC_ON
+VL
PU402
SY8208CQKC
+5VALW
SUSP#
U35P
TPS22966DPUR
+5VS
SUSP# / SYSON
+0.75VS
PU501
RT8207MZQW
+1.5V
SUSP#
P-CHANNEL
LP2301ALT1G
+1.5VS
PXS_PWREN
U315V
TPS22966DPUR
+1.5VGS
SPOK
PU601
TPS51212DSCR
+0.95VALW
SUSP#
U1895P
TPS22966DPUR
+0.95VS
PXS_PWREN
U1895V
TPS22966DPUR
+0.95VGS
EC_VGA_EN
PU801
ISL62883CHRTZ
+VGA_CORE
VR_ON
+APU_CORE
PU901
ISL62771HRTZ
+APU_CORE_NB
SPOK
PQ204
TP0610K
+VSB
Issued Date
Compal Secret Data

Title
Deciphered Date

Power Map
Custom
Date:
Rev
1.0
VAWGA/GB
Sheet
E
47
of
48
+5VALW
+3VALW / +1.8VALW / +1.5VALW / +0.95VALW

+3VS / +1.8VS / +1.5VS / +0.95VS
+3VALW
+APU_CORE / +APU_CORE_NB
3B
17
LPC_RST#
19
PXS_PWREN
13
+3VALW +5VALW
V
U1895V
+0.95VGS
LAN_PERST#
U315V
+3VGS
21
+1.5V +5VALW
V
V
+5VALW
U315V
+1.5VGS
+0.95VALW +5VALW
B+
PU501
+0.75VS
V
4
LAN
+3VALW
Issued Date
+3VS +5VALW
U1895P
+1.8VS
COMPAL CONFIDENTIAL
D4
Diode
+1.8VALW +5VALW
+1.5V
MODEL NAME:
PCB NAME:
REVISION:
DATE: 2011/11/23
WLAN / WiMAX
Mini-Express Card
+3V_LAN
+0.95VALW +5VALW
U35P
+5VS
U35P
+3VS
Q20
+1.5VS
PU801
+VGA_CORE
BATT+
PU301
B+
+1.8VALW +5VALW
B+
PU102
+RTCBATT
11
+1.5VA
+5VS +3VS
+5VALW
+5VALW
PU501
+1.5V
VGA_PEWGD
+3VS
U1895V
+1.8VGS
SUSP#
SYSON
VGATE
+3VALW
VIN
14
GPU
MarsXTX
V
V
PU901
+APU_CORE /
+APU_CORE_NB
+CHGRTC_R +3VLP
APU_PWRGD
GPU_RST#
16
RTC Battery
+CHGRTC_R
B
18
12
095VS_PWR_EN
15
APU_PCIE_RST#
VR_ON
20
B+
18
23
AND
GATE
V
EC_VGA_EN
+5VS / +3VS / +1.8VS
BATT MODE
BATT+
PXS_RST#
B+
V V
ON/OFF
APU_PWRGD
10
SYS_PWRGD_EC
EC_ON
1B
AC MODE
VIN
22
2B
ACIN
+5VALW
APU
3B
4A
KBRST#
1A
SLP_S3# / SLP_S5#
SPOK
PU401
+3VALW/+3VLP
2A
+VGA_CORE
+3VGS
3A
PU402
+5VALW / VL
PBTN_OUT#
+1.8VGS / +0.95VGS
V V
4A
B+
V V
095_18ALW_PWR_EN
EC_RSMRST#
V V
EC
3B
3A
B+
+3VGS / +1.5VGS
+RTCBATT
PU601
+0.95VALW
+3VLP
B+
PU502
+1.8VALW
V V
+3VALW
U1895P
+0.95VS
Compal Secret Data

Title
Deciphered Date

Power sequence
Rev
1.0
Date:
Sheet
1
of

LA-9911P Lenovo IdeaPad G505

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LA-9911P Lenovo IdeaPad G505

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A

AMD "Kabini" Platform

LA-9911P REV: 1.0

Compal Electronics, Inc.

Compal Secret Data

1.5V DDRIII 1600MHz

AMD Sun Pro M2

Int. Speaker Conn.

Audio Combo Jacks

Compal Electronics, Inc.

Compal Secret Data

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for APU

Voltage for On-die VGA of APU

0.95-1.2V switched power rail

0.95-1.2V switched power rail

3.3V always on power rail

3.3V switched power rail

1.8V always on power rail

1.8V switched power rail

0.95V always on power rail

0.95V switched power rail

1.5V power rail for APU and DDR

1.5V switched power rail

3.3V switched power rail for VGA

1.8V switched power rail for VGA

1.5V switched power rail for VGA

0.95V switched power rail for VGA

5V always on power rail

5V switched power rail

VSB always on power rail

0.75V switched power rail for DDR terminator

SMBUS Control Table

Board ID / SKU ID Table for AD channel

VGA Internal Thermal

USB 2.0 USB 3.0

for 15" componect

EMI Un pop component

Compal Electronics, Inc.

Compal Secret Data

BOM Structure Table

APU PCIE PORT LIST

FT3 REV 0.51

A4 PR KABINI AM5000IBJ44HM 1.5G BGA 769P APU

E1 PC 2M101082J2361 1G BGA 769P

For HDMI Need

RP11, RP6 will @ when MP

Compal Electronics, Inc.

Compal Secret Data

E2 PR KABINI EM3000IBJ23HM 1.65G BGA 769P APU

FT3 REV 0.51

A6 PR KABINI AM5200IAJ44HM 2G BGA769P APU

E1 PR KABINI EM2100ICJ23HM 1G BGA769P APU

X2 ES2 KABINI ZMA5B078J2360 1.65G BGA CPU

X5 ES2 ZM201079J4460 2G BGA 769P

HDMI & LVDS should be reverse in KABINI:

Monday, April 01, 2013

APU POWER SEQUENCE

FT3 REV 0.51

R103 R104 for EMI

APU->EC->ROM must route as

Compal Electronics, Inc.

Compal Secret Data