library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;

architecture Behavioral of full_adder is

component and_gate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);

end component;
component xor_gate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component or_gate is
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
r : in STD_LOGIC;
s : out STD_LOGIC);
end component;

signal s1,t1,t2,t3 : STD_LOGIC;

begin

xor_1 : xor_gate port map(a,b,s1);

xor_2 : xor_gate port map(s1,c,s);

and_1 : and_gate port map(a,b,t1);

and_2 : and_gate port map(a,c,t2);
and_3 : and_gate port map(c,b,t3);

or_1 : or_gate port map(t1,t2,t3,cout);

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity and_gate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end and_gate;

architecture Behavioral of and_gate is

begin

z <= x and y;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xor_gate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end xor_gate;

architecture Behavioral of xor_gate is

begin

z <= x xor y;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity or_gate is
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
r : in STD_LOGIC;
s : out STD_LOGIC);
end or_gate;

architecture Behavioral of or_gate is

begin

s <= p or q or r;

end Behavioral;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 25 ns;
a <= not a;
wait for 25 ns;
b <= not b;
wait for 25 ns;
c <= not c;

end process;

END;