Chapter 6

(Synchronous)
Sequential Circuits
J.J. Shann

Contents
6-1
6-2
6-3
6-6
6-4
6-5
6-7

Sequential Circuit Definitions

Latches
Flip-Flops
Other Flip-Flop Types
Sequential Circuit Analysis
Sequential Circuit Design
HDL Representation for Sequential Circuits
VHDL ()
6-8 HDL Representation for Sequential Circuits
Verilog ()
6-9 Chapter Summary
J.J. Shann 6-2

6-1 Sequential Circuit Definitions

Combinational circuit: no memory elements

(inputs) (outputs)

Sequential circuit:

storage elements: devices capable of storing binary

information (state)
(inputs, present state) (outputs, next state)
J.J. Shann 6-3

Logic structures for storing information:

E.g.s:

J.J. Shann 6-4

Types of Sequential Circuits

Classification:

depends on the timing of their signals.

Two main types:

1. Synchronous seq ckt:

Its behavior can be defined from the knowledge of its signals

at discrete instants of time.
Storage elements: e.g., flip-flops

2. Asynchronous seq ckt: ()

Its behavior depends upon the input signals at any instant of

time and the order in which the inputs change.
Storage elements: e.g., latches, feedback paths
Disadv.: may be unstable & difficult to design
J.J. Shann 6-5

Synchronous Sequential Circuits

Clocked seq ckts: most commonly used sync seq ckts

is syn seq ckts that use clock pulses in the inputs of storage elements
has a master-clock generator to generate a periodic train of clock
pulses
The clock pulses are distributed throughout the system.
Storage elements are affected only w/ the arrival of each pulse.

Adv.: seldom manifest instability problems

Storage elements: flip-flops
flip-flop: a binary cell capable of storing one bit of information
The state of a flip-flop can change only during a clock pulse transition.

The transition from one state to the next occurs only at

predetermined time intervals dictated by the clock pulses.

J.J. Shann 6-6

Block diagram of a sequential ckt:

(Optional)

Flip-flops

Clock pulses

J.J. Shann 6-7

6-2 Latches

Latches:

are asynchronous seq ckts

are the basic ckts from which all flip-flops are
constructed

J.J. Shann 6-8

A. SR and SR Latches

SR latch
SR latch
SR latch w/ control input

J.J. Shann 6-9

SR Latch

Q: the normal output

Q: the complement output

SR latch: w/ NOR gates

Async
Seq Ckt

Useful states:

Q+

N o ch a n g e (Q + = Q )

Set state: Q = 1, Q = 0

R eset (Q + = 0 )

Reset state: Q = 0, Q = 1

S et (Q + = 1 )

In d eterm in a te

Undefined states: Q = Q

Q + : n ex t sta te o f Q

J.J. Shann 6-10

(Case 1)

0 0

0
0

S R

Q Q

Q+ Q+

0 0

0 1
1 0

0
1

1 9
0 9

0 1

0 1
1 0

0
0

1
1

1 0

0 1
1 0

1
1

0
0

1 1

0 1
1 0

0
0

0
0

S R

1 1

Q+

No change (Q+ = Q)

Reset (Q+ = 0)

Set (Q+ = 1)

Indeterminate

Q+: next state of Q

J.J. Shann 6-11

(Case 2)
1

0 0

0
0

S R

Q Q

Q+ Q+

0 0

0 1
1 0

0
1

1
0

0 1

0 1
1 0

0
0

1 9
1

1 0

0 1
1 0

1
1

0
0 9

1 1

0 1
1 0

0
0

0
0

S R

1 1

Q+

No change (Q+ = Q)

Reset (Q+ = 0)

Set (Q+ = 1)

Indeterminate

Q+: next state of Q

J.J. Shann 6-12

(Case 3)

1 0 0 0

0 0 1

1 0 0
0

S R

Q Q

Q+ Q+

0 0

0 1
1 0

0
1

1
0

0 1

0 1
1 0

0
0

1
1 9

1 0

0 1
1 0

1
1

0 9
0

1 1

0 1
1 0

0
0

0
0

S R

0 0 1 1

Q+

No change (Q+ = Q)

Reset (Q+ = 0)

Set (Q+ = 1)

Indeterminate

Q+: next state of Q

J.J. Shann 6-13

(Case 4)

0 0 0

1 0

0 0
1

1 0 0

S R

Q Q

Q+ Q+

0 0

0 1
1 0

0
1

1
0

0 1

0 1
1 0

0
0

1
1

1 0

0 1
1 0

1
1

0
0

1 1

0 1
1 0

0
0

0
0

Q+

N o ch a n g e (Q + = Q )

R eset (Q + = 0 )

S et (Q + = 1 )

In d eterm in a te

Q + : n ex t sta te o f Q

J.J. Shann 6-14

(Case 4+)

0 1 0

0 1

0 1
0

S R

Q Q

Q+ Q+

0 0

0 1
1 0

0
1

1
0

0 1

0 1
1 0

0
0

1
1

1 0

0 1
1 0

1
1

0
0

1 1

0 1
1 0

0
0

0
0

S R

0 1 0

Q+

No change (Q+ = Q)

Reset (Q+ = 0)

Set (Q+ = 1)

Indeterminate

Q+: next state of Q

J.J. Shann 6-15

Summary:

S R

Q Q

Q+ Q+

0 0

0 1
1 0

0
1

1
0

0 1

0 1
1 0

0
0

1
1

1 0

0 1
1 0

1
1

0
0

1 1

0 1
1 0

0
0

0
0

S R

Q = ( R + Q )
+

Q + = ( S + Q)

Q+

No change (Q+ = Q)

Reset (Q+ = 0)

Set (Q+ = 1)

Indeterminate

Q+: next state of Q

J.J. Shann 6-16

Logic simulation of SR latch behavior

S

Q+

N o ch a n g e (Q + = Q )

R eset (Q + = 0 )

S et (Q + = 1 )

In d eterm in a te

Q + : n ex t sta te o f Q

J.J. Shann 6-17

S R Latch

S R latch: w/ NAND gates

Q+

N o ch a n g e (Q + = Q )

R eset (Q + = 0 )

S et (Q + = 1 )

In d eter m in a te

J.J. Shann 6-18

S R

Q Q

Q+ Q+

1 1

0 1
1 0

0
1

1
0

0 1

0 1
1 0

0
0

1
1

1 0

0 1
1 0

1
1

0
0

0 0

0 1
1 0

1
1

1
1

Q+

Q + = ( S Q )

N o ch a n g e (Q + = Q )

R eset (Q + = 0 )

Q = ( R Q)

S et (Q + = 1 )

In d eter m in a te

J.J. Shann 6-19

SR Latch w/ Control Input

SR latch w/ control input:

enable signal

S = R =1

The indeterminate condition makes this ckt difficult to

manage & it is seldom used in practice.
It is an important ckt (other latches & flip-flops are
constructed from it)
J.J. Shann 6-20

B. D Latch

D latch
D latch w/ transmission gates

J.J. Shann 6-21

D Latch

D latch (w/ control input):

C D

C S R

Q+

0 X

0 X X

1 0

1 0 1 0 (Reset)

1 1

1 1 0 1 (Set)

Q (No change)

Disadv. of a latch w/ control input:

The state of latch may keep changing for as long as the

control input stays in the active level.
J.J. Shann 6-22

D latch w/ transmission gates:

J.J. Shann 6-23

D latch w/ transmission gates:

1
D

J.J. Shann 6-24

D latch w/ transmission gates:

0
D+

J.J. Shann 6-25

6-3 Flip-Flops

Flip-flop vs. Latch:

Latch w/ control input:

can change state in response to the inputs anytime the control

input is in the active level.

The latch is controlled by the level of its control input.

Flip-flop:
responses only to a transition of a triggering input called the

clock.
Positive-edge trigger: 0 1
Negative-edge trigger: 1 0

J.J. Shann 6-26

Clock response in latch & flip-flop:

J.J. Shann 6-27

Latch Flip-flop:
1. Master-slave flip-flop: pulse-triggered f-f
Employ two latches in a special configuration that
isolates the output of the flip-flop from being affected
while its input is changing.
2. Edge-triggered flip-flop:
Produce a flip-flop that triggers only during a signal
transition, and is disabled during the rest of the clock
pulse duration.

J.J. Shann 6-28

A. Master-Slave Flip-Flops

SR master-slave flip-flop:

Master enabled, goes

to state determined by
S & R inputs
Slave disable

Master disable

* Q may change
only during the
negative edge
of the clock.

Slave enabled, goes

to state determined by
output of master (Y)
Slave disable

J.J. Shann 6-29

Logic simulation of
an SR master-slave
flip-flop:

J.J. Shann 6-30

Master-slave D f-f

Negative
edge-triggered
D flip-flop

Positive
edge-triggered
D flip-flop

J.J. Shann 6-31

B. Edge-Triggered Flip-Flop

Master-slave f-f Edge-triggered f-f

Negative
edge-triggered
D flip-flop

Positive
edge-triggered
D flip-flop

J.J. Shann 6-32

D-Type Positive-Edge-Triggered
Flip-Flop (p.6-27~6-32)
S

J.J. Shann 6-33

When clock is LOW:

1
No change

0
1

J.J. Shann 6-34

When clock is LOW:

D
1
0

No change
1

J.J. Shann 6-35

When clock goes LOW-to-HIGH: data is latched

D
D
D

D
D

J.J. Shann 6-36

When clock is HIGH: data is held

D
D
D

D
D

J.J. Shann 6-37

Timing

Setup time: G1 + G4

Hold time: max(G2, G3)

the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of
the clock transition
the minimum time for which the D input must not change
after the application of the positive transition of the clock

Propagation delay time:

the time interval b/t the trigger edge and the stabilization
of the output to a new state
J.J. Shann 6-38

Setup time: G1 + G4

the minimum time for which the D input must be

maintained at a constant value prior to the occurrence of
the clock transition

D
D

D
J.J. Shann 6-39

Hold time: max(G2, G3)

the minimum time for which the D input must not change
after the application of the positive transition of the clock

D
D

J.J. Shann 6-40

Propagation delay time:

the time interval b/t the trigger edge and the stabilization
of the output to a new state

D
D

D
D

J.J. Shann 6-41

C. Flip-Flop Timing

Clock pulse
width, tw
Setup time, ts
Hold time, th
Propagation
delay times,
tPHL, tPLH, tpd

J.J. Shann 6-42

D. Standard Graphics Symbols

* Assumption:
All flip-flops are of the positiveedge-triggered type, unless
otherwise indicated.
J.J. Shann 6-43

E. Direct Inputs

Direct inputs: asynchronous inputs

are used to force the flip-flop to a particular state

independent of the clock.
When power is turned on in a digital system, the state of the flip-

flops is unknown.
The direct inputs are useful for bringing all flip-flops in the
system to a known starting state prior to the clocked operation.

Types of direct inputs:

Preset: direct set, sets the f-f to 1
Clear: direct reset, sets the f-f to 0

J.J. Shann 6-44

0
1

E.g.: ()
D flip-flop w/
asynchronous
reset

*
*

1
*

* Active LOW

J.J. Shann 6-45

E.g.: D f-f w/ direct set and reset

direct set
(active LOW)

direct reset
(active LOW)
J.J. Shann 6-46

6-6 Other Flip-Flop Types

JK flip-flop
T flip-flop

J.J. Shann 6-47

J-K Flip-Flop

SR flip-flop

JK flip-flop

S
0

R
0

Q+
Q

J
0

K
0

Q+
Q

0
1
1

1
0
1

0
1
Indeterminate

0
1
1

1
0
1

0
1
Q

J.J. Shann 6-48

JK flip-flop

Q+

J
0

K
0

Q+
Q

0
1
1

1
0
1

0
1

Q+ = JQ + KQ
J.J. Shann 6-49

JK flip-flop (Contd) Verification

Q+ = JQ + KQ
D = Q+ =JQ + KQ

Q+

0
0
1
1

0
1
0
1

Q
0
1

Q
0
1

J.J. Shann 6-50

T Flip-Flop

J
0
0
1
1

K
0
1
0
1

Q+
Q
0
1
Q

Q+ = JQ + KQ

J=K

T
0
1

Q+
Q

From D flip-flop:
Q+ = D = TQ + TQ

Q+ = TQ + TQ
J.J. Shann 6-51

Flip-Flop Logic, Characteristic Tables &

Equations, and Excitation Tables

J.J. Shann 6-52

6-4 (Sync) Sequential Circuit Analysis

Synchronous seq ckt:

(optional)

includes f-fs w/ the clock inputs driven directly or

indirectly by a clock signal and the direct sets and resets
are unused during the normal functioning of the ckt
The behavior of a seq ckt is determined from the inputs,
outputs, and present state of the ckt.

Analysis of a seq ckt:

obtain a suitable description that demonstrates the time

sequence of inputs, outputs, and states
J.J. Shann 6-53

(1)
(1)
(2)

Analysis procedure:
Flip-Flop Characteristic Equation
1

Circuit
(sync seq)

Flip-flop
input
Equations
Output
equations

Next
state
equations

State
table
(Transition
table)

State
diagram

J.J. Shann 6-54

A. Analysis w/ D Flip-Flops

E.g. 1:

J.J. Shann 6-55

<Analysis>
1. Flip-flop input equations & Output equations:
DA = AX + BX
DB = AX

Y = (A + B) X

2. Next state equation:

(Q+ = D)
A(t + 1) = DA = AX + BX

B(t + 1) = DB = A X

comb. ckt.
J.J. Shann 6-56

3. State table:
Next state equations:

A(t + 1) = AX + BX
B(t + 1) = A X

Output equations:

Y = AX + B X

J.J. Shann 6-57

(One-dimensional)
State table

Two-dimensional
state table

J.J. Shann 6-58

input/output
X/Y

4. State diagram:

J.J. Shann 6-59

E.g. 2:

1. Flip-Flop input equations & Output equations:

DA = AXY
Z=A
2. Next-state equation:
A+ = DA = AXY
J.J. Shann 6-60

3. State table:

A+ = A X Y
Z=A

4. State diagram:

A/Z
state/output

J.J. Shann 6-61

Analysis w/ JK Flip-Flops
Flip-Flop Characteristic Equation
1

Circuit
(sync seq)

Flip-flop
input
Equations

Next
state
equations

State
table
(Transition
table)

State
diagram

Output
equations

J.J. Shann 6-62

Example:

J.J. Shann 6-63

1. Flip-flop input equations

& Output equations:
JA = B
KA = B x
JB = x
KB = A x + A x
=Ax

2. Next state equations:

(Q+ = J Q + K Q)
A+ = JA A + KA A = A B + A B + A x
B+ = JB B + KB B = B x + A B x + A B x
J.J. Shann 6-64

3. State table:
A+ = A B + A B + A x
B+ = B x + A B x + A B x

J.J. Shann 6-65

4. State diagram

J.J. Shann 6-66

 Analysis w/ T Flip-Flops
Flip-Flop Characteristic Equation
1

Circuit
(sync seq)

Flip-flop
input
Equations

Next
state
equations

State
table
(Transition
table)

State
diagram

Output
equations

J.J. Shann 6-67

Example:

J.J. Shann 6-68

1. Flip-flop input equations

& Output equations:
TA = B x
TB = x
y = AB

2. Next state equations:

(Q+ = T Q + T Q)
A+ =
=
B+ =
=

TA A + TA A
A B + A x + A B x
TB B + TB B
xB
J.J. Shann 6-69

3. State table:
A+ = A B + A x + A B x
B+ = x B
y = AB

J.J. Shann 6-70

4. State diagram

J.J. Shann 6-71

B. Mealy Model vs. Moore Model

Mealy model:

is a model of seq ckts in which the outputs depend on

both the inputs and the present states.
Xi
Inputs

Combinational
Logic for
Outputs and
Next State

State Register

Zk
Outputs

Clock

State
Feedback

E.g. 1:
J.J. Shann 6-72

Xi
Inputs

State Register

Zk
Outputs

Combinational
Logic for
Outputs and
Next State

Clock

State
Feedback

E.g. 1:

J.J. Shann 6-73

Moore model:

is a model of seq ckts in which the outputs depend only

on the present states.
State
Register
Xi
Inputs

Comb.
Logic for
Outputs

Combinational
Logic for
Next State
(Flip-flop
Inputs)

Zk
Outputs
Clock

state
feedback

E.g. 2:
J.J. Shann 6-74

State
Register
Xi
Inputs

Comb.
Logic for
Outputs

Combinational
Logic for
Next State
(Flip-flop
Inputs)

Zk
Outputs
Clock

E.g. 2:

state
feedback

J.J. Shann 6-75

Comparison:

Moore model:
The outputs of the ckt are synchronized w/ the clock.

( the outputs depend on only flip-flop outputs that are

synchronized w/ the clock)

Mealy model:
The outputs may change if the inputs change during the clock

cycle.

J.J. Shann 6-76

C. Sequential Circuit Timing

Analysis of a seq ckt:

analyze the function of the ckt

analyze the performance of the ckt
max input-to-output delay
the max clock frequency, fmax , at which the ckt can operate

clock frequency f = 1/tp , tp: the clock period

fmax = 1/tp-min , tp-min: the min allowable clock period

J.J. Shann 6-77

Sequential Circuit Timing Parameters

Sequential ckt timing parameters:

i. f-f propagation delay: tpd,FF
ii. comb logic delay through the chain of gates along the
path: tpd,COMB
iii. f-f setup time: ts
(iv. slack time, tslack : the extra time allowed in the clock
period beyond that required by the path)

J.J. Shann 6-78

For edge-triggered flip-flops:

determine the longest delay from the triggering edge of

the clock to the next triggering edge of the clock.

J.J. Shann 6-79

For pulse-triggered flip-flops:

J.J. Shann 6-80

Sequential Circuit Timing Paths

Sequential ckt timing paths:

ti: the latest time

that the input
changes after
the positive
clock edge
to: the latest time
that the output
is permitted to
change prior to
the next clock
edge

J.J. Shann 6-81

Propagation delay for a path of type PFF,FF:

t p = tslack + (tpd,FF + t pd,COMB + ts )

t p max (t pd,FF + t pd,COMB + ts ) = t p,min

J.J. Shann 6-82

Example 6-1: Clock Period and Frequency

Calculations

Example 6-1:
Suppose that all f-fs used are the same and have tpd = 0.2 ns
and ts = 0.1 ns. Then the longest path beginning and
ending w/ a f-f will be the path w/ the largest tpd,COMB.
Further, suppose that the largest tpd,COMB is 1.3 ns and that
tp has been set to 1.5 ns.
<Ans.>

t p = tslack + (t pd,FF + t pd,COMB + ts )

1.5 ns = tslack + 0.2 + 1.3 + 0.1 = tslack + 1.6 ns
tslack = 0.1 ns (contradiction w/ tslack 0)
tp is too small
t p t p, min = 1.6 ns

f max = 1 / 1.6 ns = 625 MHZ

J.J. Shann 6-83

Discussion

If tp is too large to meet the ckt specifications:

employ faster logic cells or

change the ckt design to reduce the problematic path
delays through the ckt

Hold time: th

does not appear in the clock period

equation.
relates to another timing constraint
equation dealing w/ one or both of 2
specific situations:
output changes arrive at the inputs of one or more f-fs too soon
the clock signals reaching one or more f-f are somehow delayed

(clock skew)

J.J. Shann 6-84

D. Simulation

Sequential ckt simulation:

Function simulation

The input patterns must be applied in a sequence.

There must be some means to place the ckt in a known state.
Observe the state to verify correctness.
Deal with the timing of application of inputs and observation of
outputs relative to the active clock edge.
Objective: determination or verification of the function of the ckt
Assumption: Ckt components has no delay or a very small delay.

Timing simulation

Objective: verification of the proper op of the ckt in terms of timing

Ckt components has realistic delays.

J.J. Shann 6-85

Simulation timing:

J.J. Shann 6-86

6-5 (Sync) Sequential Circuit Design

Design procedure:
1. Specification: Write a specification for the ckt.
2. Formulation: Obtain either a state diagram or state
table from the statement of the problem.
* State reduction: Reduce the # of states if necessary.
3. State assignment: Assign binary codes to the states
and obtain the binary-coded state table.
4. Flip-flop input equation determination: Select the
flip-flop type or types. Derive the flip-flop input
equations from the next-state entries in the encoded
state table.
5. Output equation determination: Derive output
equations from the output entries in the state table.
J.J. Shann 6-87

6. Optimization: Optimize the flip-flop input

equations and output equations.
7. Technology mapping: Draw a logic diagram of the
ckt using flip-flops, ANDs, ORs, and inverters.
Transform the logic diagram to a new diagram
using the available flip-flop and gate technology.
8. Verification: Verify the correctness of the final
design.

J.J. Shann 6-88

A.
State
diagram
Functional
description

B.
State
table

Minimal
state
table

C.
State
assignment

D.
Binary-coded
state
table

Flip-Flop
input
equations
&
Output
equations

E.
Circuit

F.
Verify
(Used/Unused
states)

J.J. Shann 6-89

A. Finding State Diagrams and State Tables

J.J. Shann 6-90

Initial State

Initial state:

Async and sync reset for D flip-flops

J.J. Shann 6-91

Example 6-2

E.g.: Sequence recognizer of 1101

Problem description:
Recognize the occurrence of the sequence of bits 1101 on input

X by making output Z equal to 1 when the previous three inputs

to the circuit were 110 and current input is a 1, regardless of
where it occurs in a sequence. Otherwise, Z equals 0.
The circuit has direct resets on its flip-flops to initialize the state
of the circuit to all zeros.

1101
Seq Recognizer

J.J. Shann 6-92

1101
Seq Recognizer

State diagram:

1/0

0/0

1/0
A

Init

1/0

1/0

0/0

11

0/0

110
0/0

1/1

1101
0/0

X/Z

State B = State E
J.J. Shann 6-93

State diagram: (contd)

J.J. Shann 6-94

State table:

J.J. Shann 6-95

Example

E.g.: Sequence detector of three or more

consecutive 1s
Design a ckt that detects three or more consecutive 1s in
a string of bits coming through an input line.
<Ans>
State table:
State diagram
Present
state
S0
S0
S1
S1
S2
S2
S3
S3

Input
x
0
1
0
1
0
1
0
1

Next
state

Output
y

S0
S1
S0
S2
S0
S3
S0
SJ.J.
3 Shann

0
0
0
0
0
0
1
1
6-96

Example 6-3

BCD-to-excess-3
decoder

E.g.: Finding a state diagram for a BCD-to-excess-3

decoder

Formulation: Sequence tables for code converter

LSB

MSB

LSB

MSB

B1 B2 B3 B4

0
1
2
3
4
5
6
7
8
9

J.J. Shann 6-97

B1 B2 B3 B4

State diagram:

J.J. Shann 6-98

B1 B2 B3 B4

State diagram:
Init

0/1

1/0

B1=0

0/0
B3=0

0/0

B1=1

0/1

1/0

0/0

1/1

B2=0

B2=1

B2=0

B2=1

1/1 0/1
B3=1

1/1 0/0

B3=0

0/0

1/0

0/1

B3=1

B3=0

0/1 0/0

1/0
B3=1

1/1

0/1

0/1

1/0

B3=0

B3=1

0/0

0/1

Init
J.J. Shann 6-99

State diagram: (contd)

J.J. Shann 6-100

B. State Reduction Minimal State Table

()

J.J. Shann 6-101

B. State Reduction Minimal

State Table ()

State reduction:

Implement a seq ckt with fewest possible states

Least number of flip-flops
Boundaries are power of two number of states

Fewest states usually leads to more opportunities for

don't cares
Reduce the number of gates needed for implementation

Goal:

Identify and combine states that have equivalent

behavior
Equivalent States: for all input combinations,
states transition to the same or equivalent states &
outputs are the same or compatible
J.J. Shann 6-102

State Reduction Methods

State reduction methods:

Row matching method

Implication chart method

J.J. Shann 6-103

(a) Row Matching Method

Row matching method

Identify states w/ same output behavior

If such states transition to the same next state, they are
equivalent
Combine into a single new renamed state
Repeat until no new states are combined
Adv.: Straightforward to understand and easy to
implement
Problem: does not allows yield the most reduced state
table!

J.J. Shann 6-104

E.g.: 3-bit sequence detector

Single input X, Single output Z.

Output a 1 whenever the serial sequence 010 or 110 has
been observed at the inputs.

<Ans.>
State diagram:

0/0

S0

0/0

1/0

S1

S2

0/0

1/0

0/0

1/0

S3

S4

S5

S6

1/0 0/1

1/0

0/0
S0

1/0

0/1

1/0

J.J. Shann 6-105

State table:
Input Sequence
Reset
0
1
00
01
10
11

Next State
Present State X=0 X =1
S0
S2
S1
S1
S3
S4
S2
S5
S6
S3
S0
S0
S4
S0
S0
S5
S0
S0
S6
S0
S0

Reduced state table:

Input Sequence
Reset
0 or 1
(S1, S2)
(S3, S5) 00 or 10
(S4, S6) 01 or 11

Next State
Present State X =0 X =1
S1'
S'1
S0
S1'
S3'
S'4
S3'
S0
S0
S4'
S0
S0

Output
X =0 X=1
0
0
0
0
0
0
0
0
0
1
0
0
0
1

Output
X =0 X =1
0
0
0
0
0
0
1
0
J.J. Shann 6-106

Input Sequence
Reset
(S1, S2)
0 or 1
(S3, S5) 00 or 10
(S4, S6) 01 or 11

Next State
Present State X =0 X =1
S1'
S'1
S0
S1'
S3'
S'4
S3'
S0
S0
S4'
S0
S0

Output
X =0 X =1
0
0
0
0
0
0
1
0

S0
0,1/0
S1 = S2
0/0

1/0

S3 = S5
0/0

S4 = S6

1/0 0/1

1/0

S0
J.J. Shann 6-107

E.g.: 3-state odd parity checker

Next State
Present State X=0 X=1 Output
S0 S1
S0
0
1
S1
S1 S2
0
S2
S2 S1
No
Noway
wayto
tocombine
combinestates
statesS0
S0and
andS2
S2
based
basedon
onNext
NextState
StateCriterion!
Criterion!

J.J. Shann 6-108

(b) Implication Chart Method

Enumerate all possible combinations of states

taken two at a time.

Next States
Under all
Input
Combinations

S0
S1

S1

S2

S2

S3

S3

S4

S4

S5

S5

S6

S6
S0

S1

S2

S3

S4

S5

S6

Naive Data Structure:

xij will be the same as xji
Also, can eliminate the diagonal

S0

S1

S2

S3

S4

S5

Implication Chart
J.J. Shann 6-109

Filling in the implication chart:

xij : Row is Si, Column is Sj

Si is equivalent to Sj if outputs are the same and next
states are equivalent Entry
If Si & Sj have different output behavior, then xij is crossed out.
xij contains the next states of Si & Sj which must be equivalent if

Si and Sj are equivalent

Eg.:
S0 transitions to S1 on 0, S2 on 1;
S1 transitions to S3 on 0, S4 on 1;
S1

S1-S3
S2-S4
S0
J.J. Shann 6-110

E.g.: 3-bit sequence detector

Single input X, Single output Z.
Output a 1 whenever the serial sequence 010 or 110 has
been observed at the inputs.

<Ans.>
State table:
Input Sequence
Reset
0
1
00
01
10
11

Next State
Present State X=0 X =1
S0
S2
S1
S1
S3
S4
S2
S5
S6
S3
S0
S0
S4
S0
S0
S5
S0
S0
S6
S0
S0

Output
X =0 X=1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
J.J. Shann 6-111

Starting

Present State
Input Sequence
S0
Reset
S1
0
S2
1
S3
00
S4
01
S5
10
S6
11
implication chart:

Next State
X=0 X =1
S1
S2
S3
S4
S5
S6
S0
S0
S0
S0
S0
S0
S0
S0

Output
X =0 X=1
0
0
0
0
0
0
0
0
1
0
0
0
1
0

S2 and S4
have different
I/O behavior

S1

S1-S3
S2-S4

S2

S1-S5 S3-S5
S2-S6 S4-S6

S3

S1-S0 S3-S0 S5-S0

S2-S0 S4-S0 S6-S0

S1 and S0 cannot
be combined

S4
S5

S1-S0 S3-S0 S5-S0 S0-S0

S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S0-S0

S6
S0

S1

S2

S3

S4

S5
J.J. Shann 6-112

1st marking pass:

S1

S1-S3
S2-S4

S1

S2

S1-S5 S3-S5
S2-S6 S4-S6

S2

S3

S1-S0 S3-S0 S5-S0

S2-S0 S4-S0 S6-S0

S3
S4

S4
S5

S3-S5
S4-S6

S1-S0 S3-S0 S5-S0 S0-S0

S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S0-S0

S6
S0

S1

S2

S3

S0-S0
S0-S0

S5

S4

S0-S0
S0-S0

S6
S5

S0

S1

S2

S3

S4

S5

J.J. Shann 6-113

S1

2nd Pass: adds no new information

S3-S5
S4-S6

S2
S3

S4 and S6 are equivalent

S3 and S5 are equivalent
S1 and S2 are too!

S4
S0-S0
S0-S0

S5

S0-S0
S0-S0

S6
S0

S1

S2

S3

S4

S5

Reduced state table:

Input Sequence
Reset
(S1, S2)
0 or 1
00 or 10
(S3, S5)
01 or 11
(S4, S6)

Next State
Present State X =0 X =1
S1'
S0
S'1
S1'
S3'
S'4
S3'
S0
S0
S4'
S0
S0

Output
X =0 X =1
0
0
0
0
0
0
1
0
J.J. Shann 6-114

E.g.: 3-state odd parity checker

Present State
S0
S1
S2

Next State
X =0 X =1
S1
S0
S1
S2
S2
S1

Output
0
1
0

No
Noway
wayto
tocombine
combinestates
statesS0
S0and
andS2
S2
based
basedon
onRow
Rowmatching
matchingmethod!
method!

Implication
ImplicationChart
Chart

S1
S2 S0 -S2
S1 -S1

S0 is equivalent to S2
since nothing contradicts this assertion!

S0

S1
J.J. Shann 6-115

Multiple Input State Diagram Example

E.g.: Multiple Input State Diagram Example

00

10
00

S0
[1]

S1
[0]

01
11

10

01

00

S2
[1]

01

00

S3
[0]

01
10

10

11

11

10
00

01

S4
[1]

11

00

10
11
01

Present
State
S0
S1
S2
S3
S4
S5

00
S0
S0
S1
S1
S0
S1

Next State
01 10
S1 S2
S3 S1
S3 S2
S0 S4
S1 S2
S4 S0

Output
11
S3
S5
S4
S5
S5
S5

1
0
1
0
1
0

Symbolic State Table

S5
[0]
11

State Diagram
J.J. Shann 6-116

Present
State
S0
S1
S2
S3
S4
S5

S1

S2

S0-S1
S1-S3
S2-S2
S3-S4

S4

Symbolic State Diagram

S0-S1
S3-S0
S1-S4
S5-S5

S3
S0-S0
S1-S1
S2-S2
S3-S5

S0

Present
State
S'0
S1
S2
S'3

S1-S0
S3-S1
S2-S2
S4-S5
S0-S1
S3-S4
S1-S0
S5-S5

S5

00
S0
S0
S1
S1
S0
S1

Next State
Output
01 10 11
S1 S2 S3
1
S3 S1 S5
0
S3 S2 S4
1
S0 S4 S5
0
S1 S2 S5
1
S4 S0 S5
0

S1

S1-S1
S0-S4
S4-S0
S5-S5
S2

S3

Next State
00 01 10
S0' S1 S2
S0' S3' S1
S1 S3' S2
S1 S'0 S'0

Output
11
S3'
S3'
S0'
S'3

1
0
1
0

Minimized State Table

S4

Implication Chart
J.J. Shann 6-117

Detailed Algorithm of Imp. Chart Method

1. Construct implication chart, one square for each
combination of states taken two at a time.
2. Square labeled (Si, Sj). If outputs differ then square gets
"". Otherwise write down implied state pairs for all
input combinations
3. Advance through chart top-to-bottom and left-to-right.
If square (Si, Sj) contains next state pair Sm, Sn and that
pair labels a square already labeled " ", then (Si, Sj) is
labeled " ".
4. Continue executing Step 3 until no new squares are
marked with " ".
5. For each remaining unmarked square (Si, Sj), then Si and
Sj are equivalent.
J.J. Shann 6-118

C. State Assignment ()

J.J. Shann 6-119

State Assignment

When a seq ckt implemented w/ gate logic, # gates will

depend on mapping b/t symbolic state names and binary
encodings.
E.g.: 4 states HG, HY, FG, FY
4 states 4 choices for first state, 3 for second, 2 for third, 1 for last
= 24 different encodings (4!)
HG
00
00
00
00
00
00
01
01
01
01
01
01

HY
01
01
10
10
11
11
00
00
10
10
11
11

FG
10
11
01
11
01
10
10
11
00
11
00
10

FY
11
10
11
01
10
01
11
10
11
00
10
00

HG
10
10
10
10
10
10
11
11
11
11
11
11

HY
00
00
01
01
11
11
00
00
01
01
10
10

FG
01
11
00
11
00
01
01
10
00
10
00
01

FY
11
01
11
00
01
00
10
01
10
00
01
00

Symbolic State Names:

HG, HY, FG, FY
24 state assignments
for the traffic light
controller

J.J. Shann 6-120

State Map
State Maps: similar in concept to K-maps

S0

S1

Assignment
State Name Q2 Q 1 Q0
S0
0 0 0
1 0 1
S1
1 1 1
S2
0 1 0
S3
0 1 1
S4

S2
S3

Assignment

Assignment
Q1 Q 0
Q 00 01
2

0 S0
1

S4

Assignment
State Name Q2 Q1 Q0
S0
0 0 0
0 0 1
S1
0 1 0
S2
0 1 1
S3
1 1 1
S4

S1

11

10

S4

S3

S2

State Map

Q1 Q 0
Q2 00 01 11 10
0 S0 S1 S3 S2
1

S4
State Map

J.J. Shann 6-121

Guideline for State Assignment

Adjacent assignments:
Heuristics based on input and output behavior & transitions

i.

i/j

i/k

states that share a common next state

(group 1's in next state map)

Highest Priority

ii.

states that share a common ancestor state

(group 1's in next state map)

Medium Priority

iii.

i/j

i/j

Lowest Priority

states that have common output behavior

(group 1's in output map)
J.J. Shann 6-122

Guideline 1: states that share a common next state

(group 1's in next state map)

i/j

E.g.:

i/k

Highest Priority

0/0

A
0/0

1/0
0/0

B
1/0

1/1
0/0

(A, B, D) (A, D) (B, C)

C
1/0
J.J. Shann 6-123

Guideline 2: states that share a common ancestor state

(group 1's in next state map)

E.g.:

Medium Priority

0/0

A
0/0

1/0
0/0

B
1/0

1/1
0/0

(A, B) (A, C) (C, D) (A, B)

(A, B)2; (A, C); (C, D)

1/0
J.J. Shann 6-124

states that have common output behavior

(group 1's in output map)

Guideline 3:

i/j

i/j

E.g.:

Lowest Priority

0/0

A
0/0

1/0
0/0

B
1/0

1/1
0/0

(A, B, C, D) (A, B, C)

C
1/0
J.J. Shann 6-125

E.g.:

State diagram

State table

0/0

A
0/0

Guideline 1: (A, B, D) (A, D) (B, C)

Guideline 2: (A, B)2, (A, C), (C, D)
Guideline 3: (A, B, C, D) (A, B, C)

State Map:
Q1

Q0
0
1

1/0
0/0

B
1/0

1/1
0/0

C
1/0

State Assignment:
A=
B=
C=
D=
J.J. Shann 6-126

State Assignment 1: heuristics

A = 00
B = 01
A B
C = 10
C D
D = 11

State Assignment 2: guidelines

A = 00
B = 01
A B
C = 11
D C
D = 10

Transition Table 1
Q1Q0
00
01
10
11

Q1+ Q0+

00
00
11
00

01
10
10
01

Transition Table 2
Q1Q0
00
01
11
10

Q1+ Q0+

00
00
10
00

01
11
11
01
J.J. Shann 6-127

Transition Table 1: heuristics

Transition Table 2: guidelines

Q1+ Q0+

Q1+ Q0+

Q1Q0
00
01
10
11

00
00
11
00

Q1Q0

01
10
10
01

00
01
11
10

00
00
10
00

01
11
11
01

Q1+

0
0

0 0 1
1 0 1

Q1+

0 0 1 0
0 1 1 0

Q0+

0
1

0 0 1
0 1 0

Q0+

0 0
1 1

0 0
1 1

0 0
0 0

0 0
0 0

0 0
0 1
J.J. Shann

0 0
1 0

6-128

Example: 3-Bit Sequence Detector

Reset

(S3', S4') 2

S0

i/j

i/k

Highest Priority

0,1/0
0,1/0

1/0

S1

0/1,
1/0

0/0

(S3', S4')

Medium Priority

S3
'

S4
'

0/0: (S0, S1', S3')

1/0: (S0, S1', S3', S4')

i/j

i/j

Lowest Priority
J.J. Shann 6-129

Highest Priority:
(S3', S4') 2
Q1

Q0

S0

S3

S1

S4

Medium Priority:
(S3', S4')
Lowest Priority:
0/0: (S0, S1', S3')
1/0: (S0, S1', S3', S4')
Reset State = 00
Highest Priority Adjacency

Q1

Q0

S0

S1

S3

S4

Not
Notmuch
muchdifference
differencein
inthese
thesetwo
two
assignments
assignments

J.J. Shann 6-130

Example: 4-Bit String Recognizer

Reset
S0

1/0

0/0
S1

S2

1/0

0/0

1/0

1/0

0/0

S7'
0,1/0

Medium Priority:
(S1, S2), (S3', S4') 2, (S7', S10')

0/0
S4'

S3'
0,1/0

Highest Priority:
(S3', S4'), (S7', S10') 2

S10'
0/1

1/0

Lowest Priority:
0/0: (S0, S1, S2, S3', S4', S7')
1/0: (S0, S1, S2, S3', S4', S7' , S10')

J.J. Shann 6-131

Highest Priority:
(S3', S4'), (S7', S10') 2
Medium Priority:
(S1, S2), (S3', S4') 2, (S7', S10')

State Map
Q1 Q0
00
Q2
0

01

11

10

Q1 Q0
00
Q2

S0

01

11

S0

1
Q1 Q0
00
Q2
0

01

S0

10

S0

S4'

S7'

01

11

10

Q1 Q0
00
Q2

00 = Reset = S0
S10'

11

10

S3'

S7'

S0

S3'

S4'

S10'

S7'

S4'

S10'

10

11

10

S0

S1

S3'

S2

S4'
(a)

Q1 Q0
00
Q2
0

01

10

S0

S3'

Q1 Q0
00
Q2
0

11

Q1 Q0
00
Q2
0

01

Lowest Priority:
0/0: (S0, S1, S2, S3', S4', S7')
1/0: (S0, S1, S2, S3', S4', S7' , S10')

01

11

Q1 Q0
00

01

11

S7'

S0

S1

S3'

S10'

S7'

S2

S4'

Q2

(b)

10

Adjacent states:
(S7', S10')
(S3', S4'),
(S1, S2),

S10'

J.J. Shann 6-132

Effect of Adjacencies on Next State Map

Current
State
(S0 ) 000
(S1 ) 001
(S2 ) 101
( S'3 ) 011
(S4' ) 111
( S7' ) 010
(S'10) 110

Next State
X =0 X=1
101
001
111
011
011
111
010
010
110
010
000
000
000
000

Q2 Q1
00
Q0 X
00 0

01
0

11
0

10
X

01

01

11

10

Next State
X =0 X=1
010
001
100
011
011
100
101
101
110
101
000
000
000
000

11
0

10
X

01

11

10

01

11

10

01

01

11

10

P2

01
0

11
0

10
X

11

10

01

11

10

P1

Q2 Q1
00
Q0 X
00 0

(Another assignment)

Q2 Q1
00
Q0 X
00 1

01
0

P2

(p.6-120(a))
Current
State
( S0) 000
( S1) 001
( S2) 010
( S3' ) 011
( S'4 ) 100
( S7' ) 101
(S'10) 110

Q2 Q 1
00
Q0 X
00 0

Q2 Q1
00
Q0 X
00 0

P0
Q2 Q1
00
Q0 X
00 1

01

11

10

01

11

11

10

10

P1

P0

First encoding exhibits a better clustering of 1's in the next state map
J.J. Shann 6-133

Construct the Binary-coded State Table

Minimal state table

State assignment

Transition table

Unused states: dont-care conditions

(Binary-coded state table)

Eg.:

A = 00, B = 01, C = 11, D = 10

Transition table
(Binary-coded
state table)
J.J. Shann 6-134

D. Derive Flip-Flop Input Eqs & Output Eqs

E. Circuit

J.J. Shann 6-135

Flip-Flop Excitation Tables

Select the flip-flop type or types

Flip-flop excitation tables: (p.6-46)

J.J. Shann 6-136

(a) Designing Using D Flip-Flops

Example 6-2: Sequence detector (p.6-86)

State diagram:

State table:

J.J. Shann 6-137

State assignment:
A = 00, B = 01,
C = 11, D = 10
Binary coded state table:

J.J. Shann 6-138

F-F input eqs & output eq:

A(t + 1) = DA ( A, B, X ) = m(3,6,7)

D f-f input values

B (t + 1) = DB ( A, B, C ) = m(1,3,5,7)

Z ( A, B, X ) = m(5)

J.J. Shann 6-139

Logic diagram:

DA = AB + BX
DB = X

Z = AB X

J.J. Shann 6-140

Designing w/ Unused States

Example:

State table:
3 unused states
000
110
111

J.J. Shann 6-141

Maps for optimizing flip-flop

input equations:

J.J. Shann 6-142

Logic diagram:

DA = AX + BX + B C
DB = A C X + A B X

DC = X

J.J. Shann 6-143

(b) Design Using JK Flip-Flops

()

Example:
State diagram:

J.J. Shann 6-144

 State table and JK

flip-flop inputs:

Q Q+
0 0
0 1
1 0
1 1

J
0
1

1
0

J.J. Shann 6-145

 Maps for flip-flop input equations:

J.J. Shann 6-146

 Circuit:
JA = B x
JB = x

KA = B x
KB = Ax + A x = (A x)

J.J. Shann 6-147

(c) Design Using T Flip-Flops

( )

Example: 3-bit binary counter

State diagram:

J.J. Shann 6-148

 State table and T flip-flop inputs:

J.J. Shann 6-149

 Maps for flip-flop input equations:

Circuit:

J.J. Shann 6-150

F. Verification

J.J. Shann 6-151

Verification of sync seq ckts:

show that the ckt produces the original state diagram or

state table
used states
unused states

Manual verification: for small ckts

analyze the ckt

Verification w/ simulation
requires a seq of input combinations and applied clocks

J.J. Shann 6-152

Example

E.g.:
Synthesis
(A ~ F)

Verify
Analysis
(G)

J.J. Shann 6-153

Example 6-4

1101
Seq Recognizer

E.g.: Verifying the sequence recognizer

Test generation for simulation

0,1

1,1

1,0

0,1

0,0

0,1

1,1

1,0

0,0

J.J. Shann 6-154

Simulation

0,1

1,1

1,0

0,1

0,0

0,1

1,1

1,0

0,0

J.J. Shann 6-155

 Word Problems
Example: Vending Machine
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change

<Ans,>
Understand the problem:
N
Coin
Sensor

D
Reset

Vending
Machine
FSM

Open

Gum
Release
Mechanism

Clk

J.J. Shann 6-156

Draw state diagram:

Inputs: N, D, reset

Reset
S0

Output: open
N
S1

S2

S4

S5

S6

[open]

[open]

[open]

S3

S7

S8

[open]

[open]

J.J. Shann 6-157

State Minimization
Reset
0

N
5
D
N
10
D
N, D
15
[open]

reuse states
whenever
possible

Symbolic State Table

J.J. Shann 6-158

Problems
Sections

Exercises

6-1
6-2

6-1, 6-2

6-3

6-3, 6-4

6-4

6-5~6-13

6-5

6-14~6-23, 6-25, 6-26, 6-28~6-30

6-6

6-24, 6-27, 6-31

6-7 ()

6-32~6-37

6-8 ()

6-38~43

J.J. Shann 6-159

Homework

6-5
6-8
6-9
state diagram
state table
6-16

JK flipflopsc

J.J. Shann 6-160

Given the following state diagram, select a good

state assignment. Show your assignment in a state
map and justify your answer in terms of the state
assignment guidelines.

J.J. Shann 6-161