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TRANSMISSION
LINE
t
h
GROUND PLANE
6077-01 AN 1205
Equations-1
AN 1205
The characteristic
impedance
Zo of
the microstrip is calculated using
the approximation:
Zo =
87
5.98h
ln
0.8w + t
r + 1.41
87
5.98h
Zo =
ln
The
delay
for microstrip
r + 1.41
tpd =propagation
1.017
0.475r +0.8w
0.67+ t
is:
tpd
Equations-1
AN 1205
1205
Co
(pF/ft)
tpd == 1.017
AN
0.475r + 0.67
ZoEquations-1
tpd
Co =
(pF/ft)
Zo
where:
4b
= 60 ln dielectric
Zo
constant
of
r = relative
+ t)
r 87 0.67(0.8w
5.98h
Zo =
the
PCB
board
ln
87
5.98h
Zo== 60r +
4b
0.8w
+t
Zo
ln1.41 ln 0.8w
Zo
= characteristic
impedance
of the
0.67(0.8w
++t)t
rr + 1.41
transmission line
tpd==capacitance
1.017 0.475rof
+ 0.67
Co
the transmistpd
= 1.017
r + 0.67
tpd = 1.017 0.475
r (ns/ft)
sion line
tpd
Co = tpd (pF/ft)
Zo
Co
tpd== Zo
1.017(pF/ft)
r (ns/ft)
DIELECTRIC
0.039 INCHES
(0.991 mm) TYPICAL
CORE
LAYER 2
GROUND
PLANE
DIELECTRIC
LAYER 4
TRACES
LAYERS 1 AND 4:
LAYERS 2 AND 3:
r = 4.4
6077-02 AN 1205
VCC**
VCC
GND_RXA
VCC_RXA
RXCAP1
VCC_TXECL
VCC
GND
VCC
GND*
VCC*
GND_TXHS
VCC_TXHS
GND*
VCC*
CPLLR
RXCAP0
GND_RXTTL
VCC*
VCC_RXTTL
VCC
TOP VIEW
VCC*
B
C
D
12.00
14.2
17.8
E
X
6077-03
0.80
0.5
1.80
7.5
10.2
13.8
AN0.50
1205
0.30
1.80
TXCAP1
VCC
VCC_RXTTL
12.00
GND
16.00
VCC
HDMP-1636A
VCC
GND
HDMP-1646A
TXCAP0
VCC_TXA
VCC_RXTTL
GND*
GND_TXA
GND_RXTTL
GND_RXTTL
CPLLT
VCC
VCC**
6077-04 AN 1205
The PLL capacitors are placed physically close to the appropriate pins on
the transceivers as shown in Figure 5.
Keeping the lines short prevent the
PLL loop capacitors from picking up
stray noise from surrounding lines or
components.
I/O Interfacing
The HDMP-1636A/46A has four
different I/O types as summarized
in Table 1. The I-TTL and O-TTL are
compatible to standard TTL. The
high-speed serial lines are Positive
ECL (PECL) output voltage swings,
but are designed to be AC coupled.
All I/O connections have ESD protection diodes. Figure 6 shows the
high-speed serial connections.
3
RXCAP0
RXCAP1
CPLLR
49
48
0.1
TOP VIEW
GND
*VCC
*VCC
16
17
*GND
*GND
TXA
0.1
GND
GND
0.1
VCC
TXCAP0
VCC
TOP VIEW
GND
TXCAP1
GND_RXTTL
VCC_RXTTL
VCC_RXTTL
Zo
C1
R5
TX
-DOUT
Zo
R1
R2
-DIN
0.01
VCC_RXA
0.1
+DIN
C3
RX
R6
R4
0.01
150
6077-05 AN 1205
R3
Rpad
150
+DIN
VCC
VCC_RXTTL
RBC1
RBC0
GND_RXTTL
Rpad
0.1
0.1
150
VCC_TXHS
+DOUT
-DOUT
VCC_TXECL
VCC_TXA
VCC
CPLLT
+DOUT
OPTIONAL SERIES
RESISTORS: SEE
TEXT
-DIN
C2
I/O Type
Definition
Used on Pins:
R5 = R6 = Zo
I-TTL
Input TTL.
6077-07 AN 1205
Floats high when left open
TX[0...9], LOOPEN,
REFCLK, ENBYTSYNC
O-TTL
Output TTL
BYTSYNC,
HS_OUT
High-Speed Output.
PECL Compatible.
+DOUT, -DOUT
HS_IN
High-Speed Input.
PECL Compatible.
+DIN, -DIN
C1 = C2 = C3 = 0.01 F
+DOUT
R3
Zo
RX
R4
Zo
R1
+DIN
R5
TX
-DOUT
C1
R2
C2
-DIN
C1 = C2 = 0.01 F
R5 = 2Zo
607706 1205
Applications Support
System designers can quickly
evaluate the HDMP-1636A or the
HDMP-1646A by ordering the
HDMP-163K evaluation board. This
is a completely assembled board
for the HDMP-1636A transceiver
(electrical performance is the same
as the HDMP-1646A). The evaluation
board is designed for a quick and
easy evaluation of the transceiver
chip. The board brings out all pins
from the chip to various connectors and jumper options. It can be
used in a stand-alone configuration
or connected to an external host.
The parallel interface to the host
is through a 2x10 ribbon header
on the input and a 2x14 ribbon
header on the output. SMA connectors are provided on all the
high-speed serial coax lines and on
the reference clock input (REFCLK).
A socket for an onboard reference
clock at 125MHz is also provided. A
BER much better than 1 x 10-14 can
be routinely measured using the
HDMP-163K evaluation board. This
is over 24hours of error free operation at 1.25 GB. Figure 8 shows the
eye diagram at 1.25 GB when measured using an Avago Technologies
83480A Communications Analyzer
connected to the Dout- coax port of
the HDMP-1636A.
Fiber-Optic Interface
Figure 9 shows how the HDMP1636A/46A can be connected to
the HFBR-53D5 multimode, 1-rowof-9-pins (1x9) VCSEL fiber-optic
transceiver. The following are some
suggested layout guidelines when
using the HDMP-1636A/46A and
HFBR-53D5.
Use controlled impedance transmission lines on the parallel and
high-speed serial lines.
Route the high-speed differential
lines together and keep them of
5
200.0 ps/DIV
107.6074 ns
f1 300 mV/DIV
200.0 ps/DIV
107.2954 ns
f1 150 mV/DIV
(b) DOUT+
200.0 ps/DIV
107.2954 ns
f1 150 mV/DIV
(c) DOUT-
VEE
TD+
TDVCCT
VCCR
SD
RDRD+
VEE
SD
L7
1 H
9
8
7
6
5
4
3
2
1
C18
0.1 F
C23
0.01 F
8
7
6
5
R22
270
L8
1 H
R23
270
VDDSD
R25
191
R27
68
R26
191
R28
68
C17
0.01 F
C16
0.01 F
R29 0
C14
0.01 F
C15
0.01 F
VDDSD
0.1 F
0.1 F
0.1 F
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C43
0.1 F
VDDSD
VDDSD
VDDSD
6077-09 AN 1205
0.1 F
R21
150
0.1 F
R20
150
R30
0
R42
100
C47
0.1 F
L10
1 H
VCC (5 V)
10 F
(TANTALUM)
RX_LOS
C108
10 F
(TANTALUM)
(OPTIONAL)
C21
0.1 F
C19
0.1 F
R31
0
VCC (5V)
C20
0.1 F
VCC (5V)
VCC
Q0
NC
GND
HFBR-53D5
U4
R24
270
1
NC
2
D0+
3
D04
VBB
US MC100ELT21
PECL TO TTL
CONVERSION (NON-INVERTING)
BYTSYNC
RX[9:0]
U3
HDMP-1636A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TX[9:0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
C42
0.1 F
VDDSD
7
14
XTAL 125
MHz
U2
LOOPEN
REFCLK
ENBYTSYNC
L9 1 H VDDSD
C46
0.1 F
N/C
N/C
RBC0
RBC1
FER BD-SMT-HF30ACB201209-600mA
VDDSD
L2
VDD
C109
(+3.3 V)
10 F (TANTALUM)
+
Jitter Transfer
Jitter transfer for the transmitter PLL
is shown in Figure 10. The curves are
generated by modulating REFCLK
(125 MHz) with a sinusoidal waveform and measuring the resulting
jitter transferred or imposed on the
high-speed 1.25 Gb/s transmitter
output lines. In this case, the sinusoidal waveform is swept from 10 KHz
to about 7 MHz. The PLL behaves
like a low-pass filter to any noise
present on REFCLK. Below the corner frequency (f - 3 dB) of about 1 to
2 MHz, frequencies are passed with
no attenuation. Only a slight 0.6 dB
amplification of the modulating signal occurs at the corner frequency.
The REFCLK modulation signal is
attenuated when it exceeds the corner frequency of the PLLs low pass
filter response. The vertical axis is
expressed in jitter gain (dB). Because
of the non-linear nature of the PLL,
the corner frequency is also a function of the jitter amplitude. The jitter
amplitude is varied from 0.05UI
to 1UI, resulting in the 4 different
curves shown in Figure 10. UI stands
for Unit Interval, and is a traditional
unit of measurement for jitter amplitude. One UI is defined as the 800 ps
time interval of one 1.25 GB symbol.
When jitter is equal to 800 ps, the
phase deviation of the clock is equal
to 1 UI.
100
10
TOLERANCE (UI)
Jitter Performance
The HDMP-1636A/46A meets the
jitter budget in Table 38-10 of the
IEEE 802.3z Gigabit Ethernet specification.[9] Transmitter jitter transfer,
jitter tolerance and VCC jitter transfer
curves for the SERDES are provided
in the next sections. Although not
required by the Gigabit Ethernet
standard, the graphs are useful
information in understanding the
performance of the SERDES.
-5
-10
-15
-20
1 E+3
0.05 UI
0.15 UI
0.3 UI
1.0 UI
10 E+3 100 E+3 1 E+6 10 E+6
JITTER FREQUENCY (Hz)
0.1
TOLERANCE RESULTS
INSTRUMENT LIMIT
100 E+6
Jitter Tolerance
Jitter tolerance is a measure of
design margin in a serial communications link. The purpose of the test
is to measure the transceivers error
performance as a function of sinusoidal jitter at various frequencies
and amplitude levels. There is no
jitter tolerance mask in the Gigabit
Ethernet standard. The following is
provided for information only. Sinusoidal jitter is added to REFCLK. In
this test, random and deterministic
jitter are added in order to simulate
a real system. Random jitter (0.287
UI) is added using a random noise
generator (noise diode generator),
and deterministic jitter (0.462 UI) is
added using a fixed amount of coax
cable. Detailed information on jitter
tolerance measurement techniques
is contained in the work done by the
Fibre Channel Jitter Working Group
and is a good reference.[10] Figure
11 shows the results of this test.
The lower curve is the measured
behavior of the HDMP-1636A/46A
transceiver. Note that below about
300 KHz, the transceiver can tolerate jitter above 1 UI. If viewed on
a digital oscilloscope, this corresponds to no eye opening. At these
0.01
1 E+0
100 E+0
10 E+0
1 E+6
JITTER FREQUENCY (Hz)
100 E+6
1400
1200
References
[1] HDMP-T1636A/1636A/1646A
Gigabit Ethernet Transceiver Chip
Data Sheet, publication number
5968-3339E (5/99).
1000
800
600
400
200
0
0
200
400
600
VCC NOISE (p-p, mV)
800
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright 2007-2010 Avago Technologies Limited. All rights reserved.
5980-0276E - July 28, 2010