EI2403 - VLSI Design 2 Marks With Answers

SNS College of Technology, Coimbatore 35
Department of Electronics and Instrumentation Engineering
EI2403 VLSI Design 2 Marks

Questions and Answers
IV Year, 7th Sem, EIE
UNIT I BASIC MOS TRANSISTOR

9
Enhancement mode and Depletion mode Fabrication (NMOS, PMOS, CMOS,
BiCMOS) Technology NMOS transistor current equation Second order effects
MOS Transistor Model.
UNIT II NMOS AND CMOS INVERTER AND GATES
9
NMOS and CMOS inverter Determination of pull up / pull down ratios Stick
diagram lambda based rules Super buffers BiCMOS & steering logic.
UNIT III SUB-SYSTEM DESIGN AND LAYOUT
9
Structured design of combinational circuits Dynamic CMOS & clocking Tally
circuits (NAND- NAND, NOR-NOR and AOI logic) EXOR structure
Multiplexer structures Barrel shifter, high speed adder and multiplier circuits.
UNIT IV DESIGN OF COMBINATIONAL ELEMENTS AND REGULAR
ARRAY LOGIC
9
NMOS PLA Programmable Logic Devices - Finite State Machine PLA
Introduction to FPGA.
UNIT V VHDL PROGRAMMING
9
RTL Design simulation and synthesis - Combinational logic Types Operators
Packages Sequential circuit Sub-programs Test benches. (Examples: adders,
counters, flipflops, FSM, Multiplexers / Demultiplexers).
TOTAL: 45 PERIODS
TEXT BOOKS:
Page
1. D.A.Pucknell, K.Eshraghian, Basic VLSI Design, 3rd Edition, Prentice Hall of India, New
Delhi, 2003.
2. Rabey, J.M., Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1955.
3. Bhasker, J., VHDL Primer, Prentice Hall 1995.
http://studyzone.dgpride.com
SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers
1. Unit I - BASIC MOS TRANSISTOR

What is the other name for MOSFET? Why is it called so?
MOSFET is also known as IGFET which means an Insulated Gate Field Effect
Transistor. Unlike JFET in MOSFET the gate is insulated from the substrate by an
oxide layer, hence the name.
1.2.
What are the two substructures of MOSFET?

Two substructures of MOSFET are Enhancement MOSFET (E-only MOSFET)
and Depletion Enhancement MOSFET (DE-MOSFET). DE MOSFET can be
operated in both depletion mode and enhancement mode by changing the polarity of
gate-source voltage VGS. E-only MOSFET works with large values of VGS only.
1.3.
Draw the symbols for P-channel and N-channel DE-MOSFET and E-only
MOSFET.
1.4.
What is the basic difference between JFET and MOSFET?

JFET has its gate and substrate connected together. In MOSFET gate is isolated
from the substrate.
1.5.
What are the limitations of scaling

The reduction of the size of the MOSFETs is called scaling. The operational
characteristics of MOS transistor will change with the reduction of its dimensions.
Limitations of scaling are (i) short channel effects,(ii) narrow channel effects,(iii)
small device geometry effect
1.6.
Draw the model transfer characteristics for DE-MOS and E-only MOSFET
1.7.
Define threshold voltage Vt? How is it temperature dependent?
Page
1.1.

Threshold voltage is defined as the voltage applied between the gate and the
source of a MOS device below which the drain-to-source current Ids effectively drops
to zero. Absolute value of the threshold voltage decreases with an increase in
temperature.
1.8.
List the factors on which threshold voltage depends?

Vt depends on
gate conductor material
gate insulator material
gate insulator thickness
impurities at the Silicon- Insulator interface.
Voltage between the source and the substrate,Vsb
1.9.
What are the different regions of operation for MOS transistors and the
conditions foreach?
Cutoff or threshold region; Ids = 0; Vgs< Vt ;
Non-saturation or linear region; Ids
-Vt)Vds-Vds2/2)] ; 0<Vds<Vgs-Vt
2
Saturation region; Ids
-Vt) /2)] ; 0< Vgs-Vt<Vds
1.10. Name the different SPICE models for simulation.

Level 1-Shichman-Hodges model
Level 2-Geometry based model
Level 3-Semi-empirical model
Level 4-Berkeley short channel IGFET model
1.11. Define Fermi level. Write the expression for fermi level in the P-type bulk
silicon.
Fermi level is defined as that electron-energy level in thermodynamic
equilibrium at which the probability of occupation of an energy state by an electron is
one-half.
f =VT ln (ni/Na).V
1.12. Write the expression for process transconductance parameter and device
transconductance parameter.
Process transconductance parameter OR process gain is expressed as
Kn = n Cox (A/V2). Where, n mobility of electrons cm2/ (V.s)
Device transconductance parameter or gain is expressed as
K =K(W/L)
Page
1.13. Why is the calculation of sidewall capacitance complex?

The impurity concentration varies in a complicated manner along the side
walls of the source and drain regions.
Voltage dependence of the side wall capacitances will be different from
that of junction capacitance.
Side walls of source and drain regions are curved and hence an accurate
calculation of
the side wall capacitance requires 2-D modeling.\

1.14. What is meant by diffusion capacitance? Write the expression for the same.
Diffusion capacitance CT is the total capacitance of the source and drain region
of area A and perimeter P and is approximated as CT=C j. A + C jsw .P
1.15. Illustrate pictorially the different conductor surface states.
1.16. Draw the VTC for CMOS inverter and mark the different regions of operation.
1.17. Define Noise Margin. What is its effect?

Noise Margin is one of the figures of merit of a CMOS device. It allows us to
determine the allowable noise voltage on the input of a gate so that the output will not
be affected. Low Noise Margin (NML) and High Noise Margin (NMH) are the two
commonly used specifications. If either NML or NMH for a gate are reduced, then the
gate may be susceptible to switching noise that may be present on the inputs.
1.18. What are the main CMOS fabrication technologies available?
The four main CMOS fabrication technologies are n-well process, p-well
process, twin-tub process, silicon on-insulator
Page
1.20. How is the channel stop implant made?

Channel stop implant is made by doping the P-substrate in areas where there are
no N- transistors P+ using a photo resist mask.
1.19. What is a thinox?

Thinox is an active mask formed which defines the areas where thin oxide are
needed to Implement transistor gates and allow implantation to form P or N-type
diffusions for transistor source/drain regions.

1.21. Draw the circuit of dynamic NMOS and PMOS NOR gate
1.22. What is the advantage of CMOS over PMOS and NMOS technology? (Nov/Dec
2011)
reduce the complexity of the circuit
low static power consumption
high noise immunity
high density of logic function on a chip
1.23. Write the reasons for the limited load driving capabilities of MOS transistors.
(Nov/Dec 2011)
The MOS technology lies in the limited load driving capabilities of MOS
transistors. This is due to the limited current sourcing and current sinking abilities
associated with both p- and n- transistors. Bipolar transistors provide higher gain and
have generally better noise and high frequency characteristics than MOS transistors
and have effective way of speeding up VLSI circuits.
Page
1.25. Compare CMOS and Bipolar technologies. (Nov/Dec 2012)

S.No. CMOS Technology
Bipolar Technology
1.
Low static power dissipation High power dissipation
2.
High input impedance
Low input impedance
3.
High packing density
Low packing density
4.
Low output drive current
High output drive current
5.
Drain and source are
It is unidirectional
interchangeable
6.
High noise margin
Low voltage swing logic
1.24. What are the advantages of BiCMOS technology? (May/June 2012)

Improved speed over purely-CMOS technology
Lower power dissipation than purely-bipolar technology (simplifying
packaging and board requirements)
Flexible I/Os (i.e., TTL, CMOS or ECL)
BiCMOS technology is well suited for I/O intensive applications
ECL, TTL and CMOS input and output levels can easily be generated
with no speed or tracking consequences
high performance analogue
Latchup immunity.

1.26. What is latch-up in CMOS circuits? (Nov/Dec 2012)
If every silver lining has a cloud, then the cloud that has plagued CMOS is a
parasitic circuit effect called latchup. The result of this effect is the shorting of the
VDD and VSS lines, usually resulting in chip self-description or at least system failure
with the requirement to power down. This effect was a critical factor in the lack of
acceptance of early CMOS processes.
Page
1.27. Compare Enhancement mode and depletion mode MOSFET(May/June 2012)

S.No. Enhancement mode
Depletion mode
7.
The gate electrode is placed on top A means of operating FETs in which
of a very thin insulating layer.
increasing the magnitude of the gate bias
decreases the current.
8.
There are a pair of small n-type The channel exists by manufacturing and
regions just under the drain & when we connect the FET to voltage we
source electrodes.
control its capacitance
9.
If apply a +ve voltage to gate, will Depletion-type
MOSFET
has
an
push away the holes inside the p- implanted channel. Thus if we apply Vtype substrate and attracts the DS, the drain current will flow for V-GS =
moveable electrons in the n-type 0
regions under the source & drain
electrodes.
10. Increasing the +ve gate voltage While in Depletion MOSFET the channel
pushes the p-type holes further away needs to be created, and that is done by
and enlarges the thickness of the adding a DC voltage to the Gate, until the
created channel.
condition of "Inversion" is reached and
the channel is formed. This restricts us to
use only signals of one polarity to
maintain the MOSFET operating and
avoid the cut-off condition.
11. As a result increases the amount of a N mosfet that conduct when Vgs = 0V is
current which can go from source to called depletion mode;
drain this is why this kind of
transistor is called an enhancement
mode MOSFET
2. Unit II - NMOS AND CMOS INVERTER AND GATES

2.1.
What is the use of layout design rules?

Layout design rules help in preparing photomasks used in the fabrication of
integrated circuits. These rules provide the necessary communication link between
circuit designer and the process engineer during manufacturing phase.
2.2.
What are the issues addressed by design rules?

Design rules mainly address two issues: The geometrical reproduction of features that can be reproduced by the
mask making and lithographical process.
The interactions between different layers
2.3.
Define the two main approaches for describing design rules?

The two main approaches for describing layout rules are
1. micron rule
2. - Based rules.
Micron design rules give a list of minimum feature sizes and spacing for all the
masks required in a given process.
- Based design rules are based on a single parameter, which characterizes
the linear feature- the resolution of the complete wafer implementation process.
2.4.
What are the four basic layers on which MOS circuits are formed?
1. n diffusion,
2. p diffusion,
3. polysilicon,
4. metal
Define stick diagram? Show the monochrome stick encoding for implant and
polysilicon.
Stick diagrams are used to convey layer information through the use of a colour code or
monochrome shading.
Implant
Polysilicon
In a stick diagram, what indicates the formation of transistor or a switch ?

When polysilicon crosses thinox layer a transistor or switch is formed. (2)
2.7.
What is a pass transistor? What are its advantages?

Pass transistor is similar to a buffer.
Advantages of pass transistor are
1. occupies less space, because any logical operation can be realized with lesser
number of MOS transistors
2. No direct path between VDD and Gnd. So, amount of power dissipation is
lesser understand by condition.
Page
2.6.
2.5.

2.8.
Draw the monochrome stick diagram for NMOS inverter.
2.9.
How is CMOS transmission gate superior to NMOS pass transistor?

CMOS transmission gates are superior to NMOS pass transistors in 2 ways.
1. They o/p both strong ones and strong 0s
2. T.G consists of 2 transistors in parallel. Except near the positive and negative
rails, it has about half the resistance of a single pass transistor. Halving the
resistance halves the propagation delay.
2.10. What are the disadvantages of CMOS transmission gates? Draw the symbol for
transmission gate.
Disadvantages of CMOS transmission gate are
1. Require more area than NMOS pass circuits
2. Require complemented control signals
3. T.G symbol
Page
2.12. List the advantages of generalized design rules in VLSI.

1. Ease of learning because they are scalable, portable and durable.
2. Longevity of designs that are simple, abstract and have minimum clutter.
3. Increased designer efficiency due to fewer levels and fewer rules.
4. Design efficiency accomplished by compaction, layout rule checking,
electrical rule checking, simulation and verification
5. Automatic translation to final layout.
2.11. What is meant by scaling?

Scaling of MOS transistor is concerned with systematic reduction of overall
dimensions of the devices as allowed by the available technology, while preserving
the geometric ratios found in the larger devices.

2.13. Give a brief description about NAND implementation of a MUX circuit.
MUX consists of switched paths. NAND implementation uses depletion devices
to short circuit undesired connections while using enhancement mode devices to form
the switches that exert control. MUX is defined by the locations of the ion implants
required to form the depletion mode transistors.
Diagram
A
I0
I1
I2
I3
2.14. What are the different fatal errors possible in layout design and illustrate them
pictorially. ?
2.15. List the disadvantages of dynamic logic.

1. Logic function is implemented by the NMOS pull down network.
2. Less no. of transistors required.
3. Noise margin doesnt depend on transistor ratios
4. Consumes only dynamic power.
5. Faster switching speeds.
Page
2.17. How latch up problems can be rectified in CMOS fabrication process? (Nov 04)
CMOS/bulk devices have parasitic bipolar transistors can cause latch up,a
condition in which high currents exist between VDD & Gnd.One method of
preventing Latch up consists of decreasing the current gains of the parasitic
transistors. If the product of the two current gains of both transistors is less than
unity, f/b is not self sustaining & the device cannot latch. The current gain of the
vertical pnp tr is determined by the process design & can be reduced by using buried
2.16. What is meant by domino logic?

Domino logic module consists of a PE logic block followed by an Inverter. This
ensures that all inputs to the next logic block are set to 0 after the precharge period.
So, only the possible transition during the evaluation period is the 0-1 transition.

layers of n+ material under the n wells. The tendency of CMOS / bulk devices to latch
up is reduced by putting guard rings around the p&/or n wells & making frequent
contacts to the rings. This reduces the parasitic resistance values.
2.18. Define noise margin. Illustrate how it can be obtained from the transfer
characteristics for a CMOS inverter. (Nov 04)
Noise margins are measures of gates susceptibility to spurious spikes. The larger
the noise margin the more immune a gate is to extraneous voltage signals.
(i.e.) NMH =VoH - ViH & NML =ViL - VoL
2.19. Is the transmission of logic 1 degraded as it passes through a n MOS pass
transistor? Why? (Nov 04)
Yes, the transmission of logic 1 degraded as it passes through a n MOS pass
transistor.
V0 = VDD Vt.
2.20. Draw the stick diagram of a p-well CMOS inverter. (Nov/Dec 2011)
2.21. Why BiCMOS technology does not offer speed advantage in applications like
ALU and ROM subsystems? (Nov/Dec 2011)
Main disadvantage : greater process complexity compared to CMOSResults in a
1.25 -> 1.4 times increase in die costs over conventional CMOS.Taking into account
packaging costs, the total manufacturing costs of supplying a BiCMOS chip ranges
from 1.1-> 1.3 times that of CMOS.
2.22. Define body effect. (Nov/Dec 2012)
The threshold voltage Vt is not constant with respect to the voltage difference
between the substrate and the source of the MOS transistor. This is known as the
substrate-bias effect or body effect
Page
2.24. Write the significance of based design rules. (Nov/Dec 2012)

The rules provide a necessary communication link between circuit designer and
process engineer during the manufacturing process. The main objective associated
10
2.23. What are the three approaches used in making contacts between polysilicon and
diffusion in nMOS circuits. (Nov/Dec 2012)
1. Polysilicon to metal then metal to diffusion
2. Buried contact polysilicon to diffusion
3. Butting contact (polysilicon to diffusion using metal)

with layout rules is to obtain a circuit with optimum yield in as small an area as
possible without compromising reliability of the circuit.
Page
11
2.25. Draw the circuit schematic of a non-inverting type nMOS type buffer. (Nov/Dec
2012)
3. Unit III - SUB-SYSTEM DESIGN AND LAYOUT

3.1.
Define a data path.

Data path is the core of a processor. It is where all computations are performed.
They are generally arranged in a bit sliced organization.
3.2.
What is meant by bit-sliced data path organization

Data path is where all computations are performed in a processor. They are
arranged in a bit sliced organization. Instead of operating on single bit digital signals,
the data in a processor is arranged in a word based fashion. A 32 bit processor operates
on data words that are 32 bit wide. Since the same operation has to be performed on each
bit of the data word, the data path consists of 32 identical slices, each of them operating
on a single bit. So the name bit sliced. Data path designer can concentrate on the design
of a single slice that is repeated 32 times.
Write down the Expression for the total propogation delay in an n bit carry
bypass Adder.
Tp = tset up + M tcarry + (N/M-1) tbypass + M tcarry + tsum.
3.4.
What is the total time delay for a ripple carry Adder?

Tadder = (N-1) tcarry + tsum.
3.5.
List the different considerations for designing a Ripple carry adder.

1. Propagation delay of ripple carry adder is linearly proportional to N.
2. It is important to optimize tcarry than tsum.
3. Inverting all i/ps to a full adder results in inverted values for all o/ps.
3.6.
What are the draw backs of a static adder circuit?

1. Consumes large area.
2. Circuit is slow.
3.7.
Why is static adder circuit slow?

A static adder circuit is slow as,
1. Long chains of series PMOS transistors are present in both carry & Sum
generation circuit.
2. Intrinsic load capacitance of the Co signal is large and consists of 2 diffusion
& 6 gate capacitances plus the wiring g capacitances.
3. Carry generation ckt requires 2 inverting stages per bit.
4. Sum generation ckt requires an extra logic stage
3.8.
What is the advantage of Dynamic adder design?

Reduced capacitance of dynamic circuitry results results in substantial speed up
over static implementation.
Page
12
3.3.

3.9.
What is a Manjestor carry chain adder?

It uses a cascade of pass transistors to implement the carry chain. Propogate &
Generate signals are generated using pass transistor logic. The capacitance per node
on the carry chain is very small & equals only 4 diffusion capacitances.
3.10. Why is carry bypass Adder called so?

When the bypass control signal is set to 1, the incoming carry is forwarded
immediately to the next block through a bypass transistor.
3.11. Give the expresssin for the carry output of an n bit carry lookahead adder.
Co(k)= Gk+ Co(k-1 )
3.12. What is the importance of linear carry select Adder?
The linear dependencies present in a ripple carry adder is avoided in linear carry
select adder, by anticipating both possible values of the carry i/p and evaluate the
result for both possibilities in advance.
3.13. Why is the propagation delay in a carry select Adder is linearly proportional to
N?
It is because the block select signal that selects between 0&1 solutions still
has to ripple through all stages in worst case.
3.14. What is a bit serial multiplier?
When area is of prime concern, it is possible to reduce the cost of the multiplier
by using a time multiplexed approach .Here, a combination of a single adder & a
storage element is used to iteratively compute the summation of the partial products.
3.15.
What is a booth multiplier?

Booth multiplier is a radix -4 multiplication scheme , which examines 3 bits of
the multiplicand at a time to determine whether to add 0,1,-1,2,-2 of that rank of the
multiplicand.
3.16. What are the different applications of a Shifter?

Used in floating point units, scalers & multiplications by constant numbers.
Page
3.18. List the advantages of two phase clocking scheme.(Nov 04)

1. No chance of race conditions occurring in the circuit
2. No timing errors due to races or Hazards or clock skew
3. Two phase clocking schemes are popular due to its simplicity & reliability
4. Design procedures are also simple
13
3.17. Draw the circuit of a two phase clock generator using D-FF.

3.19. What are the major problems associated with the single phase clocking
scheme?(April05)
1. Race or hazards.
2. Timing errors
What is a transmission gate? Realize a 2-input AND gate using transmission gates.
(Apr 05)
Transmission gate is a combination of a PMOS & NMOS gate connected in
parallel.
3.20. Draw a 2 to 1 multiplexer using NMOS transistors.(Nov/Dec 2011)
3.21. What are the advantages of AOI implementation of two level logic functions?
(Nov/Dec 2011)
Construction of AOI cells is particularly efficient using CMOS technology where
the total number of transistor gates can be reduced compared to the same construction
using NAND logic or NOR logic.
3.22. Name the two phases of operation in a dynamic CMOS logic.(Nov/Dec 2012)
1. Precharge and
2. Evaluate
3.23. What is two phase clocking? (Nov/Dec 2012)
Inverting a single clock can lead to skew problems. Employ two non-overlapping
clocks for master and slave sections of a flip-flop. Thus we can have between one and
four clock lines to route around the chip
3.24. What are the two phases of operation of a dynamic CMOS logic? (Nov/Dec 2012)
Refer Q.No.23
Page
14
3.25. Draw the circuit schematic of a two input CMOS NAND gate. (Nov/Dec 2012)
Give the difference between CPLD & FPGA.

Both CPLD and FPGA fall under the category of Programmable Logic
Devices. CPLD comprises multiple circuit blocks (which are PLA or PAL like) on a
single chip with internal wiring resources to connect the circuit blocks. Each PAL like
block is connected to a circuit labeled I/O block which is attached to a number of the
chips input and output pins.
FPGA is a PLD that supports implementation of relatively large logic circuits.
They provide logic blocks for implementation of the required functions. FPGA has 3
types of resources, namely, logic blocks, I/O blocks for connecting to the pins of the
package, and interconnection wires and switches
4.2.
Why is PLDs popular compared to ASICs.

PLDs have a very general structure and include a collection of programmable
switches that allow the internal circuitry in the chip to be configured in many
different ways. These switches are programmed by the end user, rather than when
the chip is manufactured. ASIC is a chip designed from scratch. The logic circuitry
that must be included on the chip is designed first and then an appropriate technology
is chosen to implement the chip. Then the chip is manufactured by a company that
has the fabrication facilities. This process is time consuming and can be cost effective
only in a bulk demand situation. Due to these reasons, PLDs are more popular than
ASICs
4.3.
List the basic steps in designing with an LCA.

1. Design a system using gates and flip-flops
2. Enter a logic diagram of the system into the computer usinga schematic
capture program.
3. Run an automatic place and route program which greaks the logic diagram
into pieces which will fit into the configurable logic blocks. Place them in
appropriate places in the LCA and then route the interconnections between the
logic blocks.
4. Run a program which will generate the bit pattern necessary to program the
LCA.
5. Download the bit pattern into the internal RAM memory cells in the LCA and
test the operation of the LCA.
4.4.
Differentiate between PAL & PLA. (Nov 04)

Both PAL and PLA uses AND-OR arrays. PAL has a programmable AND array
and a fixed OR array. Whereas PLA has both AND and OR array programmable.
4.5.
What is a LUT?
Look up Table is a memory organization through which a cells combinational
logic may be physically implemented. LUT devices are more flexible and provide
more inputs per cell but at the expense of propagation delay.
Page
4.1.
15
4. UNIT IV - DESIGN OF COMBINATIONAL ELEMENTS AND

REGULAR ARRAY LOGIC
Draw the LCA realization of 1 bit shift register.
4.7.
Mention the important building blocks of an FPGA

Important building blocks in FPGA are
1. logic block
2. I/O block
3. Interconnect switches and wires
4.8.
Mention the important building blocks of an CPLD.

1. I/O block
2. Switch matrix
3. Function block
4. In-system programming controller
4.9.
Draw the circuit for the 2 input LUT
Page
4.6.
16

4.10. Differentiate between a Moore machine & Mealy machine.
Moore machine is a sequential circuit where outputs are function of the present
state only. The outputs of the sequential circuits are synchronized with the clock as
they depend on the outputs of flip-flops only that are synchronized with the clock.
Mealy machine is a sequential circuit whose output are functions of both the
present state and inputs. The state table of a Mealy machine must include an output
section that is a function of both the present state and inputs. When the outputs are
directly taken from the flip-flop, the state table can exclude the output section.
4.11. What is the function of a placement CAD tool ?
Placement CAD tool determines where in the target device each logic function in
the optimized circuit will be realized. Placement task highly depends on the
implementation technology.
4.12. What is meant by routing? What are its different phases?
After the placement of logic functions in macro cells wires in the chip are to
be used to realize the required interconnections. This step is called routing. It is
performed in 2 phases, Global routing and local routing. A good routing algorithm
will attempt to minimize the total routing area.
4.13. What is a boundary scan test?
Boundary scan test is a method for testing boards and ASICs using a fourwire interface.
4.14. How is boundary scan test performed on a PCB or ASIC?
To detect failures, manufacturers use boundary scan to test every connection
between ASICs on a board. During boundary scan, test data is loaded into each ASIC
and then driven on to the board traces. Each ASIC monitor their input, captures the
data received and then shifts the captured data out. Any defect in the board or ASIC
connections will show up as a discrepancy between expected and actual measured
continuity data
4.15. What is done in synthesis process?
It is the process of conversion of HDL code to gate level net list of the design.
Net list is the connectivity description of gate level circuit. Synthesis is a target
technology dependent issue, so user has to specify the target /device correctly
including its package type and speed grade. After synthesis, EDA tool will generate
EDIF/XNF file.
4.16. What is meant by in - system programming?
Instead of relying on a programming unit to configure a chip, the chip can be
made to program on the circuit board itself. This method is called In System
Programming. The circuitry which allows ISP is standardized by IEEE and is called
JTAG (Joint Test Action Group) port.
Page
17
4.17. Name the various building blocks of an FPGA(Nov/Dec 2012)

Configurable logic blocks(CLB), Input/output Block(IOB) and Switch
Matrix(Interconnects)

4.18. What is a CPLD?
CPLD stands for Complex Programmable Logic Device. They can be
programmed as per the users logic and can perform the user application. They are
reprogrammable and the design modification is easy. CPLD consists of multiple
circuit blocks on a single chip, with internal wiring resources to connect the circuit
blocks. Each circuit block is a PLA or PAL like blocks.
4.19. Give the floor plan of a typical CPLD.
4.20. List two advantages & two disadvantages of FPGA based design.
Advantages:
1. Supports implementation of relatively large logic circuits
2. It can be configured in many different ways.
Disadvantages:
1. Storage cells in FPGA are volatile.
2. Limited utilization of cells based on application.
Page
ROM problems
1. Size doubles for each additional input
2. Can't exploit don't cares
18
4.21. What are the benefits of implementing combinational logic functions using PLAs
when compared with ROMs? (Nov/Dec 2011)
PLA approach advantageous when
1. Design tools are available for multi-output minimization
2. There are relatively few unique minterm combinations
3. Many minterms are shared among the output functions

4.22. Give the floor plan of a typical FPGA.
4.23. Give the applications of dynamic logic arrays. (Nov/Dec 2011)

Dynamic PLAs are used as the basis of constructing a new class of
programmable devices called field-programmable dynamic logic arrays (FPDLAs).
Since dynamic PLAs with large number of inputs can be built in a small area due to
its regular circuit structure, and they produce the outputs in a time independent of the
number of inputs affecting the outputs, FPDLAs can operate at a higher speed and
require a smaller area than programmable devices built using static logic.
4.24. Define regularity. Determine the regularity of a 4 x 4 barrel shifter.(Nov/Dec
2012)
Hierarchy involves dividing a system into a set of submodules. Dividing the
system into different submodules end up with a large number of different
submodules. With regularity as a guide, the designer attempts to divide the hierarchy
into a set of similar building blocks
Page
19
4.25. What are the advantages of PLA?(Nov/Dec 2012)

1. Can be programmed outside of the manufacturing environment
2. Most programmable logic devices are erasable and reprogrammable.
3. Allows updating a device or correction of errors
4. Allows reuse the device for a different design
5. Ideal for course laboratories
6. Programmable logic devices can be used to prototype design that will be
implemented for sale in regular ICs.
5. Unit V - VHDL PROGRAMMING

5.1.
What is meant by a hardware description language?

HDL (Hardware Description Language) is used to model a digital system at
many levels of abstraction ranging from algorithmic level to gate level.
HDL is capable of handling any levels of complexity of the system, describing
hierarchy and explicitly modeling the timing. Examples of HDL are VHDL and
Verilog.
5.2.
What are the different design units in VHDL?

(a) Entity declaration
(b) Architecture body
(c) Configuration declaration
(d) Package declaration
(e) Package body.
(a) and (b) are essential units.
5.3.
Define entity. How do you declare it?

Hardware abstraction of a digital system is called an entity. It gives the external
view of the system. An entity is modeled using different design units.
Entity is declared as follows:
entity entity name is
port (in1,in2,.:in type; out1,out2.:out type);
end entity name;
5.4.
What is meant by an architecture body?

Architecture body gives the internal description of the entity. This description
can be done in different styles as a set of interconnected components that represents
the structure of the entity, or, as a set of concurrent or sequential statements that
represents the behavior of the entity. The simulator simulates an entity by reading in
its compiled description from the design library and goes through the elaboration
phase and initialization phase to the actual simulation.
Define port. How do you declare it?

Ports are signals through which the entity communicates with the other models in
its external environment.
Port declaration is as follows: port (in1,in2,.:in type; out1,out2.:out type);
What are the different modeling styles in the architecture body?
1. Structural or port mapping or gate level modeling
2. Concurrent or data flow modeling.
3. Sequential or behavioral modeling.
4. Mixed style of modeling.
5.7.
Differentiate between component declaration and component instantiation.

Component declaration and component instantiation are two parts in the
architecture body in structural modeling. These parts are separated by a keyword
begin. Component declarations specify the interface of components that are used in
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5.6.
20
5.5.

the architecture body. The declared components are instantiated in the statement part
of the architecture body using component instantiation statements.
5.8.
Distinguish between positional association and named association in port

mapping with an example.
The signals in the port map of a component instantiation and the port signals in
the component declaration are associated by positional or by named association.
5.9.
What is meant by delta delay?

A delta delay is an infinitesimally small delay which models hardware where a
minimal amount of time is needed for a change to occur. Delta delay allows for
ordering of events that occur at the same simulation time during a simulation
5.10. Is process statement executed concurrently or sequentially? What is its content?

A process statement is a concurrent statement that can appear within an
architectural body in behavioral modeling. Process statement has a declarative part
and a statement part. The statements appearing in the statement part sequential
statements and are executed sequentially. The list of signals specified within the
parenthesis after the keyword process constitute a sensitivity list, and the process
statement is invoked whenever there is an event on any signal in this list
5.11. What is a design library?
A design library is a location in the host environment where compiled
descriptions of VHDL design code are stored. Each design library has a logical name
that is used when referring to a library in a VHDL description.
5.12. Differentiate between bit data type and STD_LOGIC.
BIT is a pre-defined type of the language. It contains the character literals 0 and
1. STD_LOGIC is the type declaration specified equivalent to bit in IEE E design
library in the package STD_LOGIC_1164
5.13. What are the utilities provided by IEEE.STD_LOGIC_II64 ?
STD_LOGIC_1164 is one of the standard IEEE package. It defines a nine value
logic type called STD_ULOGIC, and contains its associated sub types, overloaded
operator functions and other useful utilities. This standard is called the IEEE std
1164-1993.
5.14. How the problem of multiple drivers for a signal is is resolved?
Signal with more than one driver must have a resolution function associated with
it. The resolution function is the mechanism which considers the values of all the
drivers for the particular signal and determines the effective value.
Page
5.16. Define a package.
21
5.15. Distinguish between procedures and functions.

Functions and procedures are two types of sub programs. Functions are used to
describe frequently used sequential algorithms that return a single value. They are
commonly used as resolution functions or conversion functions. Procedures are used
to partition large behavioral descriptions. They can return zero or more values.

A package provides a convenient mechanism to store and share declarations that
are common across many design units. A package is represented by,
(a) a package declaration and, optionally
(b) a package body
5.17. What is the use of block statements in VHDL?
A block statement is a concurrent statement. It provides a mechanism for
creating a hierarchy within an architecture body. It can be used for 3 major purposes:
(a) To disable signal drivers by using guards
(b) To limit scope of declarations, including signal declarations
(c) To represent a portion of a design
1. Write VHDL code for tristate buffer.
entity tristate_buf is
port(a,enable:in bit; y:out bit);
end tristate_buf;
architecture seq of tristate_buf is
begin
process
begin
if enable =0 then y<=hi-z ;
elsif enable =1 then y<=a ;
end if;
end process;
end;
5.18. List any two features of concurrent descriptions.
Concurrent descriptions specify the functionality of the entity without explicitly
specifying its structure. The functionality shows the flow of information through the
entity, which is primarily, expressed using concurrent signal assignment statements
and block statements.
2. Distinguish between a signal and variable in VHDL.
Variable is assigned a value instantaneously and the assignment operator is := compound
symbol. Signal is assigned a value always after a certain delay(user specified or default delta
delay) and the assignment operator is <= compound symbol
3. Write VHDL code for the circuit given below :
Page
22
entity and_nand is
port (A,B : in bit; Y: out bit);
end and_nand;
architecture concur of and_nand is
Y<= (A and B) nand C;
end concur;

5.19. Write the VHDL entity for a full adder(Nov/Dec 2011)
entity FA is
port(x,y,cin:in std_logic; s, cout:out std_logic);
end FA;
5.20. Write a VHDL code for a D flipflop (Nov/Dec 2011)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffD IS
PORT(D,CLK,RESET:IN BIT;Q,QINV:OUT BIT);
END ffD;
ARCHITECTURE behav OF ffD IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT;
IF(RESET='1') THEN Q<='0';QINV<='1';
ELSIF D='1' THEN Q<='1';QINV<='0';
ELSE Q<='0';QINV<='1';
END IF;
END PROCESS;
END behav;
5.21. What is an entity in VHDL? Give an example(Nov/Dec 2012)
Refer Q.No.3
5.22. Write the syntax for package declaration.(Nov/Dec 2012)
package_declaration ::=
PACKAGE identifier IS
package_declarative_part
END [ PACKAGE ] [ package_simple_name ] ;
5.23. What is a package in VHDL?(Nov/Dec 2012)
Refer Q.No.16
5.24. Write a VHDL code to realize of 2 x 1 multiplexer.(Nov/Dec 2012)
library ieee;
use ieee.std_logic_1164.all;
entity mux_2x1 is
port(d0,d1,s:in std_logic; z:out std_logic; z1,z2: inout std_logic);
end mux_2x1;
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23
architecture arc of mux_2x1 is

begin
z1 <= d0 and (not s);
z2 <= (d1 and s);
z <= z1 or z2;
end arc;

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SNS College of Technology, Coimbatore 35

Department of Electronics and Instrumentation Engineering

EI2403 VLSI Design 2 Marks

UNIT I BASIC MOS TRANSISTOR

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

1. Unit I - BASIC MOS TRANSISTOR

What are the two substructures of MOSFET?

What is the basic difference between JFET and MOSFET?

What are the limitations of scaling

Define threshold voltage Vt? How is it temperature dependent?

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

List the factors on which threshold voltage depends?

1.10. Name the different SPICE models for simulation.

1.13. Why is the calculation of sidewall capacitance complex?

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

1.17. Define Noise Margin. What is its effect?

1.20. How is the channel stop implant made?

1.19. What is a thinox?

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

1.25. Compare CMOS and Bipolar technologies. (Nov/Dec 2012)

1.24. What are the advantages of BiCMOS technology? (May/June 2012)

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

1.27. Compare Enhancement mode and depletion mode MOSFET(May/June 2012)

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

2. Unit II - NMOS AND CMOS INVERTER AND GATES

What is the use of layout design rules?

What are the issues addressed by design rules?

Define the two main approaches for describing design rules?

In a stick diagram, what indicates the formation of transistor or a switch ?

What is a pass transistor? What are its advantages?

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

Draw the monochrome stick diagram for NMOS inverter.

How is CMOS transmission gate superior to NMOS pass transistor?

2.12. List the advantages of generalized design rules in VLSI.

2.11. What is meant by scaling?

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

2.15. List the disadvantages of dynamic logic.

2.16. What is meant by domino logic?

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

2.24. Write the significance of based design rules. (Nov/Dec 2012)

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

3. Unit III - SUB-SYSTEM DESIGN AND LAYOUT

Define a data path.

What is meant by bit-sliced data path organization

What is the total time delay for a ripple carry Adder?

List the different considerations for designing a Ripple carry adder.

What are the draw backs of a static adder circuit?

Why is static adder circuit slow?

What is the advantage of Dynamic adder design?

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

What is a Manjestor carry chain adder?

3.10. Why is carry bypass Adder called so?

What is a booth multiplier?

3.16. What are the different applications of a Shifter?

3.18. List the advantages of two phase clocking scheme.(Nov 04)

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

SNSCT EIE | EI2403 VLSI Design 2 Marks Question and Answers

Give the difference between CPLD & FPGA.

Why is PLDs popular compared to ASICs.

List the basic steps in designing with an LCA.

Differentiate between PAL & PLA. (Nov 04)

4. UNIT IV - DESIGN OF COMBINATIONAL ELEMENTS AND

Draw the LCA realization of 1 bit shift register.