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CMOS Digital Integrated Circuits (Electronic Systems Design) EE-412

Objective
The goal of the course is to provide
fundamental understanding of digital circuit
techniques and integrated-circuit design
flow. This includes CMOS logic circuit
design and digital system implementation.
The course will cover from gate level
schematics to synthesis using RTL code and
timing verification.

Course Outline & Schedule


Content
1.

Prerequisites
Understanding of digital logic design
techniques, analog CMOS design & analysis
and semiconductor devices.
2.

Achievement
On successful completion of the course,
student will be able to synthesize and verify
basic digital building blocks for CMOS
integrated-circuits using professional tool
for ASICs and SoCs. Interested candidate
may proceed as digital or mixed-signal IC
design engineer with further understanding
and experience.

3.

Organization
Lectures and Laboratory work. All Labs
will be based on computer simulations.
Therefore ALL students MUST bring a
personal laptop computer with charged
battery for lab hours. Without laptop lab
cannot be performed.

Grading
Two written exams, one in mid of term (30
% weightage) and other at the end of term
(50 % weightage). Two quizzes, each of 10
% weightage. Labs will be graded based on
performance/understanding and completion
on the same day. Student need to pass both
theory AND lab. Failing in either will result
in course fail.

CMOS Inverter
Static Behavior
o Switching Threshold
o Noise Margin and Robustness
Dynamic Behavior
o Capacitances and Propagation
Delay
o Propagation Delay
Power & Energy
o Dynamic & Static Power
Consumption
Technology Scaling
Combinational CMOS Logic
Static Design
o Complementary CMOS
o Ratioed and Pass-Transistor
Logic
Dynamic Design
o Basic Principles, Speed and
Power
o Signal Integrity and Cascading
Sequential CMOS Logic
Timing Metrics and Memory Elements
Static Latches and Registers
o Bistability, Mux and EdgeTriggered
o Low Voltage and SR Flip Flop
Dynamic Latches and Registers
o Transmission-Gate Edge
Triggered
o C2MOS, TSPCR
Pipelining
Nonbistable Circuits

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System Perspective
4.

5.

Literature
Text Books:
1) Digital Integrated Circuits, A Design
Perspective, 2nd Edition
Jan M. Rabaey, A. Chandrakasan and B.
Nikolic.
2) Verilog HDL: A Guide to Digital Design
and Synthesis, 2nd Edition
Samir Palnitkar

Week

Circuit Perspective

6.

Implementation
Custom Circuit Design
Cell Based Design
Array Based Implementation
Synthesis
Register Transfer Logic
MID TERM EXAM
Interconnects (C, R and L)
Interconnect Technologies
Network on Chip
Timing
Classification of Interconnects
o Synchronous and Mesochronous
o Plesiochronous and
Asynchronous
Synchronous Design
o Skew and Jitter
o Clock Distribution
Self-Timed Design
o Asynchronous Logic

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Reference Books:
1) Digital Design and Verilog HDL
Fundamentals
Joseph Cavanagh
2) Digital Integrated Circuit Design Using
Verilog and Systemverilog
Ronald W. Mehler

Laboratory Arrangement
Tool: EDA custom IC software and RTL
compiler suit for synthesis, verification and
floor planning.
Lab Setup: Server based tool access via
VNC viewer.
Access: Remote desktop login using
personal laptop.

7.

Completion and Self-Timed


Signaling
Synchronizers and Arbiters
Clock Synthesis
Verification
Arithmetic Building Blocks
o Data Path in Digital Processors
o Adder, Multiplier and Shifter
o Power / Speed Trade-off
Memory and Array Structures
o Classification
o Architecture and Building
Blocks
o Memory Core and Peripheral
Circuitry
o Reliability and Power
Dissipation
FINAL EXAM

List of Laboratory Experiments


Experiments

Week

Custom Design
1.

2.

Lab 1
Inverter (Schematic / Layout / Parasitic Extraction)
Parameter and Performance Measurements
Lab 2
Logic Gates (Schematic / Layout / Parasitic Extraction)
Parameter and Performance Measurements

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Cell Based Design


3.

4.

5.

6.

Lab 3
Introduction to RTL
First Implementation
Lab 4
Synthesis using Standard Cell Library
Generate Schematic / Layout
Lab 5
Timing Verification
Interconnect Delays
Lab 6
Floor Planning
Place and Route

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