BFM2313 DIGITAL ELECTRONICS

ASSIGNMENT

Section

: 01

Name

: MOHAMAD RADZI B. MOHD SOJAK

METRIC NO.

: FB14009

LECTURER

: ZULKIFLI BIN MD. YUSOF

INTRODUCTION
Student require to use their identity card (IC) to produce the output and input.
There will be 4 input and 4 output in the truth table. Student also need to
simulate the output so that it will be match with the input and output in the truth
table. There will be 4 circuit AND OR, NAND-NAND, OR AND, and lastly NOR-NOR.
After produce each circuit it will need to be combine and the final output will be
shown in hexadecimal number.

Figure 1 IC number with the output wanted

As the result of the IC output, the truth table is prepared

THE FINAL
VALUE THAT IS
NOT INCLUDE
ARE NO 3, 4, 6
AND 8.

Figure 2 truth table for IC

Karnaugh map
A Karnaugh map provides a pictorial method of grouping together expressions
with common factors and therefore eliminating unwanted variables. The
Karnaugh map can also be described as a special arrangement of a truth table.
The diagram below illustrates the correspondence between the Karnaugh map
and the truth table for the general case of a two variable problem.

Figure 3 karnaugh map

K-Map, if properly used will produce the simplest SOP and POS expression
possible, known as the minimum expression.
Basic Gates and Functions
AND GATE
The AND gate is an
electronic circuit that gives
a high output (1) only if all
its inputs are high. A dot
(.) is used to show the
AND operation i.e. A.B.
Bear in mind that this dot
is sometimes omitted i.e. AB
Figure 4 AND Gate

OR GATE
The OR gate is an electronic circuit that gives a high output (1) if one or more of
its inputs are high. A plus (+) is used to show the OR operation.

Figure 5 OR Gate

NOT GATE
The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter. If the input variable is A, the
inverted output is known as NOT A. This is also shown as A', or A with a bar over
the top, as shown at the outputs. The diagrams below show two ways that the
NAND logic gate can be configured to produce a NOT gate. It can also be done
using NOR logic gates in the same way.

Figure 6 NOT
NAND GATE
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.
The outputs of all NAND gates are high if any of the inputs are low. The symbol is
an AND gate with a small circle on the output. The small circle represents
inversion.

Figure 7 NAND
NOT GATE
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.

Figure 8 NOR

Figure 11 AND OR

Figure 12 waveform for AND OR

Figure 15 OR AND

Figure 16 waveform for OR AND

Figure 17 NAND NAND

Figure 18 waveform for NAND NAND

Figure 20 NOR-NOR

Figure 21 waveform for NOR-NOR

Figure 22 combine circuit

Figure 23 waveform

DISCUSSION
After simulate all the circuit, there are some problem that happen to delay our
progress of work. But the problem has been solve after check all the circuit on
the quartus and calculation result. On the result of waveform there are some
delay that occur and glitch that appear.

Figure 24 Glitch on waveform from circuit NOR-NOR

On figure above is a timing glitch or race condition. There's a slight difference in
the time it takes for the a signal and the b signal to propagate through to the
output, so if they're both changed at the same time, you can see a very short
pulse at the output before it reaches the final state (which happens to be the
same as the initial state for this circuit).
CONCLUSION
Finally, there are still a lot more gate and function that can be found in quartus
altera. After completed the assignment, it is clear on how to circuit and the gate
or waveform function to one and another. By using karnaugh map we can plot
the simplest equation possible so that the circuit can be made easily.