Ex.

No:
Date:
Aim:

STUDY OF QUARTUS II TOOL

To study about the Quartus II software tool.

Procedure:
Step 1:- Open StartQuartus II 9.1 Web Edition and click on it.

Step 2: Quartus window opens. Then, click File New Project Wizard

Step 3: New Project Wizard opens. Click Next.

Step 4: Type the name of the project and click Next.

Step 5: Type the same name as given in the previous step and click Add.

Step 6: Then the file will be added to the project. Click Finish.

Step 7: Click File New.

Step 8: New window opens. Click on Verilog HDL File and click Ok.

Step 9: A Blank page will be opened. Type the program.

Step 10: Save the program by clicking FileSave. Type the name as given earlier.

Step 11 : Compile the program by clicking Compile Design in Task window.

Step 12: If the program has some errors, Correct the errors and compile again.

Step 13: If the program has no errors, program will be compiled successfully. Then click Ok.

Step 14: To give input, Click File New and select Vector Waveform File.

Step 15: Waveform window will be opened and double click on the empty space as given
below.

Step 16:Insert Node window will be opened.Type the input and output name as given in the
program and click ok.

Step 17:Assign the input value as 1or 0 or CLOCK.

Step 18:Save the waveform file with different name.

Step 19:Click Processing Simulator tool.

Step 20:Simulator Tool window will be opened.

Step 21: select functional simulation mode.

Step 22: Click the browse button.

Step 23: Select the input file and click open.

Step 24: Click on the generate functional simulation netlist icon.

Step 25: Netlist is generated successfully and click Ok.

Step 26: Click on start icon.

Step 27: Program is simulated successfully and click ok.

Step 28: Click on Report icon.

Step 29: Output is displayed on the window.

Result:
Thus, the Quartus II software is studied.

LOGIC DIAGRAM:
AND:

Truth Table:
A

OR:
Truth Table:
A

NOT:
TruthTable:

NAND:

0
Truth Table:

Date:

Ex.No:

HDL CODE TO REALIZE ALL LOGIC GATES

AIM:
To develop the source code for logic gates by using VERILOG and obtain the simulation ,synthesis,place
and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
module logicgates(a,b,c);
input a,b;
output [6:0]c;
assign c[0]=a&b;
assign c[1]=a|b;
assign c[2]=~(a&b);
assign c[3]=~(a|b);
assign c[4]=a^b;
assign c[5]=~(a^b);
assign c[6]=~a;
endmodule

LOGIC DIAGRAM:

NOR:

Truth Table:
A

XOR:

Truth Table:
A

XNOR:

Truth Table:
A

Output:

RESULT:
Thus output of all logic gates are verified by synthesizing and simulating the verilog code.

LOGIC DIAGRAM:

Half adder:

Truth Table:
A

Full adder:

Truth Table:
A

Co

Ex.No:
Date:

DESIGN OF ADDER AND SUBTRACTOR

AIM:
To develop the source code for an half & full adder, half & full subtractor by using VERILOG and obtain
the simulation, synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
Half Adder:
module halfadder(s,c,a,b);
output s,c;
input a,b;
reg s,c;
always @(a&b)
begin
s=a^b;
c=a*b;
end
endmodule
Full Adder:
module fulladder(s,c,x,y,z);
output s,c;
input x,y,z;
reg s,c;
always @(x&y&z)
begin
s=x^y^z;
c=z*(x^y)+x*y;
end

LOGIC DIAGRAM:

Half Subtractor:

Truth Table:
X

Full adder:

Truth Table:
X

end module
Full Subtractor:
module fullsub(d,b,a,p,c);
output d,b;
input a,p,c;
reg d,b;
always @(a&p&c)
begin
d=a^p^c;
b=~a*(p^c)+p*c;
end
endmodule
Half Subtractor:
module halfsub(d,b,x,y);
output d,b;
input x,y;
reg d,b;
always @(x&y)
begin
d=x^y;
b=~x*y;
end
endmodule

Output:
Half Adder:

Full Adder:

Half Subtractor:

Full Subtractor:

RESULT:
Thus output of half & full adder, half & full subtractor are verified by synthesizing and simulating the
verilog code.

LOGIC DIAGRAM:
4 to 2 Encoder:-

8 to 3 Encoder:-

Truth Table:
D0

D1

D2

D3

I0 I1 I2 I3 I4 I5 I6 I7 Y0 Y1 Y2
1

Truth Table:

Ex.No:
Date:

DESIGN OF ENCODER

AIM:
To develop the source code for 4 to 2 encoder and 8 to 3 encoder by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:

4 to 2 Encoder:module encodertwo(d,a,b);
input[3:0]d;
output a,b;
reg a,b;
always@(d[3:0])
begin
a=d[2]|d[3];
b=d[1]|d[3];
end
endmodule

8 to 3 Encoder:module encoder(d,a,b,c);
input [7:0]d;
output a;
output b;
output c;
reg a,b,c;
always @(d[7:0])
begin
a=d[4]|d[5]|d[6]|d[7];
b=d[2] |d[3]|d[6]|d[7];
c=d[1]|d[3]|d[5]|d[7];
end
endmodule

Output:
4 to 2 Encoder:-

8 to 3 Encoder:-

RESULT:
Thus output of 8 to 3 encoder are verified by synthesizing and simulating the verilog code.

LOGIC DIAGRAM:
2 to 4 Decoder:

Truth Table:

Y0

Y1

Y2

Y3

3 to 8 Decoder:

Truth Table:

X0 X1 X2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Ex.No:

Date:

DESIGN OF DECODER

AIM:
To develop the source code for 2 to 4 decoder and 3 to 8 decoder decoder by using VERILOG and obtain
the simulation, synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
module decoder(a,b,en,z);
input a,b,en;
output [3:0]z;
reg [3:0]z;
reg abar,bbar;
always @(a,b,en) begin
abar=~a;
bbar=~b;
z[0]=(abar&bbar&en);
z[1]=(abar&b&en);
z[2]=(a&bbar&en);
z[3]=(a&b&en);
end
endmodule

3 to 8 Decoder:module decoderthree(z,a,b,c);
input a,b,c;
output[7:0]z;
reg[7:0]z;
reg abar,bbar,cbar;
always@(a or b or c)
begin
abar=~a;
bbar=~b;
cbar=~c;

Output:

2 to 4 Decoder:-

z[0]=(abar&bbar&cbar);
z[1]=(abar&bbar&c);

z[2]=(abar&b&cbar);
z[3]=(abar&b&c);
z[4]=(a&bbar&cbar);
z[5]=(a&bbar&c);
z[6]=(a&b&cbar);
z[7]=(a&b&c);
end
endmodule

3 to 8 Decoder:-

RESULT:
Thus output of 2 to 4 decoder are verified by synthesizing and simulating the verilog code.

LOGIC DIAGRAM:

Multiplexer:-

Truth Table:
Input

Demultiplexer:-

Output

D0

D1

D2

D3

Truth Table:

Input

Output

X0

X1

Y0

Y1

Y2

Y3

Ex.No:
Date:

DESIGN OF MULTIPLEXER & DEMULTIPLEXER

AIM:
To develop the source code for multiplexer & demultiplexer by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
Multiplexer:
module mux(d,s0,s1,y);
input [3:0]d;
input s0;
input s1;
output y;
reg y;
reg s0bar,s1bar;
reg p,q,r,s;
always @(d&s0&s1)
begin
s0bar=~s0;
s1bar=~s1;
p=(d[0]&s0bar&s1bar);
q=(d[1]&s0bar&s1);
r=(d[2]&s0&s1bar);
s=(d[3]&s0&s1);
y=p|q|r|s;
end
endmodule

Output:
Multiplexer:-

Demultiplexer:
module demux(s0,s1,d,e,y);
input s0,s1;
input d,e;
output [3:0]y;
reg [3:0]y;
reg s0bar,s1bar;
always @(d or s0 or s1)
begin
s0bar=~s0;
s1bar=~s1;
y[0]=(d&s0bar&s1bar&e);
y[1]=(d&s0bar&s1&e);
y[2]=(d&s0&s1bar&e);
y[3]=(d&s0&s1&e);
end
endmodule

Demultiplexer:-

RESULT:
Thus output of multiplexer & demultiplexer are verified by synthesizing and simulating the verilog
code.

LOGIC DIAGRAM:

4-Bit binary to gray converter:

Truth Table:
BCD

GRAY

Ex.No:
Date:

DESIGN OF 4 BIT BINARY TO GRAY CONVERTER

AIM:
To develop the source code for 4 bit binary to gray converter by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
module b2g(b,g);
input [3:0]b;
output [3:0]g;
reg [3:0]g;
always @(b)
begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

Output:

RESULT:
Thus output of 4 bit binary to gray converter are verified by synthesizing and simulating the verilog
code.

LOGIC DIAGRAM:

Q(t)

Q(t+1)

SR Flip Flop:

States

Truth Table:

Input

Previous
Qn
0

Present
Qn+1
0

The characteristic equation is

Qn+1=Qn+S

Ex.No:
Date:

DESIGN OF FLIPFLOPS (SR, JK, D)

AIM:
To develop the source code for flipflops (SR,JK,D) by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
SR flipflop:
module srflipflop(s,r,clk,rst,q,qbar);
input s,r,clk,rst;
output q,qbar;
reg q,qbar;
always @(posedge(clk) or posedge(rst))
begin
if(rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if(s==1'b0&&s==1'b1)
begin

q=q;

Q(t)

Q(t+1)

else

begin

q=1'b0;

end

JK Flip Flop:
Truth Table:

States

Input

Previous
Qn
0

Present
Qn+1
0

qbar=qbar;

if(s==1'b0&&r==1'b1)

qbar=1'b1;

The characteristic equation is

Qn+1=JQn+KQn

end
else if(s==1'b1&&r==1'b0)
begin
q=1'b1;
qbar=1'b0;
end
else
begin
q=1'bx;
qbar=1'bx;
end
end
endmodule
JK flipflop:
module jkflipflop(j,k,clk,rst,q,qbar);
input j,k,clk,rst;
output q,qbar;
reg q,qbar;
always @(posedge(clk) or posedge(rst))
begin
if(rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if(j==1'b0&&k==1'b0)
begin
q=q;
qbar=qbar;
end

D Flip Flop:
Truth Table:

States

Q(t)

Q(t+1)

Input

Previous
Qn
0

Present
Qn+1
0

The characteristic equation is

Qn+1=D

else if(j==1'b0&&k==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if(j==1'b1&&k==1'b0)
begin
q=1'b1;
qbar=1'b0;
end
else
begin
q=~q;
qbar=~qbar;
end
end
endmodule
D flipflop:
module dflipflop(d,clk,rst,q,qbar);
input d,clk,rst;
output q,qbar;
reg q,qbar;
always @(posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if(d==1'b0)

Output:
SR Flip Flop:-

begin
q=1'b0;
qbar=1'b1;
end
else
begin
q=1'b1;
qbar=1'b0;
end
end
endmodule

JK Flip Flop:-

D Flipflop:

RESULT:
Thus outputs of flipflops (SR, JK, D) are verified by synthesizing and simulating the verilog code.

LOGIC DIAGRAM:

2 bit Counter:-

Ex.No:
DESIGN OF 2-BIT COUNTER & REGISTER

Date:
AIM:

To develop the source code for 2-bit counter & register by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
2-bit Counter:
module count2bit(clock,clear,out);
input clock,clear;
output [1:0]out;
reg [1:0]out;
always @(posedge clock,negedge clear)
if ((~clear)||(out>=4))
out=2'b00;
else
out=out+1;
endmodule
2-bit Register:
module reg2bit(clock,clear,in,out);
input clock,clear;
output [0:1]out;
reg [0:1]out;
input [0:1]in;
always @(posedge clock,negedge clear)
if (~clear)
out=2'b00;

Output:
2 bit Counter:-

else
out=in;
endmodule

Output:
2 bit Register:-

RESULT:
Thus outputs of 2-bit counter & register are verified by synthesizing and simulating the verilog code.

LOGIC DIAGRAM:
RIPPLE CARRY ADDER:-

Ex.

No:
Date:

DESIGN OF RIPPLE CARRY ADDER

AIM:
To develop the source code for Ripple carry adder by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.
SOFTWARE REQUIRED:
Quartus II 9.1 web edition
PC
VERILOG SOURCE CODE:
module ripplecarryadder(s,cout,a,b,cin);
output [7:0]s;
output cout;
input [7:0]a,b;
input cin;

wire c1,c2,c3,c4,c5,c6,c7;
fulladd fao(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule
module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin;
wire s1,c1,c2;
xor(s1,a,b);

Output:

xor(s,s1,cin);
and(c1,a,b);
and(c2,s1,cin);
xor (cout,c2,c1);
endmodule

module sr(s,r,clk,rst,q,qbar);

RESULT:
Thus outputs of ripple carry adder are verified by synthesizing and simulating the verilog code.