0e82b Compal LA-9001P

A
Compal Confidential
2
VIUS5 LA-9001P M/B Schematics Document

AMD FP2 Processor with DDRIII + Husdon M3 FCH
AMD VGA Seymour XT
2012-05-31
www.qdzbwx.com
REV:0.3
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/01/15
2013/01/15
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Page
Rev
0.3
VAUS5 LA9001P M/B
Date:
Thursday, May 31, 2012
Sheet
E
of
50
Compal confidential
File Name :
AMD Seymour XT
VRAM
128x16, 64x16
DDR3 x 4
PCIE x 8
Gen2
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X 1
AMD FP2 APU
Dual Channel
page 15,~21
DP Port0
LVDS
translator
DP Port2
HDMI Conn.
RTD2132S
page 22
page 24
Trinity
BGA 813 pin
27mm x 30mm
page 5,~8
4 * x1 PCI-E 2.0
LVDS Conn.
page 9
BANK 0, 1
1.5V DDRIII 1333MT/s

Upgradeable to 4G Memory
2Channel Speaker
x4 UMI Gen. 1
2.5GT/s per lane
page 30
GPP0
page 23
Single Digital MIC
LAN(10/100/Giga)
Realtek
8105E-VD (10/100)
8111F-CGT (Giga)
IO Board
Hudson M3
page 26
RealTek
ALC259-VC2
uFCBGA-656
24.5mm x 24.5mm
Audio Combo Jack

(APPLE type)
page 30
Stereo
HeadPhone Output
Microphone Input
1*USB3.0,6*USB2.0
RJ45 CONN
page 27
WLAN
3
1*SATA serial
CMOS Camera page 23

USB PORT 3.0 x1(Left)
USB(reserve for WiMAX)
LPC BUS
PCI-E(WLAN)
page 25
PCI Express
Mini card Slot 2
SPI ROM
page 11
SATA(SSD)
page 32
IO Board
page 10,~14
PCI Express
Mini card Slot 1
page 32
Audio Codec
AZALIA
page 33
Card Reader RTS 5178 (2in1)
EC
page 32
IO Board
3
USB PORT 2.0 x2(Right)
ENE KB9012
page 31
page 32
IO Board
Sub-borad
Int.KBD
page 32
POWER Board
Touch Pad
LED Board
page 32
SATA1
IO Board
SATA2.0 HDD CONN

page 29
Thermal Sensor
page 28
Compal Secret Data
2012/01/15
Issued Date
2013/01/15
Deciphered Date
Title
Size
Date:

MB Block Diagram
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Friday, May 25, 2012
Sheet
E
of
50
www.qdzbwx.com
page 25
Voltage Rails
+3VS
+1.5VS
+1.2VS
+1.1VS
+1.5V
+5VALW
+B
+APU_CORE
+3VALW
State
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
SMB_EC_CK2_SUS
SMB_EC_DA2_SUS
FCH_SCLK0
FCH_SDATA0
SMB_EC_CK2
SMB_EC_DA2
+3VS
X
X
X
KB9012
+3VALW
KB9012
+3VALW
FCH
ON
ON
LOW
S3 (Suspend to RAM)
HIGH
HIGH
ON
ON
OFF
OFF
HIGH
ON
OFF
OFF
LOW
ON
OFF
OFF
LOW
S5 (Soft OFF)
LOW
PCB Revision
ID
0.3
USB Port Table
USB 2.0 USB 3.0
KB9012
V
X
X
X
X
X
+3VALW
X
X
V
+3VS
Thermal
Sensor
FCH
X
X
V
+3VS
X
X
X
X
X
X
X
APU
X
V
+1.5V
X
X
XHCI
Rb
Vab
0V
R03 PVT
100K
8.2K
0.25V
R02 DVT
100K
18K
0.5V
R01 EVT
100K
33K
0.82V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
USB Port (Right Side 1)

USB Port (Right Side 2)
Mini Card(WLAN)
Camera
CardReader
USB Port (Left Side)
USB OC MAPPING
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
0001 011X b
Thermal Sensor
1001_101xb
SB-TSI(default)
1001_100xb
VGA(thermal)
1000_001xb
RTD2132S
1010_1000b
FCH SM Bus address

Device
Address
DDR DIMM1
1001 000Xb
USB20 port10
USB30 port0
USB20 port0 port1
APU PCIE PORT LIST

Port
1
2
3
4
USB Port
0
1
2
3
Device
FCH PCIE PORT LIST

Port
Device
BOM Structure
A4R1@
A4R3@
A6R1@
A6R3@
A8R1@
A8R3@
A10R1@
A10R3@
SXTR1@
SXTR3@
A70MR1@
A70MR3@
PX@
CMOS@
UMA@
GAS@
8105@
GIGA@
HDMI@
NONAOAC@
AOAC@
ME@
DEBUG@
@
SSD@
BTO Item
A4 BGA APU (R1 compal part)
Seymour XT GPU (R1 compal part)
Seymour XT GPU (R3 compal part)
A70 Hudson M3 FCH (R1 compal part)
A70 Hudson M3 FCH (R3 compal part)
Common VGA circuit
CMOS Camera part

UMA strap pin
Gastube
RTL8105E
RTL8111F
HDMI part
No AOAC function
support AOAC function
ME part
Debug Switch (MP will remove)
Unpop
SSD part
1
2
3
4
LAN
WLAN
Compal Secret Data
Issued Date
Ra = R1562
Rb = R1564
BOM Structure Table
4 External
USB Port
Port
RTD2132
X
X
X
Ra
x
R10 MP
WLAN
SODIMM WWAN
BRD ID
OC#
EC SM Bus1 address
OFF
Board ID / SKU ID Table for AD channel
BATT
OFF
2012/01/15
2013/01/15
Deciphered Date
Title
Custom
Notes List
Rev
0.3
VAUS5 LA9001P M/B
Date:
Tuesday, May 29, 2012
Sheet
E
www.qdzbwx.com
+3VS
(LV shifter)
ON
ON
VGA
KB9012
ON
ON
SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1
ON
HIGH
SOURCE
HIGH
HIGH
Board ID
0
1
2
3
4
5
6
7
+1.0VGS
Clock
HIGH
BOARD ID Table
+3.3VGS
+1.5VGS
S3
+VS
+VGA_CORE
+1.8VGS
+V
+APU_CORE_NB
+1.1VALW
S0
+VALW
S1(Power On Suspend)
S4 (Suspend to Disk)
+0.75VS
+1.5V_APU
SLP_S3# SLP_S5#
Full ON
+2.5VS
power
plane
SIGNAL
STATE
+5VS
of
50
Without BACO option :
Power-Up/Down Sequence
PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation

PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
"Thames" has the following requirements with regards to power-supply sequencing

to avoid damaging the ASIC:
All the ASIC supplies, except for VDDR3, must fully reach their respective
nominal voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the
ramp up of VDDR3 relative to other power rails.
The external pull-up resistors on the DDC/AUX signals (if applicable) should
ramp up before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO
enabled designs, VDDC must ramp up before VDD_CT at system power up.
For power down, reversing the ramp-up sequence is recommended
BACO option :
PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
VDDR3(3.3VGS)
dGPU Power Pins
Voltage
PX 3.0
BACO Mode Max current
PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,

DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18
1.8V
OFF
ON
1679mA
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and

SPV10
1.0V
OFF
ON
775mA
PCIE_VDDC
1.0V
OFF
ON
1.1A
VDDR3
3.3V
OFF
ON
60mA
BIF_VDDC (current consumption = 55mA@1.0V, in

BACO mode)
Same as
VDDC
OFF
ON
Same as
PCIE_VDDC
70mA
VDDR1
1.5V
OFF
OFF
1.2A
VDDC/VDDCI
TBD
OFF
OFF
28
PCIE_VDDC(1.0V)
VDDR1(1.5VGS)
2
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PERSTb
REFCLK
Straps Reset
Straps Valid
3
Global ASIC Reset
PX5.0
less than 20ms (Seymour)
T4+16clock
iGPU
PE_GPIO0(PXS_RST#)
+VGA_CORE
dGPU
BIF_VDDC
PE_GPIO1(PXS_PWREN)
+1.5V_IO
+5VLAW
PWM
Regulator
+1.0VGS
+1.8VGS
2012/01/15
Deciphered Date
2013/01/15
A
B+
+B
Compal Secret Data
Issued Date
Short PX_MODE and PX_PWREN
+3.3VGS
MOS
Title
+1.5VGS
Regulator
Regulator
+VGA_CORE

VGA Notes List
Size
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Date:
www.qdzbwx.com
+3.3VALW
Sheet
E
of
50
<15>
PCIE_CRX_GTX_P[0..7]
PCIE_CTX_GRX_P[0..7]
<15>
<15>
PCIE_CRX_GTX_N[0..7]
PCIE_CTX_GRX_N[0..7]
<15>
AH5
AH6
AG5
AG6
AE6
AE5
AD6
AD5
PCIE_CRX_DTX_P0
PCIE_CRX_DTX_N0
PCIE_CRX_DTX_P1
PCIE_CRX_DTX_N1
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
AM10
AN10
AN8
AM8
AP8
AR8
AR7
AP7
UMI_RXP0
UMI_RXN0
UMI_RXP1
UMI_RXN1
UMI_RXP2
UMI_RXN2
UMI_RXP3
UMI_RXN3
+1.2VS
P_GPP_RXP[0]
P_GPP_RXN[0]
P_GPP_RXP[1]
P_GPP_RXN[1]
P_GPP_RXP[2]
P_GPP_RXN[2]
P_GPP_RXP[3]
P_GPP_RXN[3]
1
R1
2 P_ZVDDP
196_0402_1%
P_UMI_RXP[0]
P_UMI_RXN[0]
P_UMI_RXP[1]
P_UMI_RXN[1]
P_UMI_RXP[2]
P_UMI_RXN[2]
P_UMI_RXP[3]
P_UMI_RXN[3]
AR11
GPP
<26>
<26>
<25>
<25>
P_GFX_RXP[0]
P_GFX_RXN[0]
P_GFX_RXP[1]
P_GFX_RXN[1]
P_GFX_RXP[2]
P_GFX_RXN[2]
P_GFX_RXP[3]
P_GFX_RXN[3]
P_GFX_RXP[4]
P_GFX_RXN[4]
P_GFX_RXP[5]
P_GFX_RXN[5]
P_GFX_RXP[6]
P_GFX_RXN[6]
P_GFX_RXP[7]
P_GFX_RXN[7]
P_GFX_RXP[8]
P_GFX_RXN[8]
P_GFX_RXP[9]
P_GFX_RXN[9]
P_GFX_RXP[10]
P_GFX_RXN[10]
P_GFX_RXP[11]
P_GFX_RXN[11]
P_GFX_RXP[12]
P_GFX_RXN[12]
P_GFX_RXP[13]
P_GFX_RXN[13]
P_GFX_RXP[14]
P_GFX_RXN[14]
P_GFX_RXP[15]
P_GFX_RXN[15]
UMI
AP1
AP2
AM1
AM2
AK3
AK4
AJ1
AJ2
AH4
AH3
AF2
AF1
AD1
AD2
AB3
AB4
AA1
AA2
Y4
Y3
V2
V1
T1
T2
P3
P4
N1
N2
M4
M3
K2
K1
GRAPHICS
UCPU1A
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
P_GFX_TXP[0]
P_GFX_TXN[0]
P_GFX_TXP[1]
P_GFX_TXN[1]
P_GFX_TXP[2]
P_GFX_TXN[2]
P_GFX_TXP[3]
P_GFX_TXN[3]
P_GFX_TXP[4]
P_GFX_TXN[4]
P_GFX_TXP[5]
P_GFX_TXN[5]
P_GFX_TXP[6]
P_GFX_TXN[6]
P_GFX_TXP[7]
P_GFX_TXN[7]
P_GFX_TXP[8]
P_GFX_TXN[8]
P_GFX_TXP[9]
P_GFX_TXN[9]
P_GFX_TXP[10]
P_GFX_TXN[10]
P_GFX_TXP[11]
P_GFX_TXN[11]
P_GFX_TXP[12]
P_GFX_TXN[12]
P_GFX_TXP[13]
P_GFX_TXN[13]
P_GFX_TXP[14]
P_GFX_TXN[14]
P_GFX_TXP[15]
P_GFX_TXN[15]
P_GPP_TXP[0]
P_GPP_TXN[0]
P_GPP_TXP[1]
P_GPP_TXN[1]
P_GPP_TXP[2]
P_GPP_TXN[2]
P_GPP_TXP[3]
P_GPP_TXN[3]
P_UMI_TXP[0]
P_UMI_TXN[0]
P_UMI_TXP[1]
P_UMI_TXN[1]
P_UMI_TXP[2]
P_UMI_TXN[2]
P_UMI_TXP[3]
P_UMI_TXN[3]
P_ZVDDP
P_ZVSS
TRINITY-A8-SERIES_BGA813
Compensation Resistor to VDDP
AN1
AN2
AM4
AM3
AK2
AK1
AH1
AH2
AF3
AF4
AE1
AE2
AD4
AD3
AB2
AB1
Y1
Y2
V3
V4
U1
U2
T4
T3
P2
P1
M1
M2
K3
K4
J1
J2
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
AG7
AG8
AE7
AE8
AD7
AD8
AB6
AB5
PCIE_CTX_C_DRX_P0
PCIE_CTX_C_DRX_N0
PCIE_CTX_C_DRX_P1
PCIE_CTX_C_DRX_N1
AN6
AM6
AP6
AR6
AP4
AR4
AP3
AR3
UMI_TXP0_C
UMI_TXN0_C
UMI_TXP1_C
UMI_TXN1_C
UMI_TXP2_C
UMI_TXN2_C
UMI_TXP3_C
UMI_TXN3_C
AP11
P_ZVSS
1
R2
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C33
C34
C35
C36
1
1
1
1
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C37
C38
C39
C40
C41
C42
C43
C44
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_DRX_P0 <26>
PCIE_CTX_DRX_N0 <26>
PCIE_CTX_DRX_P1 <25>
PCIE_CTX_DRX_N1 <25>
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
UMI_TXP0
UMI_TXN0
UMI_TXP1
UMI_TXN1
UMI_TXP2
UMI_TXN2
UMI_TXP3
UMI_TXN3
LAN
WLAN
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
2
196_0402_1%
Compensation Resistor to VSS
A8R3@
All power supplies in Power Sequencing Group A must be stable and within specification before
any power supply in Power Sequencing Group B is greater than 10 percent of its specified typical
operating value.
All power supplies in Power Sequencing Group B must be stable and within specification one ms
before the assertion of PWROK.
Power Sequence of APU

+1.5V (+1.5V_APU)
+2.5VS (+APU_VDDA)
UCPU1
A4R3@
UCPU1
A6R3@
UCPU1
A10R3@
Group A
ZZZ1
+1.5VS
A4 SERIES ZM198169E2351 1.9G BGA813
A6 SERIES ZM212169E2451 2.1G BGA813
A10 SERIES ZM202268E4451 2G BGA813P
LA9001P
+APU_CORE
DA60000TW00
UCPU1
A4R1@
UCPU1
A6R1@
UCPU1
A10R1@
Group B
+APU_CORE_NB
A4 SERIES AM4355SHE23HJ 1.9G BGA813

UCPU1
A6 SERIES AM4455SHE24HJ 2.1G BGA813 A10 SERIES AM4655SIE44HJ 2G BGA813P
+1.2VS
A8R1@
2012/01/15
Issued Date
A8 SERIES AM4555SHE44HJ 1.6G BGA813
Compal Secret Data
2013/01/15
Deciphered Date
Title
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
FP2 PCIE/UMI
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
of
50
www.qdzbwx.com
No sequencing relationships are required between the power sequencing groups during S3 entry.
DDR3 compatible processors require VDDIO to remain powered and within specification during the
S3 sleep state. All other processor power supply planes are powered down during S3.
UCPU1B
<9>
DDRA_SMA[15..0]
<9>
<9>
<9>
<9>
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM[7..0]
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
<9>
<9>
<9>
<9>
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
<9>
<9>
DDRA_CKE0
DDRA_CKE1
<9>
<9>
DDRA_ODT0
DDRA_ODT1
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
AA28
R29
T30
R28
R26
P26
P27
P30
P29
M28
AB26
M26
M29
AE27
L26
L27
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
AB27
AA29
M30
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
D16
D20
E25
F30
AK29
AL25
AM20
AM16
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
G17
H17
F22
G22
E26
F26
H30
G30
AL29
AL30
AH25
AJ25
AK20
AL20
AK15
AL15
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
W29
Y30
W26
W27
U29
V30
U26
U27
DDRA_CKE0
DDRA_CKE1
L29
K30
DDRA_ODT0
DDRA_ODT1
AD30
AG28
AE26
AG29
DDRA_SCS0#
DDRA_SCS1#
<9>
<9>
<9>
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
<9>
<9>
MEM_MA_RST#
MEM_MA_EVENT#
DDRA_SCS0#
DDRA_SCS1#
AD26
AE29
AB30
AF30
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
AB29
AD29
AD28
MEM_MA_RST#
MEM_MA_EVENT#
J28
AA26
G32
+MEM_VREF
+1.5V_APU
15mil
1
R3
2 M_ZVDDIO
39.2_0402_1%
Place them close to APU within 1"
AJ32
MA_ADD[0]
MA_ADD[1]
MA_ADD[2]
MA_ADD[3]
MA_ADD[4]
MA_ADD[5]
MA_ADD[6]
MA_ADD[7]
MA_ADD[8]
MA_ADD[9]
MA_ADD[10]
MA_ADD[11]
MA_ADD[12]
MA_ADD[13]
MA_ADD[14]
MA_ADD[15]
MA_DATA[0]
MA_DATA[1]
MA_DATA[2]
MA_DATA[3]
MA_DATA[4]
MA_DATA[5]
MA_DATA[6]
MA_DATA[7]
MA_DATA[8]
MA_DATA[9]
MA_DATA[10]
MA_DATA[11]
MA_DATA[12]
MA_DATA[13]
MA_DATA[14]
MA_DATA[15]
MA_BANK[0]
MA_BANK[1]
MA_BANK[2]
MA_DATA[16]
MA_DATA[17]
MA_DATA[18]
MA_DATA[19]
MA_DATA[20]
MA_DATA[21]
MA_DATA[22]
MA_DATA[23]
MA_DM[0]
MA_DM[1]
MA_DM[2]
MA_DM[3]
MA_DM[4]
MA_DM[5]
MA_DM[6]
MA_DM[7]
MA_DATA[24]
MA_DATA[25]
MA_DATA[26]
MA_DATA[27]
MA_DATA[28]
MA_DATA[29]
MA_DATA[30]
MA_DATA[31]
MA_DQS_H[0]
MA_DQS_L[0]
MA_DQS_H[1]
MA_DQS_L[1]
MA_DQS_H[2]
MA_DQS_L[2]
MA_DQS_H[3]
MA_DQS_L[3]
MA_DQS_H[4]
MA_DQS_L[4]
MA_DQS_H[5]
MA_DQS_L[5]
MA_DQS_H[6]
MA_DQS_L[6]
MA_DQS_H[7]
MA_DQS_L[7]
MA_DATA[32]
MA_DATA[33]
MA_DATA[34]
MA_DATA[35]
MA_DATA[36]
MA_DATA[37]
MA_DATA[38]
MA_DATA[39]
MA_DATA[40]
MA_DATA[41]
MA_DATA[42]
MA_DATA[43]
MA_DATA[44]
MA_DATA[45]
MA_DATA[46]
MA_DATA[47]
MA_CLK_H[0]
MA_CLK_L[0]
MA_CLK_H[1]
MA_CLK_L[1]
MA_CLK_H[2]
MA_CLK_L[2]
MA_CLK_H[3]
MA_CLK_L[3]
MA_DATA[48]
MA_DATA[49]
MA_DATA[50]
MA_DATA[51]
MA_DATA[52]
MA_DATA[53]
MA_DATA[54]
MA_DATA[55]
MA_CKE[0]
MA_CKE[1]
MA0_ODT[0]
MA0_ODT[1]
MA1_ODT[0]
MA1_ODT[1]
MA_DATA[56]
MA_DATA[57]
MA_DATA[58]
MA_DATA[59]
MA_DATA[60]
MA_DATA[61]
MA_DATA[62]
MA_DATA[63]
MA0_CS_L[0]
MA0_CS_L[1]
MA1_CS_L[0]
MA1_CS_L[1]
MA_RAS_L
MA_CAS_L
MA_WE_L
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
G20
E20
H23
G23
E19
H20
E22
D22
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
H25
F25
D28
D29
E23
D24
D26
D27
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
G28
G29
H27
J29
E28
F27
H29
H28
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
AH29
AJ30
AM28
AM27
AH27
AH28
AJ29
AK27
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
AK26
AJ26
AK23
AJ23
AM26
AL26
AM24
AL23
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
AK22
AH22
AK19
AH19
AM22
AL22
AJ20
AL19
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
AK17
AJ17
AK14
AH14
AM18
AL17
AH15
AL14
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ[63..0]
<9>
Y33
R32
T31
P33
P32
P31
N32
M33
M32
L32
AB31
M31
K32
AF33
K33
J32
AB33
AA32
K31
C18
B23
C28
D31
AM31
AN30
AR24
AN18
B18
A18
B24
A24
B30
B29
D32
D33
AM32
AM33
AN28
AP29
AP23
AP24
AR18
AP18
W32
Y32
V33
V32
U32
V31
T33
T32
H32
H33
AF31
AH31
AE32
AH33
AD31
AF32
AC32
AG32
AB32
AD32
AD33
MA_RESET_L
MA_EVENT_L
H31
Y31
MEM_MB_EVENT#
MB_ADD[0]
MB_ADD[1]
MB_ADD[2]
MB_ADD[3]
MB_ADD[4]
MB_ADD[5]
MB_ADD[6]
MB_ADD[7]
MB_ADD[8]
MB_ADD[9]
MB_ADD[10]
MB_ADD[11]
MB_ADD[12]
MB_ADD[13]
MB_ADD[14]
MB_ADD[15]
MB_BANK[0]
MB_BANK[1]
MB_BANK[2]
MB_DM[0]
MB_DM[1]
MB_DM[2]
MB_DM[3]
MB_DM[4]
MB_DM[5]
MB_DM[6]
MB_DM[7]
MB_DQS_H[0]
MB_DQS_L[0]
MB_DQS_H[1]
MB_DQS_L[1]
MB_DQS_H[2]
MB_DQS_L[2]
MB_DQS_H[3]
MB_DQS_L[3]
MB_DQS_H[4]
MB_DQS_L[4]
MB_DQS_H[5]
MB_DQS_L[5]
MB_DQS_H[6]
MB_DQS_L[6]
MB_DQS_H[7]
MB_DQS_L[7]
MB_CLK_H[0]
MB_CLK_L[0]
MB_CLK_H[1]
MB_CLK_L[1]
MB_CLK_H[2]
MB_CLK_L[2]
MB_CLK_H[3]
MB_CLK_L[3]
MB_CKE[0]
MB_CKE[1]
MB0_ODT[0]
MB0_ODT[1]
MB1_ODT[0]
MB1_ODT[1]
MB0_CS_L[0]
MB0_CS_L[1]
MB1_CS_L[0]
MB1_CS_L[1]
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_DATA[0]
MB_DATA[1]
MB_DATA[2]
MB_DATA[3]
MB_DATA[4]
MB_DATA[5]
MB_DATA[6]
MB_DATA[7]
MB_DATA[8]
MB_DATA[9]
MB_DATA[10]
MB_DATA[11]
MB_DATA[12]
MB_DATA[13]
MB_DATA[14]
MB_DATA[15]
MB_DATA[16]
MB_DATA[17]
MB_DATA[18]
MB_DATA[19]
MB_DATA[20]
MB_DATA[21]
MB_DATA[22]
MB_DATA[23]
MB_DATA[24]
MB_DATA[25]
MB_DATA[26]
MB_DATA[27]
MB_DATA[28]
MB_DATA[29]
MB_DATA[30]
MB_DATA[31]
MB_DATA[32]
MB_DATA[33]
MB_DATA[34]
MB_DATA[35]
MB_DATA[36]
MB_DATA[37]
MB_DATA[38]
MB_DATA[39]
MB_DATA[40]
MB_DATA[41]
MB_DATA[42]
MB_DATA[43]
MB_DATA[44]
MB_DATA[45]
MB_DATA[46]
MB_DATA[47]
MB_DATA[48]
MB_DATA[49]
MB_DATA[50]
MB_DATA[51]
MB_DATA[52]
MB_DATA[53]
MB_DATA[54]
MB_DATA[55]
MB_DATA[56]
MB_DATA[57]
MB_DATA[58]
MB_DATA[59]
MB_DATA[60]
MB_DATA[61]
MB_DATA[62]
MB_DATA[63]
C16
B17
B20
C20
A16
B16
B19
A20
B22
C22
A26
B26
B21
A22
C24
B25
A28
B28
B31
A32
C26
B27
A30
C30
B33
C32
F33
F32
B32
C31
E32
F31
AK32
AL32
AP32
AN31
AK31
AK33
AN32
AP33
AP30
AR30
AP27
AN26
AR32
AP31
AR28
AP28
AP25
AN24
AR22
AP21
AP26
AR26
AN22
AP22
3
AR20
AP19
AP16
AR16
AN20
AP20
AP17
AN16
MB_RESET_L
MB_EVENT_L
M_VREF
M_ZVDDIO
A8R3@
A8R3@
0.75V reference voltage
+1.5V_APU
2
EVENT# pull high

+1.5V_APU
4
R4
1K_0402_1%
2 1K_0402_5% MEM_MA_EVENT#
R6 1
2 1K_0402_5% MEM_MB_EVENT#
15mil
1
R5 1
+MEM_VREF
1
R7
1K_0402_1%
1
2
C45
1000P_0402_50V7K
C46
0.1U_0402_16V7K
2012/01/15
Issued Date
Compal Secret Data
2013/01/15
Deciphered Date
Title
FP2 DDRIII Memory I/F
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
of
50
www.qdzbwx.com
<9>
<9>
UCPU1C
F15
E15
H19
F19
E14
H15
E17
D18
Place near APU
<10>
<10>
DP2_TXP2
DP2_TXN2
<24>
<24>
DP2_TXP3
DP2_TXN3
<10>
<10>
APU_CLK
APU_CLK#
APU_SVC
APU_SVD
<43>
APU_SVT
AL7
AK7
DISP_CLKIN_H
DISP_CLKIN_L
E5
E6
SVC
SVD
D6
AK11
AH9
APU_THERMTRIP#
ALERT_L
AL12
AK5
AR10
<43>
APU_VDD_SEN_L
<43>
APU_VDDNB_SEN_H
RESET_L
PWROK
PROCHOT_L
THERMTRIP_L
ALERT_L
E11
G11
H12
F11
H11
E8
E7
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L
G6
H6
H5
G7
G5
H7
APU_VDD_SEN_H
DMAACTIVE_L
TEST4
TEST5
RSVD
RSVD
RSVD
RSVD
RSVD
DP0_AUXP
R10
1 1.8K_0402_5%
DP0_AUXN
R11
1 1.8K_0402_5%
U5
U6
<24>
+1.5V_APU
+3VS
Asserted as an input to force the

processor into the HTC-active state
R12
1K_0402_5%
C6
D7
A6
DP_INT_PWM
B6
DP_AUX_ZVSS
AL6
Y23
V23
G9
F9
E9
G8
F12
E12
F14
G12
AJ8
AH8
G14
H14
V25
Y25
AH32
R25
T25
AL5
R15
R14
10K_0402_5%
@
<22>
2 150_0402_1%
Q1 @
1
APU_PROCHOT#
T1
T2
T3
T4
T5
T6
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST24
TEST25_H
TEST25_L
<22>
HDMI_DET
R13
10K_0402_5%
@
2
LVDS_HPD
M7
L7
J7
P7
R7
U7
+1.5V_APU
APU_TEST31
T19
T20
APU_TEST35
AP10
1
1
Indicates to the FCH that a thermal trip

has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately
THERMTRIP shutdown
temperature: 125 degree
2 510_0402_1%
2 510_0402_1%
+1.2VS
R19
1K_0402_5%
R21
R22
R23
1 HDMI@ 2 300_0402_5%
1
2 300_0402_5%
@
ALLOW_STOP
T23
R23
<31,36,43>
2
0_0402_5%
R16
R17
R18
T7
T8
T17
T18
H_PROCHOT#
MMBT3904_NL_SOT23-3
2 39.2_0402_1%
R20
10K_0402_5%
+1.5V_APU
APU_THERMTRIP#
Q2
1
C
APU_PROCHOT#
APU_PWRGD
SIC
SID
TEST6
TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST31
TEST32_H
TEST32_L
TEST35
R5
R6
APU_RST#
APU_PWRGD
SVT
AJ11
AH11
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
<43>
CLKIN_H
CLKIN_L
DP_AUX_ZVSS
To HDMI
<10>
DP2_TXP[3]
DP2_TXN[3]
AL9
AK9
APU_SIC
APU_SID
<10>
<10,43>
DP2_TXP[2]
DP2_TXN[2]
B5
A5
APU_DISP_CLK
APU_DISP_CLK#
<43>
<43>
DP2_TXP[1]
DP2_TXN[1]
B4
A4
DISPLAY PORT 2
<24>
<24>
B3
A3
DP_BLON
DP_DIGON
DP_VARY_BL
TEST
DP2_TXP1
DP2_TXN1
DP2_TXP[0]
DP2_TXN[0]
CLK
<24>
<24>
B2
A2
HDMI_CLK <24>
HDMI_DATA <24>
P5
P6
<10>
1
R24
2
0_0402_5%
H_THERMTRIP#
1
@ R25
2
0_0402_5%
MAINPWON
<12>
MMBT3904_NL_SOT23-3
T9
T10
<31,36,38>
L8
P8
AH12
AJ12
AK12
VSS_SENSE
VDDP_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDD_SENSE
VDDR_SENSE
SENSE
HDMI
DP2_TXP0
DP2_TXN0
DP1_TXP[3]
DP1_TXN[3]
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD
J5
J6
2 2
B
C1
C2
DP5_AUXP
DP5_AUXN
To LVDS
Translater
DP1_TXP[2]
DP1_TXN[2]
<22>
<22>
DP1_TXP[1]
DP1_TXN[1]
D1
D2
DP4_AUXP
DP4_AUXN
DP0_AUXP_C
DP0_AUXN_C
D4
D3
DISPLAY PORT 1
DP1_TXP[0]
DP1_TXN[0]
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
E2
E1
DP3_AUXP
DP3_AUXN
C49 1
C5088 1
DP0_TXP[3]
DP0_TXN[3]
DP2_AUXP
DP2_AUXN
DP0_AUXP
DP0_AUXN
L5
L6
2 2
F1
F2
DP1_AUXP
DP1_AUXN
M5
M6
DP0_TXP[2]
DP0_TXN[2]
DISPLAY PORT MISC.
DP0_TXP[1]
DP0_TXN[1]
F4
F3
DP0_AUXP
DP0_AUXN
DISPLAY PORT 0
DP0_TXP[0]
DP0_TXN[0]
H3
H4
<24>
<24>
H2
H1
SER.
2 0.1U_0402_16V7K DP0_TXP0
2 0.1U_0402_16V7K DP0_TXN0
CTRL
C47 1
C4888 1
DP0_TXP0_C
DP0_TXN0_C
JTAG
<22>
<22>
RSVD
LVDS
UCPU1D
Route as differential
with APU_VDD_SEN_L
A8R3@
+1.5V_APU
2 1K_0402_5%
ALLOW_STOP
2 1K_0402_5%
APU_SIC
R26
R28
2 1K_0402_5%
APU_SID
R31
2 1K_0402_5%
ALERT_L
CPU TSI interface level shift
HDT Debug conn
C5988 1
+3VS
1 R32
1 R33
31.6K_0402_1%
+1.5VS
2 0.1U_0402_16V4Z
BSH111, the Vgs is:

min = 0.4V
Max = 1.3V
JHDT1
1
3
5
30K_0402_1%
R40
ALLOW_STOP
2 300_0402_5%
APU_RST#
2 300_0402_5%
APU_PWRGD
APU_SID
APU_TRST#
Q3
1
D
2 1K_0402_5%
R38
7
R36
EC_SMB_DA2_SUS
<31>
To EC
R42
2 10K_0402_5%
11
R46
2 10K_0402_5%
13
R49
2 10K_0402_5%
15
BSH111 1N_SOT23-3
@
R45
R48
R50
2 1K_0402_5%
APU_SVT
2 1K_0402_5%
APU_SVC
2 1K_0402_5%
APU_SVD
17
Q4
19
@
3
APU_SIC
EC_SMB_CK2_SUS
<31>
+1.5V_APU
+1.5V_APU
To EC
10
11
12
13
14
15
16
17
18
19
20
APU_TCK
APU_TMS
APU_TDI
APU_TDO
10
APU_PWRGD
12
APU_RST#
14
APU_DBRDY
16
APU_DBREQ#
APU_DBREQ#
APU_TCK
APU_TMS
APU_TDI
APU_TDO
APU_TRST#
R27
R29
R30
R34
R35
R37
1
1
1
1
1
1
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST24
APU_DBRDY
R39
R41
R43
R44
R47
1
1
1
1
1
18
R51
1 0_0402_5% APU_TEST19
20
R52
1 0_0402_5% APU_TEST18
2
2
2
2
2
2
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
2
2
2
2
2
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
BSH111 1N_SOT23-3
SAMTE_ASP-136446-07-B
@
2012/01/15
Issued Date
Compal Secret Data
2013/01/15
Deciphered Date
Title
FP2 Display/MISC/HDT
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
of
50
www.qdzbwx.com
R215 1
UCPU1F
+APU_CORE
180P_0402_50V8J
180P_0402_50V8J
C108
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C107
C106
0.22U_0402_10V4Z
C105
0.22U_0402_10V4Z
C104
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C103
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C102
C101
C100
C99
C82
180P_0402_50V8J
330U_B2_2.5VM_R15M
180P_0402_50V8J
C81
180P_0402_50V8J
C80
180P_0402_50V8J
C79
C78
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C77
0.22U_0402_10V4Z
C76
C75
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C74
0.22U_0402_10V4Z
C73
C72
0.22U_0402_10V4Z
C71
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C70
C69
C68
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C67
C66
C65
C64
VDDP
180P_0402_50V8J
180P_0402_50V8J
C118
1000P_0402_50V7K
1000P_0402_50V7K
C117
C116
0.22U_0402_10V4Z
C115
0.22U_0402_10V4Z
+APU_VDDA
C129
1000P_0402_50V7K
3300P_0402_50V7-K
0.22U_0402_10V4Z
4.7U_0603_6.3V6K
C128
C114
FBMA-L11-201209-221LMA30T_0805
L1
1
C127
C126
180P_0402_50V8J
180P_0402_50V8J
C113
C94
C93
1000P_0402_50V7K
1000P_0402_50V7K
C92
0.22U_0402_10V4Z
C91
0.22U_0402_10V4Z
C90
4.7U_0603_6.3V6K
C89
4.7U_0603_6.3V6K
C88
C87
0.01U_0402_16V7K
180P_0402_50V8J
22U_0603_6.3V6M
C125
1
@ J5
+1.5V
+1.5V_APU
PAD-OPEN 4x4m
Need Short
Northbridge Power Pins

for Remote Decoupling
+1.2VS
22U_0603_6.3V6M
22U_0603_6.3V6M
C131
C130
close to APU
A8R3@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y11
Y12
Y14
Y15
Y17
Y19
Y20
Y22
AA4
AA5
AB7
AB8
AC1
AC2
AC4
AC9
AC11
AC12
AC14
AC15
AC17
AC19
AC20
AC22
AC23
AC25
AE4
AF9
AF11
AF12
AF14
AF15
AF17
AF19
AF20
AF22
AF23
AF25
AG1
AG2
AG4
AG9
AG11
AG26
AH7
AH17
AH20
AH23
AH26
AH30
AJ4
AJ5
AJ6
AJ7
AJ9
AJ14
AJ15
AJ19
AJ22
AJ27
AJ28
AJ33
AK6
AK8
AK25
AK28
AK30
AL1
AL2
AL4
AL8
AL11
AL27
AL28
AL33
AM5
AM7
AM9
AM11
AM15
AM17
AM19
AM21
AM23
AM25
AM29
AM30
AN3
AN4
AN33
AP5
AP9
AR2
AR5
AR9
AR17
AR19
AR21
AR23
AR25
AR27
AR29
AR31
A8R3@
2012/01/15
Issued Date
Compal Secret Data
2013/01/15
Deciphered Date
Title
FP2 PWR / GND

Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
of
50
www.qdzbwx.com
+VDDP_CAP
VDDP_CAP
VDDP_CAP
VDDA
VDDA
C86
0.01U_0402_16V7K
AN14
AP14
AP15
AR14
AR15
+1.5V_APU
22U_0603_6.3V6M
AM13
AM14
VDDR
VDDR
VDDR
VDDR
VDDR
+2.5VS
C124
+APU_VDDA
AA6
AA7
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
+VDDNB_CAP
22U_0603_6.3V6M
+VDDP_CAP
AM12
AN12
AP12
AP13
AR12
AR13
+1.2VS
+APU_CORE_NB
C123
+1.2VS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDR
22U_0603_6.3V6M
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
W33
AA23
AA25
AA27
AA30
AA33
AB28
AC30
AC33
AD23
AD25
AD27
AE28
AE30
AE33
AG23
AG25
AG27
AG30
AG33
+1.2VS
C122
+1.5V_APU
J33
K23
K25
L28
L30
L33
M27
N23
N25
N30
N33
P28
R27
R30
R33
U28
U30
U33
W28
W30
M9
N9
+1.5V
C121
VDDNB_CAP
VDDNB_CAP
B11
B12
B13
B14
B15
C8
C10
C12
C14
D8
D10
D12
D14
+1.5V_APU
C85
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
Decoupling between CPU and DIMMs

across VDDIO and VSS split
22U_0805_6.3V6M
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
V17
V19
V20
V22
W8
AA8
AA9
AA11
AA12
AA14
AA15
AA17
AA19
AA20
AA22
AD9
AD11
AD12
AD14
AD15
AD17
AD19
AD20
AD22
AG12
AG14
AG15
AG17
AG19
AG20
AG22
22U_0805_6.3V6M
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C63
A7
A8
A9
A10
A11
A12
A13
A14
A15
B7
B8
B9
B10
+APU_CORE_NB
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C62
+APU_CORE
UCPU1E
J12
J14
J15
J17
J19
J20
J22
M11
M12
M14
M15
M17
M19
M20
M22
R8
R9
R11
R12
R14
R15
R17
R19
R20
R22
U8
V9
V11
V12
V14
V15
A17
A19
A21
A23
A25
A27
A29
A31
B1
C3
C4
C33
D5
D9
D11
D13
D15
D17
D19
D21
D23
D25
D30
E4
E27
E29
E30
E33
F5
F6
F7
F8
F17
F20
F23
F28
F29
G1
G2
G4
G15
G19
G25
G26
G27
G33
H8
H9
H22
H26
J4
J8
J9
J11
J23
J25
J26
J27
J30
K9
K11
K12
K14
K15
K17
K19
K20
K22
L1
L2
L4
M8
M23
M25
N4
N11
N12
N14
N15
N17
N19
N20
N22
R1
R2
R4
T9
T11
T12
T14
T15
T17
T19
T20
T22
U4
W1
W2
W4
W5
W6
W7
Y9
+1.5V
+1.5V
+VREF_DQ
JDIMM1
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
<6>
<6>
DDRA_CKE0
DDRA_CKE0
DDRA_SBS2#
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
<6>
<6>
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK0
DDRA_CLK0#
<6>
DDRA_SMA10
DDRA_SBS0#
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
<6> DDRA_SWE#
<6> DDRA_SCAS#
<6>
DDRA_SMA13
DDRA_SCS1#
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
<6>
<6>
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
3
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
<6>
<6>
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R57 1
2 10K_0402_5%
+3VS
C145
2.2U_0603_6.3V6K
C146
0.1U_0402_16V4Z
R58
10K_0402_5%
2
1
4
205
207
GND1
BOSS1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
0.1U_0402_16V4Z
2
DDRA_SDM2
C132
C133
1
0.1U_0402_16V4Z
DDRA_SDQ22
DDRA_SDQ23
0.1U_0402_16V4Z
2
C134
C135
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C136
1
0.1U_0402_16V4Z
C137
1
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQS3# <6>
DDRA_SDQS3 <6>
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1
DDRA_CKE1
<6>
DDRA_SMA15
DDRA_SMA14
2
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
+1.5V
DDRA_CLK1 <6>
DDRA_CLK1# <6>
DDRA_SBS1#
DDRA_SRAS#
<6>
<6>
R53
1K_0402_1%
+VREF_DQ
15mil
DDRA_SCS0# <6>
DDRA_ODT0 <6>
DDRA_ODT1
+1.5V
<6>
+VREF_CA
DDRA_SDQ36
DDRA_SDQ37
+VREF_DQ
C138
DDRA_SDM4
C139
15mil
R55
1K_0402_1%
R54
1K_0402_1%
+VREF_CA
+VREF_CA
C140
C141
R56
1K_0402_1%
DDRA_SDQ38
DDRA_SDQ39
3
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
+0.75VS
DDRA_SDQS5# <6>
DDRA_SDQS5 <6>
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
C142
0.1U_0402_16V4Z
+1.5V
C143
4.7U_0603_6.3V6K
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
SGA00001700
DDRA_SDQS7# <6>
DDRA_SDQS7 <6>
DDRA_SDQ62
DDRA_SDQ63
MEM_MA_EVENT#
MEM_MA_EVENT# <6>
FCH_SDATA0 <12,25>
FCH_SCLK0 <12,25>
+0.75VS
206
208
GND2
BOSS2
LCN_DAN06-K4406-0103
ME@
<Address: 00>
2012/01/15
Issued Date
Compal Secret Data
Reverse Type H:4mm
2013/01/15
Deciphered Date
Title
DDRIII SO-DIMM 1
Rev
0.3
VAUS5 LA9001P M/B
Date:
C243
220U_B2_2.5VM_R35
DDRA_SDQ48
DDRA_SDQ49
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
Place near DIMM1
+1.5V
DDRA_SDQ20
DDRA_SDQ21
Sheet
E
of
50
www.qdzbwx.com
DDRA_SDQ42
DDRA_SDQ43
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
MEM_MA_RST# <6>
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDM1
MEM_MA_RST#
<6>
<6>
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ16
DDRA_SDQ17
<6>
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ10
DDRA_SDQ11
<6>
DDRA_SMA[0..15]
1000P_0402_50V7K
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SMA[0..15]
0.1U_0402_16V4Z
<6>
<6>
DDRA_SDQS0# <6>
DDRA_SDQS0 <6>
<6>
DDRA_SDM[0..7]
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ[0..63]
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ2
DDRA_SDQ3
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
DDRA_SDM0
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1000P_0402_50V7K
DDRA_SDQ0
DDRA_SDQ1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CLK_CALRN
G30
G28
DISP_CLKP
DISP_CLKN
H33
H31
VGA
R67
R68
<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
1
1
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R
APU_CLKP
APU_CLKN
J30
K29
SLT_GFX_CLKP
SLT_GFX_CLKN
H27
H28
GPP_CLK0P
GPP_CLK0N
J27
K26
WLAN
LAN
<25> CLK_PCIE_WLAN
<25> CLK_PCIE_WLAN#
<26> CLK_PCIE_LAN
<26> CLK_PCIE_LAN#
R69
R70
1
1
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R
F33
F31
R72
R74
1
1
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
E33
E31
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
M23
M24
GPP_CLK4P
GPP_CLK4N
M27
M26
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
R23
R24
GPP_CLK7P
GPP_CLK7N
N27
R27
GPP_CLK8P
GPP_CLK8N
@
<26>
R77
CLK_LAN_25M
2 22_0402_5%CLK_LAN_25M_R
25M_X1
25M_X2
J26
C31
25M_X1
C33
25M_X2
1
OSC
NC
OSC
NC
5
P
G
3
8.2K_0402_5%
C157
R64
1
EC
@
R217
10K_0402_5%
+3VS
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
<14>
<14>
<14>
<14>
<14>
UMA@
R146
10K_0402_5%
BOARD
Config.
GPIO31
GPIO31
Function
PX5
UMA
PX@
R152
10K_0402_5%
T11
T12
AF18
AE18
AC16
AD18
B25
R71
R73
D25
D27
C28
A26
A29
A31
B27
AE27
AE19
SERIRQ
G25
E28 APU_PROCHOT#_R
E26 APU_PWRGD_R
G26
F26
H7
F1
F3
E6
1
1
2 22_0402_5%
2 0_0402_5%
CLK_PCI_EC
CLK_PCI_DB
<14,31>
<25>
LPC_CLK1 <14>
LPC_AD0 <25,31>
LPC_AD1 <25,31>
LPC_AD2 <25,31>
LPC_AD3 <25,31>
LPC_FRAME# <25,31>
R75
R76
<31>
1
1
APU_RST#
ALLOW_STOP <7>
APU_PROCHOT# <7>
APU_PWRGD <43,7>
2 0_0402_5%
2 0_0402_5%
<7>
+RTCBATT
RTC_CLK
<14,31>
1
W=20mils
R78
G2
32K_X1
G4
32K_X2
18P_0402_50V8J
2
C158 1
32K_X1
+RTCBATT_R
2
510_0402_5%
1
C159
2
CLRP1 @
SHORT PADS
32.768KHZ_12.5PF_CM31532768DZFT
Y1
Need OPEN
R79
20M_0402_5%
C161 1
32K_X2
18P_0402_50V8J
Close to HUDSON-M3
for Clear CMOS
A70MR1@
R80
1M_0402_5%
Compal Secret Data
<26,31>
21807-A13-HUDSON-M3_FCBGA656
C162
1
PLT_RST#
<25>
25MHZ_10PF_X3G025000DC1H
32K_X1
32K_X2
10P_0402_50V8J
X1
DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#
S5_CORE_EN
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
25M_X1
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
14M_25M_48M_OSC
C160
1
LPCCLK0
2 R65
@1
@
0_0402_5%
25M_X2
2012/01/15
Issued Date
Deciphered Date
2013/01/15
Title

FCH PCIE/CLK/PCI/LPC/RTC
10P_0402_50V8J
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet

E
10
of
50
www.qdzbwx.com
N25
N26
LAN
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
GPP_CLK1P
GPP_CLK1N
LPC
APU
DISP2_CLKP
DISP2_CLKN
T24
T23
<7> APU_CLK
<7> APU_CLK#
APU
<7> APU_DISP_CLK
<7> APU_DISP_CLK#
APU
PCIE_RCLKP
PCIE_RCLKN
R26
T26
BT_OFF#
R62
0_0402_5%
F27
S5 PLUS
+1.1VS_CKVDD
2 2K_0402_1% CLK_CALRN
CLOCK GENERATOR
R66 1
<15,25>
VGA,LAN,WLAN,Cardreader
APU_PCIE_RST#
U1
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
@
R218
10K_0402_5%
AA27
AA26
W27
V27
V26
W26
W24
W23
0.1U_0402_16V4Z
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
+3VS
MC74VHC1G08DFT2G SC70 5P
2
R60
B
1
2
1
33_0402_5%
A
PCIE_CALRP
PCIE_CALRN
V33
V31
W30
W32
AB26
AB27
AA24
AA23
APU_PCIE_RST#_C
AF29
AF31
AB5
AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9
C156@
1
2
2 590_0402_1% PCIE_CALRP
2 2K_0402_1% PCIE_CALRN
<14>
<14>
+3VALW
APU_PCIE_RST #: Reset PCIE device on APU
1
1
R61
R63
+VDDAN_11_PCIE
UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
PCI_CLK3
PCI_CLK4
1U_0402_6.3V6K
AB33
AB31
AB28
AB29
Y33
Y31
Y28
Y29
PCIRST#
<14>
UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N
PCI_CLK1
AE30
AE32
AD33
AD31
AD28
AD29
AC30
AC32
For PCIE device reset on FS1

(GFX,GLAN,WLAN,LVDS Travis)
AF3
AF1
AF5
AG2
AF6
UMI_RXP0_C
UMI_RXN0_C
UMI_RXP1_C
UMI_RXN1_C
UMI_RXP2_C
UMI_RXN2_C
UMI_RXP3_C
UMI_RXN3_C
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
2
2
2
2
2
2
2
2
PCI CLKS
UMI_TXP0
UMI_TXN0
UMI_TXP1
UMI_TXN1
UMI_TXP2
UMI_TXN2
UMI_TXP3
UMI_TXN3
1
1
1
1
1
1
1
1
PCI INTERFACE
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
C148
C149
C150
C151
C152
C153
C154
C155
PCI EXPRESS INTERFACES
UMI_RXP0
UMI_RXN0
UMI_RXP1
UMI_RXN1
UMI_RXP2
UMI_RXN2
UMI_RXP3
UMI_RXN3
PCIE_RST#
A_RST#
HUDSON-2
APU_PCIE_RST#_C AE2
2 33_0402_5% A_RST#
AD5
R59 1
PLT_RST#
150P_0402_50V8J
2 C147
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
R59/ C147 close to FCH

1
150P_0402_50V8J
U2A
U2B
HUDSON-2
AJ22
AH22
AM23
AK23
AH24
AJ24
AN24
AL24
AL26
AN26
AJ26
AH26
AN29
AL28
AK27
AM27
AL29
AN31
AL31
AL33
2
AH33
AH31
AJ33
AJ31
+AVDD_SATA
R94 1
1K_0402_1% SATA_CALRP
AF28
R95 1
931_0402_1% SATA_CALRN
AF27
SATA_RX1N
SATA_RX1P
SATA_TX2P
SATA_TX2N
SATA_RX2N
SATA_RX2P
SATA_TX3P
SATA_TX3N
SATA_RX3N
SATA_RX3P
SATA_TX4P
SATA_TX4N
SATA_RX4N
SATA_RX4P
SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
NC6
NC7
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161
VGA_RED
NC8
NC9
VGA_GREEN
NC10
NC11
VGA_BLUE
NC12
NC13
VGA_HSYNC/GPO68
VGA_VSYNC/GPO69
VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71
SATA_CALRP
SATA_CALRN
VGA_DAC_RSET
R97
2 10K_0402_5%
AD22
AF21
AG21
SATA_ACT#/GPIO67
VGA MAINLINK
+3VS
SATA_X1
SATA_X2
AUX_VGA_CH_P
AUX_VGA_CH_N
AUXCAL
ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N
ML_VGA_HPD/GPIO229
AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14
AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9 GBE_PHY_INTR
V6
V5
V3
T6
V1
4MB SPI ROM
+3VALW
R92 1
2 SPI_SB_CS0#
10K_0402_5%
R81 1
2 SPI_WP#
10K_0402_5%
R83 1
2 SPI_HOLD#
10K_0402_5%
C164
1
2
R82
33_0402_5%
@
0.1U_0402_16V4Z
U3
SPI_SB_CS0# 1
2
SPI_SO
3
SPI_WP#
4
SPI_CLK_FCH
+3VALW
AH20
AJ20
SATA_FRX_C_DTX_N1
SATA_FRX_C_DTX_P1
SATA_TX1P
SATA_TX1N
SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80
CS#
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
8
7
6
5
<29>
<29>
SATA_FTX_C_DRX_P1
SATA_FTX_C_DRX_N1
SATA_RX0N
SATA_RX0P
SD CARD
HDD
AN22
AL22
GBE LAN
<29>
<29>
AL20
AN20
SATA_FRX_C_DTX_N0
SATA_FRX_C_DTX_P0
SPI ROM
<25>
<25>
SATA_TX0P
SATA_TX0N
VGA DAC
SSD
SATA_FTX_C_DRX_P0
SATA_FTX_C_DRX_N0
SERIAL ATA
<25>
<25>
AK19
AM19
SPI_HOLD#
SPI_CLK_FCH
SPI_SI
C163
22P_0402_50V8J
@
W25Q32BVSSIG SOIC 8P SPI ROM
R93
2 10K_0402_5%
Mount R92, R81 if

support FCH share ROM
+3VALW
SPI_SO
SPI_SI
SPI_CLK_FCH
SPI_SB_CS0#
SPI_WP#
L30
L32
2
M29
M28
N30
M33
N32
K31
1
R96
2
715_0402_1%
V28
V29
U28 AUXCAL
R98
1
@
2 100_0402_1%
+VDDAN_11_ML
Place them close to ball within 1"
T31
T33
T29
T28
R32
R30
P29
P28
C29
T13
BT_DISABLE#
WL_OFF#
1
R214
1
R105
1
R108
1
R109
AK15
AN16
AL16
K6
10K_0402_5%
10K_0402_5%
K3
10K_0402_5%
2
M6
10K_0402_5%
VIN0/GPIO175
HW MONITOR
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
VIN1/GPIO176
VIN2/SDATI_1/GPIO177
VIN3/SDATO_1/GPIO178
VIN4/SLOAD_1/GPIO179
TEMPIN0/GPIO171
VIN5/SCLK_1/GPIO180
K5
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
TEMPIN1/GPIO172
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
N2
M3
L2
N4
P1
P3
M1
M5
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
NC1
NC2
NC3
NC4
NC5
R99
1
R100
1
R101
1
R102
1
R103
1
R104
1
R106
1
R107
10K_0402_5%
2
10K_0402_5%
@
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
10K_0402_5%
AG16
AH10
A28
G27
L4
Need to enable internal

pull down to leave
unconnected
A70MR1@
4
2012/01/15
Issued Date
Compal Secret Data
2013/01/15
Deciphered Date
Title
FCH SATA/SPI/VGA/HWM/SD
Custom
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
11
of
50
www.qdzbwx.com
<25> BT_DISABLE#
<25> WL_OFF#
AH16
AM15
AJ16
+3VALW
T9
T10
V9
For FCH internal debug use

@
2 2.2K_0402_5%
TEST0
R115 1
2 2.2K_0402_5%
TEST1
2 2.2K_0402_5%
TEST2
R116 1
<31>
GATEA20
<31>
<31>
<31>
KBRST#
EC_SCI#
EC_SMI#
AE22
SYS_RESET#
<25,26>
FCH_PCIE_WAKE#
<7>
+3VALW
R119 1
2 10K_0402_5%
USB_OC0#
R121 1
2 10K_0402_5%
USB_OC1#
R122 1
2 10K_0402_5%
USB_OC2#
R123 1
2 10K_0402_5%
USB_OC3#
<31>
R124 1
2 10K_0402_5%
USB_OC5#
R127 1
2 10K_0402_5%
USB_OC4#
R128 1
2 10K_0402_5%
USB_OC6#
R130 1
2 10K_0402_5%
USB_OC7#
R132 1
2 10K_0402_5%
H_THERMTRIP#
R133 1
2 100K_0402_5% EC_LID_OUT#
R134 1
2 10K_0402_5%
FCH_PCIE_WAKE#
2 2.2K_0402_5%
FCH_SCLK1
R148 1
R149 1
2 2.2K_0402_5%
<16>
PEG_CLKREQ#
FCH_SDATA1
2 2.2K_0402_5%
FCH_SCLK0
R142 1
2 2.2K_0402_5%
FCH_SDATA0
R143 1
2 10K_0402_5%
WD_PWRGD
R144 1
2 8.2K_0402_5%
WLAN_CLKREQ#
R145 1
2 8.2K_0402_5%
LAN_CLKREQ#
R154 1
R155 1
@
@
2 2.2K_0402_5%
EC_RSMRST#
2 10K_0402_5%
HDA_BITCLK
2 10K_0402_5%
2 10K_0402_5%
USB_OC7#
USB_OC6#
USB_OC5#
USB_OC4#
USB_OC3#
USB_OC2#
USB_OC1#
USB_OC0#
change back to @
USB_OC1#
USB_OC0#
M7
R8
T1
P6
F5
P5
J7
T8
<30> HDA_BITCLK_AUDIO
<30> HDA_SDOUT_AUDIO
<30> HDA_SDIN0
R125 1
R126 1
2 33_0402_5%
2 33_0402_5%
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
R129 1
R131 1
2 33_0402_5%
2 33_0402_5%
HDA_SYNC
HDA_RST#
AB3
AB1
AA2
Y5
Y3
Y1
AD6
AE4
K19
J19
J21
PEG_CLKREQ#_R
<15>
<17,39,42>
USB_HSD9P
USB_HSD9N
RSMRST#
USB_HSD8P
USB_HSD8N
CLK_REQ4#/SATA_IS0#/GPIO64
SMARTVOLT1/SATA_IS2#/GPIO50
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
GBE_LED0/GPIO183
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
0_0402_5%
DDR3L_EN#
PXS_RST#
PXS_PWREN
PX@
0_0402_5% 2
0_0402_5% 2
1
1
R136
R138
1
3
VGA_GATE#
Q6
S 2N7002K_SOT23-3
2
G
2
2
0_0402_5%
PX@
1
@
R112
10K_0402_5%
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
A70M3
High
USB_HSD0P
USB_HSD0N
USBSS_CALRP
USBSS_CALRN
USB_SS_TX3P
USB_SS_TX3N
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
USB_SS_TX2P
USB_SS_TX2N
USB_SS_RX2P
USB_SS_RX2N
USB_SS_TX1P
USB_SS_TX1N
PS2_DAT/SDA4/GPIO187
PS2_CLK/CEC/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
USB_SS_TX0P
USB_SS_TX0N
1 R153
1
R147
D21
C20
D23
C22
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
EMBEDDED CTRL
F21
E20
F20
A22
E18
A20
J18
H18
G18
B21
K18
D19
A18
C18
B19
B17
A24
D17
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
AMD only support FP2 + A70M3,

@ FCH_SEL function
R111 1
Hudson-M3
OHCI(DEV-20,FUN-5)
H6
H5
H10
G10
K10
J12
G12
F12
K12
K13
USB30_P10
USB30_N10
@
R113
10K_0402_5%
USB30-Left1
E10
F10
C10 USB20_P7
A10 USB20_N7
USB20-Left1
Hudson-M3
OHCI(DEV-19,FUN-0)
EHCI(DEV-19,FUN-2)
H9
G9
A8
C8
USB20_P5
USB20_N5
<32>
<32>
Card Reader
USB20_P3
USB20_N3
<23>
<23>
Int. Camera
USB20_P2
USB20_N2
<25>
<25>
WLAN
USB20_P1
USB20_N1
<32>
<32>
USB20-Right2
USB20_P0
USB20_N0
<32>
<32>
USB20-Right1
F8
E8
C6
A6
C5
A5
C1
C3
E1
E3
C16
A16
USBSS_CALRP
USBSS_CALRN
R118 1
R120 1
2 1K_0402_1%
2 1K_0402_1%
Hudson-M3
OHCI(DEV-18,FUN-0)
EHCI(DEV-18,FUN-2)
+FCH_VDD_11_SSUSB_S
A14
C14
C12
A12
D15
B15
E14
F14
Hudson-M3
XHCI(DEV-16,FUN-0)
XHCI(DEV-16,FUN-1)
F15
G15
H13
G13
J16
H16
USB30_TX_P0
USB30_TX_N0
J15
K15
USB30_RX_P0
USB30_RX_N0
H19
G19
G22
G21
E22
H22
J22
H21
R135
R137
R139
R140
K21
K22
F22
F24
E24
B23
C24
F18
FCH_SEL
1
1
1
1
USB30_TX_P0 <33>
USB30_TX_N0 <33>
USB30-Left1
USB30_RX_P0 <33>
USB30_RX_N0 <33>
2
2
2
2
USB3.0 and
USB2.0 Option
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
EC_PWM2
EC_PWM2
<14>
strap pin
Left USB port 3.0 & 2.0 co-lay

@
USB20_N7
2
R1606
1
0_0402_5%
@
USB20_P7
2
R1607
1
0_0402_5%
USB30_N10
2
R1610
1
0_0402_5%
USB20_LN
USB30_P10
2
R1611
1
0_0402_5%
USB20_LP
A70MR1@
USB20_LN
<33>
USB20_LP
<33>
2012/01/15
Issued Date
Compal Secret Data
2013/01/15
Deciphered Date
Title
FCH-ACPI/USB/HDA/GPIO
Rev
0.3
VAUS5 LA9001P M/B
Date:
<Support Wakeup>
Custom
Before setting (for reference)

A
Hudson-M3
XHCI(DEV-16,FUN-0)
XHCI(DEV-16,FUN-1)
B11
D11
FCH_SEL
2 11.8K_0402_1%
Low
USB_HSD5P
USB_HSD5N
USB_RCOMP
H1
H3
A60M2
USB_HSD6P
USB_HSD6N
B9
FCH_SEL
USB_HSD7P
USB_HSD7N
USB_SS_RX0P
USB_SS_RX0N
+3VALW
FCH Chip
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
PX@
<31>
USB_HSD12P
USB_HSD12N
G8
Sheet
E
12
of
50
www.qdzbwx.com
<40>
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD
USB_HSD13P
USB_HSD13N
USB_SS_RX1P
USB_SS_RX1N
T15
T16
HDA_SDIN0
change back to always mount
GA20IN/GEVENT0#
USB_FSD0P/GPIO185
USB_FSD0N
USB_SS_RX3P
USB_SS_RX3N
<30> HDA_SYNC_AUDIO
<30> HDA_RST_AUDIO#
R150 1
U2
EC_RSMRST#
<32>
<33>
R141 1
WD_PWRGD
AG24
AE24
<26> LAN_CLKREQ#
AE26
AF22
AH17
AG18
AF24
<30> FCH_SPKR
AD26
FCH_SCLK0
<25,9> FCH_SCLK0
FCH_SDATA0 AD25
<25,9> FCH_SDATA0
T7
FCH_SCLK1
<32> FCH_SCLK1
R7
FCH_SDATA1
<32> FCH_SDATA1
AG25
<25> WLAN_CLKREQ#
AG22
J2
AG26
<15,42> VGA_PWRGD
V8
W8
Y6
V10
AA8
2
1
AF25
PEG_CLKREQ#_R
R117
@
0_0402_5%
+3VS
R151 1
H_THERMTRIP#
AG19
R9
C26
T5
U4
K1
V7
R10
AF19
USB 3.0
R114 1
TEST0
TEST1/TMS
TEST2
HD AUDIO
+3VALW
USB MISC
TEST0
TEST1
TEST2
USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB 1.1
FCH_PWRGD
USBCLK/14M_25M_48M_OSC
USB 2.0
SYS_RESET#
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
FCH_PWRGD
PCIE_RST2#/PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
ACPI / WAKE UP EVENTS
<31>
<31>
<31>
<31,43>
EC_LID_OUT#
GPIO
<31>
USB OC
HUDSON-2
AB6
R2
W7
T3
W2
J4
N7
T14
R110
10K_0402_5%
@
U2D
PCIE_RST2 : Reset PCIE device on Hudson2/3
+3VS
PCI/GPIO I/O
CORE S0
CLKGEN I/O
PCI EXPRESS
MAIN LINK
SERIAL ATA
GBE LAN
+3VALW
1
@R166
@
R166
2.2U_0402_6.3V6M
3.3V_S5 I/O
22U_0603_6.3V6M
22U_0603_6.3V6M
C193
1U_0402_6.3V6K
C198
USB
10U_0603_6.3V6M
C182
22U_0603_6.3V6M
2
2
0_0402_5%
+3VALW
+VDDXL_3.3V
Tie to +3.3V_S5 rail if USB3 Wake
is supported; otherwise, tie to
+3.3V_S0 rail.
Hudson-2 designs: Tie to +3.3V_S0
rail.
L7
1
2
MBK1608221YZF_2P
1
@R168
@
R168
1U_0402_6.3V6K
2
0_0603_5%
VDDAN_33_HWM_S
+VDDAN_33_HWM
USB SS
AA4
0.1U_0402_16V7K
C223
26mA
VDDIO_AZ_S
220 ohm
+3VALW
M8
VDDCR_11_SSUSB_S_1
VDDCR_11_SSUSB_S_2
VDDCR_11_SSUSB_S_3
VDDCR_11_SSUSB_S_4
0.1U_0402_16V7K
12mA
VDDAN_11_SSUSB_S_1
VDDAN_11_SSUSB_S_2
VDDAN_11_SSUSB_S_3
VDDAN_11_SSUSB_S_4
VDDAN_11_SSUSB_S_5
L111
1
2
MBK1608221YZF_2P
+VDDPL_11_SYS_S
1
@R169
@
R169
2
0_0402_5%
1
@R171
@
R171
2
0_0402_5%
AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.
+3VS
+VDDIO_AZ
1
C224
VDDIO_AZ_S should be tied to

+3.3/1.5V_S5 rail if Wake on Ring
is supported
2.2U_0402_6.3V6M
A70MR1@
2012/01/15
Issued Date
Compal Secret Data
2013/01/15
Deciphered Date
Title
Custom
FCH PWR
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
13
of
50
www.qdzbwx.com
J24
2.2U_0402_6.3V6M
0.1U_0402_16V7K
C229
0.1U_0402_16V7K
C228
1U_0402_6.3V6K
C227
10U_0603_6.3V6M
C226
42 ohm/4A
C217
2 0_0603_5% +VDDCR_11_SSUSB
+1.1VS
42ohm @ 100MHz
1
2
@R165
@
R165
0_0805_5%
+1.1VALW
VDDPL_11_SYS_S
C222
@R172
@
R172 1
+1.1VALW
C210
2.2U_0402_6.3V6M
+VDDCR_1.1V
C216
C192
N20
M20
POWER
FBMA-L11-201209-221LMA30T_0805
220 ohm
L141
+1.1VALW
C186
70mA
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
424mA
N16
N17
P17
M17
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.1VS
42ohm @ 100MHz
1
2
@R159
@
R159
0_0603_5%
+1.1VS
42ohm @ 100MHz
1
2
@R162
@
R162
0_0805_5%
+VDDXL_3.3V
C209
0.1U_0402_16V7K
C221
0.1U_0402_16V7K
C220
1U_0402_6.3V6K
G24
P16
M14
N14
P13
P14
1U_0402_6.3V6K
187mA
42mA
2 0_0603_5% +VDDAN_11_SSUSB
VDDCR_11_S_1
VDDCR_11_S_2
+VDDIO_33_S
5mA
VDDXL_33_S
C197
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
N18
L19
M18
V12
V13
Y12
Y13
W11
T12
T13
2.2U_0402_6.3V6M
@R170
@
R170 1
C206
0.1U_0402_16V7K
C203
1U_0402_6.3V6K
C202
U12
U13
0.1U_0402_16V7K
40mils
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
140mA
0.1U_0402_16V7K
1U_0402_6.3V6K
VDDIO_GBE_S_1
VDDIO_GBE_S_2
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
282mA
C219
2.2U_0402_6.3V6M
C225
1U_0402_6.3V6K
C215
0.1U_0402_16V7K
C214
+3VS
220 ohm
2
L13
1
2
+VDDPL_33_SATA
MBK1608221YZF_2P
+FCH_VDD_11_SSUSB_S
2.2U_0402_6.3V6M
C218
10U_0603_6.3V6M
C213
L12
1
2
+VDDPL_33_PCIE
MBK1608221YZF_2P
+VDDCR_11V_USB
220 ohm
+3VS
220 ohm
C244
L101
1
2
MBK1608221YZF_2P
0.1U_0402_16V7K
+1.1VALW
C208
2.2U_0402_6.3V6M
C207
+VDDAN_11_USB_S
0.1U_0402_16V7K
C212
2.2U_0402_6.3V6M
220 ohm
C201
L81
1
2
MBK1608221YZF_2P
220 ohm
C211
AMD strong recommended
+1.1VALW
+VDDAN_33_USB
L91
1
2
+VDDPL_33_USB_S
MBK1608221YZF_2P
10U_0603_6.3V6M
C200
G7
H8
J8
K8
K9
M9
M10
N9
N10
M12
N12
M11
59mA
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
470mA
+VDDAN_33_USB
C199
0.1U_0402_16V7K
C205
2.2U_0402_6.3V6M
C204
220 ohm/2A
10U_0603_6.3V6M
1
2
FBMA-L11-201209-221LMA30T_0805
+AVDD_SATA
C191
AA9
AA10
VDDIO_33_GBE_S
AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19
1U_0402_6.3V6K
1 0_0402_5%
C196
R167 2
C185
AB11
AA11
VDDAN_11_ML_1
VDDAN_11_ML_2
VDDAN_11_ML_3
VDDAN_11_ML_4
2
0_0805_5%
+VDDAN_11_PCIE
1337mA
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SATA_10
+VDDAN_11_PCIE
0.1U_0402_16V7K
AB10
L5
220 ohm
VDDPL_11_DAC
AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27
C190
0.1U_0402_16V7K
C184
0.1U_0402_16V7K
Y22
V23
V24
V25
+3VALW
L6
1
2 +VDDPL_33_SSUSB_S
MBK1608221YZF_2P
LDO_CAP
226mA
C189
0.1U_0402_16V7K
+3VALW
VDDPL_33_SATA
7mA
V21
1088mA
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
+1.1VS_CKVDD
1U_0402_6.3V6K
12mA
VDDPL_33_PCIE
C170
VDDPL_33_USB_S
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
+VDDAN_11_ML
C188
4.7U_0402_6.3V6M
11mA
+VDDPL_11_DAC
2 0_0603_5%
C187
VDDPL_33_SSUSB_S
2
M31
2.2U_0603_6.3V6K
2 0_0402_5%
0.1U_0402_16V4Z
C195
2.2U_0603_6.3V6K
C194
220 ohm
14mA
@ R164 1
+FCH_VDDAN_33_DAC
L4
30mA
1
2
FBMA-L11-201209-221LMA30T_0805
11mA
VDDAN_33_DAC
AG28
+VDDPL_33_SATA
@ R163 1
220 ohm/2A
+3VS
VDDPL_33_ML
T22
AH29
1
C183
L3
1
2
MBK1608221YZF_2P
30mA
D7
+VDDPL_33_PCIE
+1.1VS
VDDPL_33_DAC
V22
U22
L18
+VDDPL_33_SSUSB_S
+VDDPL_33_USB_S
LDO_CAP: Internally generated 1.8V

supply for the RGB outputs
VDDPL_33_SYS
12mA
1U_0402_6.3V6K
+FCH_VDDAN_33_DAC
20mA
C181
+VDDPL_33_ML
1
R156
+1.1VS_CKVDD
340mA
H26
J25
K24
L22
M22
N21
N22
P22
1U_0402_6.3V6K
+VDDPL_33_DAC
2 0_0402_5%
C169
2 0_0402_5%
@ R161 1
C180
@ R160 1
H24
0.1U_0402_16V7K
+VDDPL_33_MLDAC
47mA
C179
0.1U_0402_16V7K
C176
0.1U_0402_16V7K
C175
+VDDPL_33_SYS
+VDDPL_33_SYS
0.1U_0402_16V7K
2
+VDDPL_33_MLDAC
0_0402_5%
C178
1
@ R158
1U_0402_6.3V6K
+FCH_VDDAN_33_DAC
T14
T17
T20
U16
U18
V14
V17
V20
Y17
C168
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
0.1U_0402_16V7K
0.1U_0402_16V7K
C174
0.1U_0402_16V7K
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
C167
AB17
AB18
AE9
AD10
AG7
AC13
AB12
AB13
AB14
AB16
+VCC_VDDCR_11
0.1U_0402_16V7K
102mA
+VDDIO_33_PCIGP
C173
C172
1007mA
HUDSON-2
C177
2 0_0603_5%
0.1U_0402_16V7K
@ R157 1
22U_0603_6.3V6M
+3VS
C171
0.1U_0402_16V7K
C166
2.2U_0402_6.3V6M
C165
+1.1VS
U2C
L2
1
2
+VDDPL_33_SYS
MBK1608221YZF_2P
220 ohm
STRAP PINS
PULL
HIGH
U2E
1
PCI_CLK1
PCI_CLK3
ALLOW
PCIE GEN2
USE
DEBUG
STRAPS
PCI_CLK4
CLK_PCI_EC
NON_FUSION
CLOCK MODE
EC
ENABLED
DEFAULT
LPC_CLK1
EC_PWM2
RTC_CLK
CLKGEN
ENABLED
LPC ROM
S5 PLUS
MODE
DISABLED
DEFAULT
DEFAULT
DEFAULT
PCI_CLK4
LPC_CLK1
<12>
EC_PWM2
+3VALW
+3VALW
+3VALW
1
@
2
1
2
+3VALW
1
2
1
2
1
2
1
2
R191 2.2K_0402_5%
R190 2.2K_0402_5%
R189 10K_0402_5%
RTC_CLK
<10,31>
S5 PLUS
MODE
ENABLED
CLK_PCI_EC
<10>
<10,31>
2
PCI_CLK3
<10>
SPI ROM
R179 10K_0402_5%
PCI_CLK1
<10>
+3VS
R178 10K_0402_5%
<10>
+3VS
R177 10K_0402_5%
+3VS
CLKGEN
DISABLE
DEFAULT
R188 10K_0402_5%
DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PULL
HIGH
T21
L28
K33
N28
PULL
LOW
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
USE PCI
PLL
DISABLE
ILA
AUTORUN
USE FC
PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
BYPASS
PCI PLL
ENABLE
ILA
AUTORUN
BYPASS
FC PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
R6
<10>
PCI_AD27
<10>
PCI_AD26
<10>
PCI_AD25
<10>
PCI_AD24
<10>
PCI_AD23
1
2
1
2
1
2
1
2
R184 2.2K_0402_5%
R183 2.2K_0402_5%
R182 2.2K_0402_5%
Compal Secret Data
2012/01/15
Issued Date
R181 2.2K_0402_5%
R180 2.2K_0402_5%
A70MR1@
2013/01/15
Deciphered Date
Title
Custom
FCH-VSS/Strap
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
14
of
50
www.qdzbwx.com
EFUSE
DEFAULT
R176 10K_0402_5%
VSSPL_SYS
DEFAULT
R187 10K_0402_5%
VSSPL_DAC
VSSAN_DAC
VSSANQ_DAC
VSSIO_DAC
EC
DISABLED
R175 10K_0402_5%
VSSXL
FUSION
CLOCK
MODE
R186 10K_0402_5%
H25
VSSAN_HWM
IGNORE
DEBUG
STRAP
R174 10K_0402_5%
N8
K25
FORCE
PCIE GEN1
PULL
LOW
R185 10K_0402_5%
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33
R173 10K_0402_5%
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GROUND
HUDSON-2
A3
A33
B7
B13
D9
D13
E5
E12
E16
E29
F7
F9
F11
F13
F16
F17
F19
F23
F25
F29
G6
G16
G32
H12
H15
H29
J6
J9
J10
J13
J28
J32
K7
K16
K27
K28
L6
L12
L13
L15
L16
L21
M13
M16
M21
M25
N6
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R4
R11
R25
R28
T11
T16
T18
<5>
<5>
<5>
<5>
U8A
U8F
LVDS CONTROL
VARY_BL
DIGON
AF30
AE31
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
AE29
AD28
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
AD30
AC31
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
AC29
AB28
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
AB30
AA31
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
AA29
Y28
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
Y30
W31
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
PCI EXPRESS INTERFACE
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
W29
V28
PCIE_RX7P
PCIE_RX7N
V30
U31
PCIE_RX8P
PCIE_RX8N
U29
T28
PCIE_RX9P
PCIE_RX9N
T30
R31
PCIE_RX10P
PCIE_RX10N
R29
P28
PCIE_RX11P
PCIE_RX11N
P30
N31
PCIE_RX12P
PCIE_RX12N
N29
M28
M30
L31
L29
K30
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
AH30 PCIE_CRX_C_GTX_P0
AG31 PCIE_CRX_C_GTX_N0
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 C258 PX@
1 C259 PX@
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
AG29 PCIE_CRX_C_GTX_P1
AF28 PCIE_CRX_C_GTX_N1
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 C277 PX@
1 C276 PX@
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
AF27 PCIE_CRX_C_GTX_P2
AF26 PCIE_CRX_C_GTX_N2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 C256 PX@
1 C257 PX@
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
AD27 PCIE_CRX_C_GTX_P3
AD26 PCIE_CRX_C_GTX_N3
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 C275 PX@
1 C274 PX@
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
AC25 PCIE_CRX_C_GTX_P4
AB25 PCIE_CRX_C_GTX_N4
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 C255 PX@
1 C254 PX@
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
Y23
Y24
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 C273 PX@
1 C272 PX@
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
AB27 PCIE_CRX_C_GTX_P6
AB26 PCIE_CRX_C_GTX_N6
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
1 C253 PX@
1 C252 PX@
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
2
2
1 C271 PX@
1 C270 PX@
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
Y27
Y26
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
0.1U_0402_16V7K
0.1U_0402_16V7K
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
TXOUT_U3P
TXOUT_U3N
AB11
AB12
AH20
AJ19
AL21
AK20
AH22
AJ21
AL23
AK22
AK24
AJ23
LVTMDP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
W24
W23
TXOUT_L3P
TXOUT_L3N
V27
U26
U24
U23
216-0774207-A11ROB_FCBGA631
SXTR1@
T26
T27
LVDS
AL15
AK14
AH16
AJ15
AL17
AK16
2
AH18
AJ17
AL19
AK18
T24
T23
P27
P26
P24
P23
M27
N26
CLOCK
R395 2
PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION
GPU_RST#
PWRGOOD
PCIE_CALRN
2 R298
AA22
2 R300
2K_0402_1% 1 PX@
+1.0VGS
<12>
AL27
<10,25>
PERSTB
PXS_RST#
APU_PCIE_RST#
216-0774207-A11ROB_FCBGA631
PX@
R399
100K_0402_5%
N10
PX@
Y22 1.27K_0402_1% 1
PCIE_CALRP
2 R299
1 PX@
10K_0402_5%
1 0_0402_5%
+3VGS
U16
VGA_PWRGD
AK30
AK32
0_0402_5%
1
Y
A
GPU_RST#
R222
2
@
PX@
SXTR1@
PCIE LANE
U8
SXTR3@
2012/01/15
Issued Date
S IC 216-0809024 A11 SEYMOUR XT S3 C38!
Compal Secret Data
2013/01/15
Deciphered Date
Title
Custom
Date:
SeymourXT-S3 PCIE/LVDS
Rev
0.3
VAUS5 LA9001P M/B
Sheet
E
15
of
50
www.qdzbwx.com
<12,42>
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_VGA#
<10>
<10>
U8B
Y11
AE9
L9
N9
+1.8VGS
+DPC_VDD18
C306
0.1U_0402_10V6K
C305
1U_0402_6.3V4Z
+DPC_VDD18
C304
10U_0603_6.3V6M
L8
2
1
BLM15BD121SN1D_0402
PX@
<20>
<20>
<20>
VRAM_ID2
VRAM_ID1
VRAM_ID0
VRAM_ID2
VRAM_ID1
VRAM_ID0
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7
TXCAP_DPA3P
TXCAM_DPA3N
DVCLK
DVCNTL_0
DVCNTL_1
DVCNTL_2
DVO
TX0P_DPA2P
TX0M_DPA2N
DPA
TX1P_DPA1P
TX1M_DPA1N
DVDATA_12
DVDATA_11
DVDATA_10
DVDATA_9
DVDATA_8
DVDATA_7
DVDATA_6
DVDATA_5
DVDATA_4
DVDATA_3
DVDATA_2
DVDATA_1
DVDATA_0
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
DPB
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
+1.0VGS
+DPC_VDD18
+DPC_VDD18
W6
V6
+DPC_VDD18
+DPC_VDD18
AC6
AC5
+DPC_VDD10
+DPC_VDD10
AA5
AA6
+DPC_VDD10
L9
C347
0.1U_0402_10V6K
C346
1U_0402_6.3V4Z
+DPC_VDD10
C307
10U_0603_6.3V6M
2
1
BLM15BD121SN1D_0402
PX@
AG3
AG5
AH3
AH1
AK3
AK1
AK5
AM3
AK6
AM5
AJ7
AH6
AK8
AL7
DPC
DPC_PVDD
DPC_PVSS
TXCCP_DPC3P
TXCCM_DPC3N
DPC_VDD18#1
DPC_VDD18#2
TX0P_DPC2P
TX0M_DPC2N
DPC_VDD10#1
DPC_VDD10#2
TX1P_DPC1P
TX1M_DPC1N
U1
W1
U3
Y6
AA1
AF2
AF4
DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5
TX2P_DPC0P
TX2M_DPC0N
DPC_CALR
V4
U5
W3
V2
+3VGS
Y4
W5
AA3
Y2
J8
1 R307
2
150_0402_1%
PX@
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO5
R339
R338
R325
R320
2
@
2 PX@
2 PX@
2 PX@
1
1
1
1
GPU_GPIO8
GPU_GPIO9
R313
R314
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
1 10K_0402_5%
1 10K_0402_5%
GPU_GPIO11 R315
GPU_GPIO12 R316
GPU_GPIO13 R317
2 PX@
2
@
2
@
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
VGA_HSYNC R548
VGA_VSYNC R549
1
1
2 10K_0402_5%
2 10K_0402_5%
I2C
SCL
SDA
GPU_VID1
PEG_CLKREQ#
+1.8VGS
L6
GPIO24_TRSTB
L5
GPIO25_TDI
L3
GPIO26_TCK
L1
GPIO27_TMS
K4
T64
GPIO28_TDO
1R326
2
TEST_EN K7
AF24
PX@ 5.11K_0402_1%
T65
+DPLL_PVDD
L14
2
1
BLM15BD121SN1D_0402
PX@
PX@
3
C325
0.1U_0402_10V6K
C324
1U_0402_6.3V4Z
C323
10U_0603_6.3V6M
+DPLL_PVDD
1
PX@
PX@
AB13
W8
W9
W7
AD10
+1.0VGS
1
2 R613
4.7K_0402_5%
+DPLL_VDDC
PX@
PX@
C332
0.1U_0402_10V6K
C331
1U_0402_6.3V4Z
C330
10U_0603_6.3V6M
1
PX@
2 R329
+TSVDD
PX@
PX@
1499_0402_1%
+VREFG_GPU
AC16
+DPLL_VDDC
DDC/AUX
PLL/CLOCK
+DPLL_VDDC
XTALIN
XTALOUT
PX@
2 R335
2 R333
PX@
AF14
AE14
10_0402_5%
10_0402_5%
AD14
AM28
AK28
AC22
AB22
DPLL_PVDD
DPLL_PVSS
DDC1CLK
DDC1DATA
AUX1P
AUX1N
DPLL_VDDC
DDC2CLK
DDC2DATA
XTALIN
XTALOUT
AUX2P
AUX2N
XO_IN
XO_IN2
DDCCLK_AUX3P
DDCDATA_AUX3N
DDCCLK_AUX5P
DDCDATA_AUX5N
T4
T2
PX@
VREFG
R2SET
+DPLL_PVDD
PX@
Had confirm with I+A & A+A FAE

& check list is to use 1M
R337
VDD2DI
VSS2DI
A2VSSQ
+DPLL_PVDD
C336
0.1U_0402_16V4Z
C335
1U_0402_6.3V4Z
PX@
H2SYNC
V2SYNC
HPD1
PX_EN
2 R332
1249_0402_1%
PX@
2
1
C322 0.1U_0402_10V6K
PX@
1M_0402_5%
DPLUS
DMINUS
AE23 +VDD1DI
AD23
PX@
PX@
PX@
PX@
+VDD1DI
AM12
AK12
+1.8VGS
L11
1
2
BLM15BD121SN1D_0402
PX@
1
+VDD1DI
AL11
AJ11
AK10
AL9
PX@
PX@
PX@
AH12
AM10
AJ9
DAC2
A2VDD
+TSVDD
C334
10U_0603_6.3V6M
L17
2
1
BLM18AG121SN1D_0603
C
Y
COMP
+1.8VGS
+1.8VGS
B2
B2B
A2VDDQ
PX@
G2
G2B
+DPLL_VDDC
PX@
1 R318
2
499_0402_1%
+AVDD +AVDD
THERMAL
DDC6CLK
DDC6DATA
AL13
AJ13
T53
T54
+3VGS
AD19
AC19
AE20
AE17
+3VGS
PX@R327
PX@
R327
10K_0402_5%
PX@ R328
PX@R328
10K_0402_5%
AE19
@
AG13 1 R330
2
715_0402_1%
VGA_SMB_CK2_R
AE6
AE5
VGA_SMB_DA2_R
PX@Q64A
PX@
Q64A
DMN66D0LDW-7_SOT363-6
4
EC_SMB_CK2
<28,31>
EC_SMB_DA2
<28,31>
PX@Q64B
PX@
Q64B
AD2
AD4
AC11
AC13
AD13
AD11
AD20
AC20
AE16
AD16
AC1
AC3
T58
T59
4
PX@
Y6
4
XTALIN
1
NC
OSC
OSC
NC
+3VGS
+TSVDD
XTALOUT
27MHZ 10PF 20PPM X3G027000DA1H

PX@
PX@
C341
8.2P_0402_50V8D
R334 1
+TSVDD
2 2.61K_0402_5% R5
AD17
AC17
TS_FDO
TSVDD
TSVSS
216-0774207-A11ROB_FCBGA631
PX@
C350
8.2P_0402_50V8D
Issued Date
Compal Secret Data
SXTR1@
2012/01/15
Deciphered Date
2013/01/15
change Y6 follow QAWYA (SJ10000FH00)
Title
SeymourXT-S3 Main Gen/MSIC

Size
C
Date:
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
16
of
50
www.qdzbwx.com
L49
2
1
BLM15BD121SN1D_0402
PX@
AC14
AB16
AG24
AE22
+1.8VGS
L10
1
2
BLM15BD121SN1D_0402
+AVDD
+VDD1DI
R2
R2B
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN
TESTEN_LEGACY
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
AD22
+AVDD
2
<12>
<42>
VDD1DI
VSS1DI
VGA_HSYNC
VGA_VSYNC
GPU_VID0
T57
AH26
AJ27
C401
10U_0603_6.3V6M
<42>
R331
10K_0402_5%
@
AH24
AG25
C315
10U_0603_6.3V6M
GPIO26_TCK
AVDD
AVSSQ
C400
1U_0402_6.3V4Z
2
10K_0402_5%
RSET
T56
C396
1U_0402_6.3V4Z
PX@ 1 R324
HSYNC
VSYNC
T55
AL25
AJ25
GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS
B
BB
DAC1
AM26
AK26
@
@
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
G
GB
C313
0.1U_0402_10V6K
+3VGS
PX@ 1 R321
PX@ 1 R322
PX@ 1 R323
+3VGS
ACIN
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
D4
CH751H-40PT_SOD323-2
<31,37>
U6
U10
T10
U8
U7
@
2
T9
T8
T7
P10
GPU_GPIO8
P4
GPU_GPIO9
P2
N6
GPU_GPIO11
N5
GPU_GPIO12
N3
GPU_GPIO13
Y9
N1
GPU_VID0
M4
T63
R6
W10
PX@
2
M2
R319 1
10K_0402_5%
P8
GPU_VID1
P7
T70
N8
N7
PEG_CLKREQ#
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
VGA_SMB_DA2_R
VGA_SMB_CK2_R
GPU_GPIO5
C397
0.1U_0402_10V6K
R
RB
GENERAL PURPOSE I/O
R1
R3
+3.3VS TO +3.3VGS
Q27
+3VS
+3VGS
PMV65XP_SOT23-3
D
PX@C344
PX@
C344
10U_0603_6.3V6M
@ R284
C345 PX@
1U_0402_6.3V6K
470_0603_5%
PX@
R271
1
@ R283
0_0402_5%
PXS_PWREN#
20K_0402_5%
PXS_PWREN
<12,39,42>
2
G
PXS_PWREN
PX@
R270
20K_0402_5%
+5VALW
PX@
PX@ 1
C1139
10U_0603_6.3V6M
S
2N7002K_SOT23-3
D
Q30 PX@
S 2N7002K_SOT23-3
@ Q35
2
G
C1143 PX@
0.1U_0402_16V4Z
+1.5V_IO TO +1.5VGS
+1.5V_IO
+1.5VGS
@
R274
470_0603_5%
C1147 PX@
1U_0402_6.3V6K
@ R285
PXS_PWREN# 1
PX@
R275
20K_0402_5%
PX@
C1146
10U_0603_6.3V6M
0_0402_5%
1 2
+VSB
PX@
R286
100K_0402_5%
2 2
G
@
Q31
2N7002K_SOT23-3
R280
0_0402_5%
@
PX@ PX@
Q69A
C1149 PX@
0.1U_0402_25V6
PX@ PXS_PWREN# 2
Q69B
43K_0402_5%
R278
PXS_PWREN
+3VALW
1
2
3
PX@
R276
100K_0402_5%
Issued Date
Compal Secret Data
2012/01/15
Deciphered Date
2013/01/15
Title
SeymourXT-S3 BACO Power

Size
C
Date:
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
17
of
50
www.qdzbwx.com
U12
PX@
AO4430L_SO8
8
7
6
5
10U_0603_6.3V6M 1
C1145
PX@
+DPEF_VDD18
U8G
DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2
+DPEF_VDD10
2
MBK1608121YZF_0603
total:240mA@LVDS
total:220mA@DP
1
1
AG14
AH14
AM14
AM16
AM18
DPA_VDD18#1
DPA_VDD18#2
DPE_VDD10#1
DPE_VDD10#2
DPA_VDD10#1
DPA_VDD10#2
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
DPF_VDD18#1
DPF_VDD18#2
DPB_VDD18#1
DPB_VDD18#2
AF6
AF7
L19
0_0603_5%
PX@
MBK1608121YZF_0603
L21
L21
0_0603_5%
PX@
MBK1608121YZF_0603
+DPAB_VDD18
2
+DPAB_VDD10
110mA
AF22
AG22
AF23
AG23
AM20
AM22
AM24
AF17
DPF_VDD10#1
DPF_VDD10#2
DPB_VDD10#1
DPB_VDD10#2
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
DPEF_CALR
DPAB_CALR
AF8
AF9
20mA
AG18
AF19
DPE_PVDD
DPE_PVSS
AE10
20mA
DP PLL POWER
DPA_PVDD
DPA_PVSS
+DPAB_VDD10
AF10
AG9
AH8
AM6
AM8
+DPEF_VDD18
AG8
AG7
+DPEF_VDD18
+DPAB_VDD18
AE13
AF13
+DPEF_VDD10
+DPEF_VDD18
+1.0VGS
AE1
AE3
AG1
AG6
AH5
130mA
AF16
AG17
R463 PX@
2
1
150_0402_1%
L19
total:220mA
+DPEF_VDD18
AE11 +DPAB_VDD18
AF11
+DPAB_VDD10
110mA
AG20
AG21
C361
0.1U_0402_10V6K
L20
C360
1U_0402_6.3V4Z
C356
10U_0603_6.3V6M
L20
0_0603_5%
PX@
DP A/B POWER
130mA
AG15
AG16
C359
10U_0603_6.3V6M
+1.0VGS
C364
10U_0603_6.3V6M
C358
1U_0402_6.3V4Z
MBK1608121YZF_0603
C357
0.1U_0402_10V6K
C362
0.1U_0402_10V6K
+1.8VGS
@
total:300mA
C355
0.1U_0402_10V6K
+DPAB_VDD18
total:440mA@LVDS
total:300mA@DP
C368
1U_0402_6.3V4Z
L18
C367
10U_0603_6.3V6M
C363
1U_0402_6.3V4Z
+1.8VGS
L18
0_0603_5%
PX@
1 R464
2
150_0402_1%
PX@
+DPAB_VDD18
+DPAB_VDD18
+DPAB_VDD18
+DPEF_VDD18
20mA
AG19
AF20
20mA
DPF_PVDD
DPF_PVSS
DPB_PVDD
DPB_PVSS
AG10
AG11
+DPAB_VDD18
216-0774207-A11ROB_FCBGA631
SXTR1@
www.qdzbwx.com
Issued Date
Compal Secret Data
2012/01/15
Deciphered Date
2013/01/15
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
Date:
SeymourXT-S3 DPX Power

Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
18
of
50
+1.5VGS
+PCIE_VDDR
V11
U11
NC#1
NC#2
NC#3
NC#4
MEM CLK
+PCIE_VDDR
AM30
PX@
3
PX@
+MPV18
75mA L8
+SPV18
50mA H7
+SPV10
100mAH8
+1.0VGS
J7
L28
1
2
BLM15BD121SN1D_0402
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PCIE_PVDD
BIF_VDDC#1
BIF_VDDC#2
R21
U21
PX@
NC_MPV18
SPVSS
ISOLATED
CORE I/O
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
M13
M15
M16
M17
M18
M20
M21
N20
PX@
PX@
PX@
PX@
PX@
M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11
PX@
C343
22U_0603_6.3V6K
+VDDCI
PX@
+VGA_CORE
NC_VSSRHA
SPV10
PX5 only
NC_VDDRHA
SPV18
+VGA_CORE
PX@
PX@
PX@
PX@
PX@
14.1A(RMS)/19.1A(Peak)
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
M11
M12
PLL
For Seymour, PCIE_PVDD is PCIE_VDDR.
C458
0.1U_0402_10V6K
L16
C464
1U_0402_6.3V4Z
PX@
C456
10U_0603_6.3V6M
C462
10U_0603_6.3V6M
L48
PX@
1
2
BLM15BD121SN1D_0402
1
PX@
L17
C449
0.1U_0402_10V6K
C463
0.1U_0402_10V6K
PX@
C426
10U_0603_6.3V6M
C430
0.1U_0402_10V6K
C447
1U_0402_6.3V4Z
PX@
C454
1U_0402_6.3V4Z
L47
1
2
BLM15BD121SN1D_0402
AA11
AA12
VDDR4#1
VDDR4#2
VDDR4#3
PX@
C425
10U_0603_6.3V6M
C429
1U_0402_6.3V4Z
PX@
POWER
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
PX@
C424
10U_0603_6.3V6M
V12
Y12
U12
170mA
BLM15BD121SN1D_0402
PX@
AA17
AA18
AB17
AB18
PX@
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
CORE
I/O
L24
C446
10U_0603_6.3V6M
60mA
PX@
+1.0VGS
PX@
C423
10U_0603_6.3V6M
PX@
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
PX@
2000mA
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
+VGA_CORE
R745
0_0603_5%
1
2
PX@
PX@
U8E
AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32
C420
1U_0402_6.3V4Z
PX@
PX@
LEVEL
TRANSLATION
AA20
AA21
AB20
AB21
17mA
PX@
C419
1U_0402_6.3V4Z
L24
0_0402_5%
PX@
PX@
C418
1U_0402_6.3V4Z
C384
10U_0603_6.3V6M
C428
1U_0402_6.3V4Z
+3VGS
C410
1U_0402_6.3V4Z
C427
10U_0603_6.3V6M
C404
10U_0603_6.3V6M
1
BLM15BD121SN1D_0402
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26
9/28 Reserved for VGA_CORE

02/07 change to S3 size
MBK1608121YZF_0603
C417
1U_0402_6.3V4Z
219mA
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
C403
1U_0402_6.3V4Z
L46
C422
0.1U_0402_10V6K
+VDDC_CT
C405
1U_0402_6.3V4Z
+1.8VGS
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
C416
1U_0402_6.3V4Z
L46
0_0402_5%
PX@
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22
C380
10U_0603_6.3V6M
PCIE
C388
1U_0402_6.3V4Z
MEM I/O
C387
1U_0402_6.3V4Z
PX@
C383
1U_0402_6.3V4Z
PX@
C415
1U_0402_6.3V4Z
PX@
C461
1U_0402_6.3V4Z
PX@
C385
0.1U_0402_10V6K
PX@
PX@
C399
1U_0402_6.3V4Z
PX@
C398
1U_0402_6.3V4Z
PX@
L22
0_0603_5%
PX@
C432
1U_0402_6.3V4Z
PX@
C431
1U_0402_6.3V4Z
PX@
C470
1U_0402_6.3V4Z
PX@
C460
1U_0402_6.3V4Z
PX@
L22
@
2
+PCIE_VDDR
C465
1U_0402_6.3V4Z
PX@
+1.8VGS
440mA
U8D
C466
10U_0603_6.3V6M
C516
1U_0402_6.3V4Z
C392
0.1U_0402_10V6K
C381
0.1U_0402_10V6K
C391
0.1U_0402_10V6K
C390
0.1U_0402_10V6K
C389
0.1U_0402_10V6K
C374
1U_0402_6.3V4Z
C373
1U_0402_6.3V4Z
C372
1U_0402_6.3V4Z
C371
1U_0402_6.3V4Z
C370
1U_0402_6.3V4Z
C369
10U_0603_6.3V6M
C366
10U_0603_6.3V6M
C365
10U_0603_6.3V6M
0.9A(RMS)/1.3A(Peak)
1
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
A32
AM1
AM32
PX@
216-0774207-A11ROB_FCBGA631
SXTR1@
3
216-0774207-A11ROB_FCBGA631
SXTR1@
PX@
PX@
Issued Date
Compal Secret Data
2012/01/15
Deciphered Date
2013/01/15
Title
SeymourXT-S3 Power/GND
Size
C
Date:
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
19
of
50
www.qdzbwx.com
<21>
<21>
M_DA[63..0]
M_DA[63..0]
M_DQM[7..0]
M_DQM[7..0]
M_DQS[7..0]
<21>
M_DQS#[7..0]
M_DQS[7..0]
M_DQS#[7..0]
PARK SCL has

different recommand
9/28 change P/N to

SD034100A80R455
DRAM_RST#
C469
120P_0402_50V8J
10_0402_1%PX@
1
DRAM_RST
1
<21>
1 R366
2
51.1_0402_1%
PX@
1
R456
PX@
4.99K_0402_1%
PX@
+1.5VGS
+1.5VGS
R365
40.2_0402_1%
PX@
R363
40.2_0402_1%
PX@
C467
0.1U_0402_16V4Z
PX@
R457
100_0402_1%
PX@
R364
100_0402_1%
PX@
+MVREFSA
1
+MVREFDA
C514
0.1U_0402_16V4Z
PX@
+1.5VGS
M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5
+MVREFDA
+MVREFSA
K26
J26
2 240_0402_1%
J25
2 240_0402_1%
K25
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
GDDR5/DDR3
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA0_6
MAA0_7/MAA0_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13/BA2
MAA1_6/MAA_14/BA0
MAA1_7/MAA_15/BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
EDCA0_0/RDQSA_0
EDCA0_1/RDQSA_1
EDCA0_2/RDQSA_2
EDCA0_3/RDQSA_3
EDCA1_0/RDQSA_4
EDCA1_1/RDQSA_5
EDCA1_2/RDQSA_6
EDCA1_3/RDQSA_7
DDBIA0_0/WDQSA_0
DDBIA0_1/WDQSA_1
DDBIA0_2/WDQSA_2
DDBIA0_3/WDQSA_3
DDBIA1_0/WDQSA_4
DDBIA1_1/WDQSA_5
DDBIA1_2/WDQSA_6
DDBIA1_3/WDQSA_7
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
MVREFDA
MVREFSA
CKEA0
CKEA1
MEM_CALRN0
MEM_CALRP0
WEA0B
WEA1B
GDDR5
DRAM_RST L10
@
51.1_0402_1%
2
2
51.1_0402_1%
@
C515 @ 0.1U_0402_16V4Z
1
2
1
2
C517 @
K8
L7
MAA1_8
MAA0_8
K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_BA2
M_BA0
M_BA1
E32
E30
A21
C21
E13
D12
E3
F4
M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM4
M_DQM5
M_DQM6
M_DQM7
H28
C27
A23
E19
E15
D10
D6
G5
M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7
H27
A27
C23
C19
C15
E9
C5
H4
M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7
L18
K16
VRAM_ODT0
VRAM_ODT1
R461
R462
R359
R360
R361
R362
1
1
1
1
1
1
X76@ 2
X76@ 2
X76@ 2
X76@ 2
X76@ 2
X76@ 2
VRAM_ID0
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
VRAM_ID1
VRAM_ID2
VRAM_ID0
<16>
VRAM_ID1
<16>
VRAM_ID2
<16>
M_BA2
M_BA0
M_BA1
<21>
<21>
<21>
Vendor
VRAM_ID0
VRAM_ID1
VRAM_ID2
K4W1G1646G-BC11
64MX16 (512MB) Samsung 128MB
R461
R1 PN:SA00004GS00
R360
R362
R3 PN:SA00004GS40
H5TQ1G63DFR-11C
R462
Hynix 128MB
64MX16 (512MB) R1 PN:SA000041S20
R359
R362
R3 PN:SA000041S30
K4W2G1646C-HC11
Samsung 256MB
R461
R1 PN:SA000047Q00
128M16 (1GB)
R360
R3 PN:SA000047Q10
H5TQ2G63DFR-11C
Hynix 256MB
R462
R1 PN:SA00003YOA0
128M16 (1GB)
R359
R361
R3 PN:SA00003YOI0
K4W2G1646E-BC11
H26
H25
M_CLK0
M_CLK#0
G9
H9
M_CLK1
M_CLK#1
G22
G17
M_RAS#0
M_RAS#1
G19
G16
M_CAS#0
M_CAS#1
H22
J22
M_CS#0
G13
K13
M_CS#1
K20
J17
M_CKE0
M_CKE1
G25
H10
M_WE#0
M_WE#1
G14
G20
VRAM_ODT0
VRAM_ODT1
<21> Samsung 256MB

<21>
R461
R1 PN:SA00005SH00
R359
R361
R3 PN:SA00005SH30
M_CLK0 <21>
M_CLK#0 <21>
M_CLK1 <21>
M_CLK#1 <21>
M_RAS#0
M_RAS#1
<21>
<21>
M_CAS#0
M_CAS#1
<21>
<21>
M_CS#0
<21>
M_CS#1
<21>
M_CKE0
M_CKE1
<21>
<21>
M_WE#0
M_WE#1
<21>
<21>
M_MA13
DRAM_RST
CLKTESTA
CLKTESTB
0.1U_0402_16V4Z
SXTR1@ 216-0774207-A11ROB_FCBGA631
debug only, for clock
Issued Date
Compal Secret Data
Route 50ohms single-ended/100ohm diff and keep short
2012/01/15
Deciphered Date
2013/01/15
Title
B
observation,if not need, DNI.
Date:
R361
www.qdzbwx.com
R458 1 PX@
R459 1 PX@
R460
1
1
R373
+1.8VGS
GDDR5/DDR3
M_MA[13..0]
M_MA[13..0]
<21>
U8C
MEMORY INTERFACE
<21>
SeymourXT-S3 MEM Interface

Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
20
of
50
<20>
M_DQS[7..0]
<20>
M_DQS#[7..0]
M_MA[13..0]
M_DQM[7..0]
M_DQS[7..0]
M_DQS#[7..0]
U19
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
<20>
<20>
<20>
<20>
M_BA0
M_BA1
M_BA2
<20>
<20>
<20>
M_CLK0
M_CLK#0
M_CKE0
M2
N8
M3
M_CLK0
M_CLK#0
M_CKE0
J7
K7
K9
M_DQS2
M_DQS0
F3
C7
M_DQM2
M_DQM0
E7
D3
M_DQS#2
M_DQS#0
G3
B7
ODT/ODT0
CS/CS0
RAS
CAS
WE
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
PX@
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
J1
L1
J9
L9
E3
F7
F2
F8
H3
H8
G2
H7
M_DA22
M_DA20
M_DA19
M_DA18
M_DA21
M_DA17
M_DA23
M_DA16
D7
C3
C8
C2
A7
A2
B8
A3
M_DA3
M_DA1
M_DA0
M_DA5
M_DA6
M_DA7
M_DA2
M_DA4
M8
H1
+VREFC_A2
+VREFD_Q2
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
B2
D9
G7
K2
K8
N1
N9
R1
R9
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
+1.5VGS
M_BA0
M_BA1
M_BA2
M2
N8
M3
M_CLK0
M_CLK#0
M_CKE0
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VRAM_ODT0 K1
L2
M_CS#0
J3
M_RAS#0
K3
M_CAS#0
L3
M_WE#0
M_DQS3
M_DQS1
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
M_DQM3
M_DQM1
E7
D3
M_DQS#3
M_DQS#1
G3
B7
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C
E3
F7
F2
F8
H3
H8
G2
H7
M_DA25
M_DA28
M_DA27
M_DA31
M_DA24
M_DA29
M_DA26
M_DA30
D7
C3
C8
C2
A7
A2
B8
A3
M_DA14
M_DA10
M_DA15
M_DA11
M_DA12
M_DA8
M_DA13
M_DA9
M8
H1
+VREFC_A3
+VREFD_Q3
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
<20>
<20>
<20>
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
<20>
M_CLK1
M_CLK#1
M_CKE1
M_BA0
M_BA1
M_BA2
M2
N8
M3
M_CLK1
M_CLK#1
M_CKE1
J7
K7
K9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
M_DQS4
M_DQS5
F3
C7
M_DQM4
M_DQM5
E7
D3
M_DQS#4
M_DQS#5
G3
B7
PX@
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
+1.5VGS
M_DA47
M_DA42
M_DA45
M_DA40
M_DA44
M_DA43
M_DA46
M_DA41
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M_BA0
M_BA1
M_BA2
M2
N8
M3
M_CLK1
M_CLK#1
M_CKE1
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VRAM_ODT1 K1
L2
M_CS#1
J3
M_RAS#1
K3
M_CAS#1
L3
M_WE#1
M_DQS6
M_DQS7
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
M_DQM6
M_DQM7
E7
D3
M_DQS#6
M_DQS#7
G3
B7
96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
+1.5VGS
M_DA52
M_DA48
M_DA54
M_DA50
M_DA53
M_DA49
M_DA55
M_DA51
D7
C3
C8
C2
A7
A2
B8
A3
M_DA60
M_DA58
M_DA56
M_DA61
M_DA63
M_DA62
M_DA57
M_DA59
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C
X76@
+1.5VGS
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
J1
L1
J9
L9
PX@
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
L8
R444
243_0402_1%
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DRAM_RST# T2
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
X76@
+1.5VGS
D7
C3
C8
C2
A7
A2
B8
A3
M8
H1
+VREFC_A4
+VREFD_Q4
+1.5VGS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C
X76@
M_DA35
M_DA34
M_DA36
M_DA37
M_DA32
M_DA38
M_DA33
M_DA39
+1.5VGS
ODT/ODT0
CS/CS0
RAS
CAS
WE
J1
L1
J9
L9
E3
F7
F2
F8
H3
H8
G2
H7
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
L8
R410
243_0402_1%
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
DRAM_RST# T2
B1
B9
D1
D8
E2
E8
F9
G1
G9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
VRAM_ODT1K1
L2
M_CS#1
M_RAS#1 J3
M_CAS#1 K3
L3
M_WE#1
VRAM_ODT1
<20> M_CS#1
<20> M_RAS#1
<20> M_CAS#1
<20> M_WE#1
U21
VREFCA
VREFDQ
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
J1
L1
J9
L9
PX@
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
L8
R451
243_0402_1%
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DRAM_RST# T2
B1
B9
D1
D8
E2
E8
F9
G1
G9
U18
VREFCA
VREFDQ
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
L8
R454
243_0402_1%
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
T2
DRAM_RST#
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
VRAM_ODT0K1
L2
M_CS#0
M_RAS#0 J3
M_CAS#0 K3
L3
M_WE#0
VRAM_ODT0
<20> M_CS#0
<20> M_RAS#0
<20> M_CAS#0
<20> M_WE#0
<20>
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M_BA0
M_BA1
M_BA2
U20
VREFCA
VREFDQ
M8
H1
+VREFC_A1
+VREFD_Q1
M_DQM[7..0]
<20>
M_DA[63..0]
M_MA[13..0]
<20>
<20>
M_DA[63..0]
X76@
+1.5VGS
+1.5VGS
+1.5VGS
+1.5VGS
1
PX@
+VREFD_Q4
C479
1
R446
4.99K_0402_1%
PX@
R445
4.99K_0402_1%
PX@
PX@
+VREFC_A4
C513
C477
C476
PX@
2
1
2
C475
1
2
1
2
C474
1
2
C473
1
2
C472
1
2
PX@
+VREFD_Q3
R447
4.99K_0402_1%
PX@
0.1U_0402_10V6K
0.1U_0402_10V6K
PX@
+VREFC_A3
R448
4.99K_0402_1%
PX@
+1.5VGS
+1.5VGS
PX@
PX@
PX@
PX@
PX@
PX@
C487
PX@
C505
2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PX@
C504
C503
C502
C509
C499
C498
C497
PX@
C496
PX@
C495
PX@
C508
1
1
C511
2
2
2
10U_0603_6.3V6M10U_0603_6.3V6M
C494
PX@
C491
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C493
PX@
C512
2
10U_0603_6.3V6M
1
C483
2
56_0402_1%
C490
2
10U_0603_6.3V6M
C510
C489
2
10U_0603_6.3V6M
1
C492
C488
C484
10U_0603_6.3V6M
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C501
C506
0.01U_0402_16V7K
PX@
C500
1
R422 PX@
R385
4.99K_0402_1%
PX@
+1.5VGS
1
M_CLK1
PX@
+VREFD_Q2
R449
4.99K_0402_1%
PX@
R384
4.99K_0402_1%
PX@
0.1U_0402_10V6K
2
56_0402_1%
R383
4.99K_0402_1%
PX@
0.1U_0402_10V6K
1
R396 PX@
+VREFC_A2
R388
4.99K_0402_1%
PX@
0.1U_0402_10V6K
M_CLK#0
PX@
0.1U_0402_10V6K
2
56_0402_1%
+VREFC_A1
R387
4.99K_0402_1%
PX@
0.1U_0402_10V6K
1
R443 PX@
0.1U_0402_10V6K
M_CLK0
PX@
R382
4.99K_0402_1%
PX@
2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
M_CLK#1
1
R436 PX@
2
56_0402_1%
C507
0.01U_0402_16V7K
PX@
ref 139-02 recommand
VRAM P/N :
add off page
Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! )
Park SCL recommand pu
Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! )
60.4 ohm to 1.5VGS0619 update
update VRAM PN
Issued Date
0619 update
Compal Secret Data
2012/01/15
Deciphered Date
2013/01/15
Title
SeymourXT-S3 DDR3 VRAM

Size
C
Date:
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
21
of
50
www.qdzbwx.com
+VREFD_Q1
R386
4.99K_0402_1%
PX@
R381
4.99K_0402_1%
PX@
R380
4.99K_0402_1%
PX@
R379
4.99K_0402_1%
PX@
R450
4.99K_0402_1%
PX@
+3VS
EEROM
+3VS_PS
30mil
30mil
R192
Will @ U4 after DVT
0_0603_5%
+SWR_VDD
+3VS_PS
C232
1 +SWR_VDD
L15 2
FBMA-L11-201209-221LMA30T_0805
2 +SWR_LX
L171 1
4.7UH_PG031B-4R7MS_1.1A_20%
@
1
+SWR_V12
60mil 13
18
60mil 12
60mil 11
27
7
DP_V33
TXEC+
TXEC-
SWR_VDD
PVCC
TXE2+
TXE2-
Power
1
C231
C230
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
40mil
SWR_LX
SWR_VCCK
VCCK
DP_V12
LVDS
1 +DP_V33
L16 2
FBMA-L11-201209-221LMA30T_0805
+DP_V33
1
U5
Close to Pin3
TXE1+
TXE1TXE0+
TXE0-
19
20
LVDS_ACLK <23>
LVDS_ACLK# <23>
21
22
U4
0_0402_5%
2
MIIC_SCL R193 1
2
MIIC_SDA R194 1
0_0402_5%
LVDS_A2 <23>
LVDS_A2# <23>
MIIC_SCL_R
MIIC_SDA_R
8
7
6
5
A0
A1
A2
GND
1
2
3
4
1
CAT24C64WI-GT3_SO8
23
24
VCC
WP
SCL
SDA
LVDS_A1 <23>
LVDS_A1# <23>
25
26
LVDS_A0 <23>
LVDS_A0# <23>
+3VS_PS
LVDS_HPD
2 1K_0402_5%
LVDS_HPD_R
2
R198
100K_0402_5%
+1.2VS
Close to L171
Close to
Pin27
+SWR_V12 1
R200
2
0_0805_5%
8
4
HPD
ROM
DP_REXT
DP_GND
2
R195
4.7K_0402_5%
EDID_CLK <23>
EDID_DATA <23>
31
30
MIICSCL0
MIICSDA0
@
MIIC_SCL
29
28
MIICSCL1
MIICDA1
MIIC_SCL
MIIC_SDA
1:RevD W EEPROM
0:RevE W/O EEPROM
R196
4.7K_0402_5%
33
GND
R199
12K_0402_1%
TL_INVT_PWM <23>
TL_ENVDD <23>
APU_INVT_PWM
ENBKL_R
RTD2132S-VE-CG_QFN32_5X5
+3VS_PS
Change to 12Kohm 1% (DG ref.)

20101114
EDID_DATA
R201 1
2 4.7K_0402_5%
EDID_CLK
R202 1
2 4.7K_0402_5%
MIIC_SDA
R203 1
2 4.7K_0402_5%
20110124 Modify
1
C241
0.1U_0402_16V4Z
1
C240
0.1U_0402_16V4Z
1@
32
LVDS
EDID
14
15
16
17
C239
C238
0.1U_0402_16V4Z
22U_0603_6.3V6M
1@
CIICSCL1
CIICSDA1
GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)
Close to Pin13
LANE0P
LANE0N
R197
<7>
AUX_P
AUX_N
Other
9
10
CSCL
CSDA
Reserved for EC programming ROM

Need EC confirm
1
C237
0.1U_0402_16V4Z
1
C236
0.1U_0402_16V4Z
1
C235
22U_0603_6.3V6M
C234
0.1U_0402_16V4Z
C233
10U_0603_6.3V6M
5
6
+SWR_VDD
DP0_AUXP_C
DP0_AUXN_C
DP0_TXP0_C
DP0_TXN0_C
<7>
<7>
GPIO
<7>
<7>
Close to Pin18
RTD2132S
DP-IN
Close to L15
2
1
Will mount R200, @ L171, C238, C239 after DVT
Close to Pin7
Vendor advise reserve it

(We delete the 0ohm path between ENBKL_R & TL_BKOFF#)
+3VS
ENBKL_R
<23,31>
1
R209
R210
4.7K_0402_5%
2
1
3
1
3
DP_INT_PWM
2
G
U6
Y
A
<31>
5
1
BKOFF#
ENBKL
TL_BKOFF#
<23>
@
Q7
2N7002K_SOT23-3
CSDA
CSCL
R212
R213
1
1
2 0_0402_5%
2 0_0402_5%
TL_DATA <31>
TL_CLK <31>
www.qdzbwx.com
<7>
MMBT3904_NL_SOT23-3
APU_INVT_PWM
Q8
2
2
2.2K_0402_5% B
R208
4.7K_0402_5%
2 0_0402_5%
C242
0.1U_0402_16V7K
1
2
@
R206
100K_0402_5%
R207
47K_0402_5%
+3VS_PS
Panel PWM
R204
Issued Date
Compal Secret Data
2012/01/15
2013/01/15
Deciphered Date
Title
LVDS Translator - RTD2132S
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
22
of
50
LCD POWER CIRCUIT

CMOS Camera
+LCDVDD
1
+5VALW
+3VS
(40 MIL)
1
GND
OUT
+LCDVDD
+LCDVDD_CONN
L29
1
Q73
DTC124EKAT146_SC59-3
R1458 CMOS@
150K_0402_5%
W=60mils
0.1U_0402_16V4Z
<31>
+3VS_CMOS
CMOS@ (40 MIL)

2
1
+3VS_CMOS_R
R1456
1
0_0603_5%
CMOS@
C1152
0.1U_0402_16V4Z R02
2
10U
1
C1153 @
10U_0603_6.3V6M
CMOS_ON#
FBMA-L11-201209-221LMA30T_0805
C1156
C1157
C1155 CMOS@
0.1U_0402_16V4Z
@
4.7U_0805_10V4Z
R1459
100K_0402_5%
C1154
IN
TL_ENVDD
Q72
PMV65XP_SOT23-3
<22>
DTC124EK
220K_0402_5%
2
R1457
1
LCD_ENVDD#
CMOS@
Q70
PMV65XP_SOT23-3
C1150
4.7U_0603_6.3V6K
S
2
G
R1455
100K_0402_5%
Q71
2N7002K_SOT23-3
S
+3VS
W=60mils
R1454
150_0603_5%
0.1U_0402_16V4Z
VGA LCD/PANEL BD. Conn.

+LEDVDD
B+
C1158
680P_0402_50V7K
@
1 R1460 2
0_0805_5%
C1159
4.7U_0805_25V6-K
JLVDS1 ME@
change to EC contorl ,
due to FCH only 16 level
Add for protect DISPOFF# damage

@ R1466 1
@
<22>
TL_BKOFF#
TL_BKOFF# R1202 1
R891
1
2
0_0402_5%
2 0_0402_5%
TL_INVT_PWM
<31>
EC_INVT_PWM
R1463 1
R1465 1
<22>
<22>
2 0_0402_5%
R1201 1
2 0_0402_5%
DISPOFF#
R825
100K_0402_5%
R890
10K_0402_5%
+3VS
1
680P_0402_50V7K
C1160 @
+LCDVDD_CONN
(60 MIL)
+3VS
2
<12>
<12>
+3VS_CMOS
USB20_P3
USB20_N3
USB20_P3
USB20_N3
CMOS
31
32
33
34
35
36
GND1
GND2
GND3
GND4
GND5
GND6
STARC_107K30-000001-G2
R85
SP010011S00
300_0402_5%
follow AMD interlock

suggestion
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2
4
C8244
15P_0402_50V8J
Compal Secret Data
2012/01/15
Issued Date
2013/01/15
Deciphered Date
Title

LVDS/CAMERA
Custom
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
23
of
50
www.qdzbwx.com
RB751V_SOD323
@
BKOFF#
BKOFF#
LVDS_ACLK
LVDS_ACLK#
<22> LVDS_A2
<22> LVDS_A2#
<22> LVDS_A1
<22> LVDS_A1#
<22> LVDS_A0
<22> LVDS_A0#
<22> EDID_DATA
<22> EDID_CLK
D33
<22,31>
2 0_0402_5%
DISPOFF#
INVT_PWM
2 0_0402_5%
<22>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
+5VS
+3VS
RB491D_SC59-3
D31 HDMI@
2
1+HDMI_5V
+5VS
1
C1223
1000P_0402_50V7K
1
2
150K_0402_5%
2
B
HDMI@ R1470
2.2K_0402_5%
R1471 HDMI@
2.2K_0402_5%
1
@
R864
200K_0402_5%
HDMI_DET
HDMI@
R859
100K_0402_5%
JHDMI1 @
HDMI_DET_R
+5VS_HDMI
HDMIDAT_R
HDMICLK_R
<7>
<7>
DP2_TXP0
DP2_TXN0
<7>
<7>
DP2_TXP1
DP2_TXN1
<7>
<7>
DP2_TXP2
DP2_TXN2
<7>
<7>
DP2_TXP3
DP2_TXN3
C51
C52
HDMI@ 1
HDMI@ 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX2P
HDMI_TX2N
DP2_TXP1
DP2_TXN1
C53
C54
HDMI@ 1
HDMI@ 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX1P
HDMI_TX1N
DP2_TXP2
DP2_TXN2
C55
C56
HDMI@ 1
HDMI@ 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX0P
HDMI_TX0N
DP2_TXP3
DP2_TXN3
C57
HDMI@ 1
C5888 HDMI@ 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_CLKP
HDMI_CLKN
DP2_TXP0
DP2_TXN0
C1161
HDMI@
0.1U_0402_16V4Z 2
HDMI@ C
Q87
MMBT3904_NL_SOT23-3
<7>
HDMI@
R434
1K_0402_5%
R84
D32 @
BAT54S-7-F_SOT23-3
FOR EMI
1
W=40mils
+5VS_HDMI
F1
HDMI@
1.1A_6VDC_FUSE
1
2 +5VS_HDMI
1
HDMI_CLKN
R1473 1 @
2 0_0402_5%
HDMI_CLK-_CONN
HDMI_CLKP
HDMI_TX0N
R1474 1 @
R1475 1 @
2 0_0402_5%
2 0_0402_5%
HDMI_CLK+_CONN
HDMI_TX0-_CONN
HDMI_TX0P
HDMI_TX1N
R1476 1 @
R1477 1 @
2 0_0402_5%
2 0_0402_5%
HDMI_TX0+_CONN
HDMI_TX1-_CONN
HDMI_TX1P
HDMI_TX2N
R1478 1 @
R1480 1 @
2 0_0402_5%
2 0_0402_5%
HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2P
R1481 1 @
2 0_0402_5%
HDMI_TX2+_CONN
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
CONCR_099ATAC19NBLCNF
L30
HDMI_CLKP
Close to HDMI connector
HDMI@
Change Symbol to main source 02/24
HDMI_CLK+_CONN
D1 @
HDMI_CLKN
HDMI_TX0P
HDMI_TX0N
1
4
HDMI_TX2-_CONN
HDMI_TX2-_CONN
WCM-2012HS-900T
HDMI_TX2+_CONN
HDMI_TX2+_CONN
L31
HDMI_TX1-_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN
HDMI_TX1+_CONN
HDMI_CLK-_CONN
HDMI@
2
3
HDMI_TX0+_CONN
HDMI_TX0-_CONN
3
WCM-2012HS-900T
L32
HDMI_TX1P
HDMI_TX1N
HDMI@
TVWDF1004AD0_DFN9
2
HDMI_TX1+_CONN
HDMI_TX1-_CONN
D2 @
WCM-2012HS-900T
L33
HDMI_TX2P
HDMI@
HDMI_TX0-_CONN
HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX0+_CONN
HDMI_CLK-_CONN
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_CLK+_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN
R243 1 HDMI@ 2 604_0402_1%
HDMI_CLK+_CONN
R244 1 HDMI@ 2 604_0402_1%
TVWDF1004AD0_DFN9
HDMI_TX1-_CONN
R245 1 HDMI@ 2 604_0402_1%
HDMI_TX1+_CONN
R246 1 HDMI@ 2 604_0402_1%
HDMICLK_R
HDMI_TX0-_CONN
R247 1 HDMI@ 2 604_0402_1%
HDMIDAT_R
HDMI_TX0+_CONN
R248 1 HDMI@ 2 604_0402_1%
HDMI_TX2-_CONN
R249 1 HDMI@ 2 604_0402_1%
HDMI_TX2+_CONN
R250 1 HDMI@ 2 604_0402_1%
<7>
HDMI_DATA
D69
L30ESDL5V0C3-2_SOT23-3
HDMI@
HDMI_CLK
Q75A
HDMI@
2N7002DW-T/R7_SOT363-6
6
+5VS
4.7K_0402_5% HDMI@
R242
+3VS
HDMICLK_R
HDMI_CLK
2
R241
1
<7>
4.7K_0402_5% HDMI@
+3VS
HDMI_DATA
2
G
Q76
2N7002K_SOT23-3
HDMI@
HDMIDAT_R
Q75B
HDMI@
2N7002DW-T/R7_SOT363-6
2012/01/15
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
2013/01/15
Deciphered Date
Title
HDMI CONN
Rev
0.3
VAUS5 LA9001P M/B
Date: Friday, May 25, 2012
Sheet
E
24
of
50
www.qdzbwx.com
HDMI_CLK-_CONN
3
WCM-2012HS-900T
HDMI_TX2N
Mini-Express Card for WLAN/WiMAX(Half)
Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
+1.5VS_WLAN
1
@
1
C1172
0.1U_0402_16V4Z
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB
C1173
0.1U_0402_16V4Z
2@
+1.5VS
Mini-Express Card(WLAN/WiMAX)
0_0402_5%
WLAN_CLKREQ#
BT_DISABLE_R
WLAN_CLKREQ#
<10> CLK_PCIE_WLAN#
<10> CLK_PCIE_WLAN
PCI_RST#_R
CLK_PCI_DB
<5>
<5>
<5>
<5>
PCIE_CRX_DTX_N1
PCIE_CRX_DTX_P1
PCIE_CTX_DRX_N1
PCIE_CTX_DRX_P1
+3VS_WLAN
<31>
<31>
EC_TX
EC_RX
EC_TX
EC_RX
BT_DISABLE#
@ R1493
<10>
BT_OFF#
@ R1520
0_0402_5%
1 R1498 2
1
2
R1499
0_0402_5%
53
2
1K_0402_5%
2
1K_0402_5%
WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
GND
GND
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
APU_PCIE_RST#
LPC_FRAME#
<10,31>
LPC_AD3
<10,31>
LPC_AD2
<10,31>
LPC_AD1
<10,31>
LPC_AD0
<10,31>
CLK_PCI_DB
+1.5VS_WLAN
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
@ R1492 1
R1494 1
R1495 1
2 0_0402_5%
APU_PCIE_RST#
2 @ 0_0402_5%
2
0_0402_5%
R1496 1
R1497 1
2 @ 0_0402_5%
2 @ 0_0402_5%
+3VALW
WL_OFF#
<11>
APU_PCIE_RST#
+3VALW
+3VS_WLAN
<10,15>
FCH_SCLK0
<12,9>
FCH_SDATA0
<12,9>
BELLW_80019-1021
DC040004X00
1
2
0_0402_5%
R1504
NONAOAC@
+3VS

suggestion
2
VCC
D-
HSD-
D+
HSD+
GND
OE#
USB20_N2
USB20_P2
WLAN_USB_ON#
R1518
AOAC@
USB20_N2
USB20_P2
USB20_N2
<12>
USB20_P2
<12>
WLAN_USB_ON#
<31>
R1505
0_0402_5%
+3VS_WLAN_AOAC
+3VS_WLAN
1 0_0603_5%
NONAOAC@
C8246
15P_0402_50V8J
USB20_P2_WLAN
NC
TS3USB31RSER_QFN8_1P5X1P5
NONAOAC@
R1503
0_0402_5%
1
2
USB20_P2_WLAN
R87
300_0402_5%
USB20_N2_WLAN
USB20_N2_WLAN
54
AOAC@
C1185
0.1U_0402_16V4Z
1
2
U56
7
USB20_N2_WLAN
USB20_P2_WLAN
R1500
2
AOAC@
1
C1170
0.1U_0402_16V4Z
1 0_0603_5%
C1171
0.1U_0402_16V4Z
+3VALW
Q77
AO3413_SOT23-3
D
AOAC@
2
<31>
R1501
100K_0402_5%
AOAC_ON#
R1502
150K_0402_5%
AOAC@
For EC to detect
debug card insert.
<10>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
<12>
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
R1491
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
FCH_PCIE_WAKE#
FCH_PCIE_WAKE#
BT_DISABLE#
2
2
2
2
2
2
R1488
0_0402_5%
JWLAN1 ME@
<12,26>
<11>
@
@
@
@
@
@
1
1
1
1
1
1
+3VS_WLAN
R251
R252
R253
R254
R255
R2561
AOAC@
C1174
0.1U_0402_16V4Z
AOAC@
C1175
0.1U_0402_16V4Z
Mini-Express Card for SSD(Full)
Mini-Express Card(WWAN/SSD)
+3VS_SSD
SSD Active:4.5W(1.5A)
+3VS_SSD
+3VS
0.1U_0402_16V4Z
J14
10U_0603_6.3V6M
1
SSD@
C1176
SSD@
C1177
SSD@
C1178
@
C1179
<11>
<11>
SSD@
SATA_FRX_C_DTX_P0 C1180 1
SATA_FRX_C_DTX_N0 C1181 1
SSD@
SSD@
SATA_FTX_C_DRX_N0 C278 1
SATA_FTX_C_DRX_P0 C2758 1
SSD@
SATA_FRX_C_DTX_P0
SATA_FRX_C_DTX_N0
SATA_FTX_C_DRX_N0
SATA_FTX_C_DRX_P0
Need SHORT
JUMP_43X79
11/07 Change type to 0603
2 0.01U_0402_16V7K SATA_FRX_DTX_P0
2 0.01U_0402_16V7K SATA_FRX_DTX_N0
2 0.01U_0402_16V7K SATA_FTX_DRX_N0
2 0.01U_0402_16V7K SATA_FTX_DRX_P0
+3VS_SSD
53
WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
BELLW_80019-1021
DC040004X00
Compal Secret Data
Issued Date
2012/01/15
Deciphered Date
2013/01/15
Title
Mini-Card
Size
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Date:
Sheet
E
25
of
50
www.qdzbwx.com
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
10U_0603_6.3V6M
<11>
<11>
JSSD1 ME@
0.01U_0402_16V7K
Layout Notice : Place as close

chip as possible.
+LAN_VDD10
<12>
<10>
<10>
16
LAN_CLKREQ#
<10,31>
<12,25>
<31> LAN_WAKE#
FCH_PCIE_WAKE#
+3V_LAN
2
1
1 0_0402_5%
2 0_0402_5%
PCIE_WAKE#_R
R1510 2
R1511 1
+3V_LAN
1 10K_0402_5%
2 1K_0402_5%
@
@
1
2
1
R1513
DVDD33
DVDD33
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
ENSW REG
EVDD10
VDDREG
VDDREG
2
46
2.49K_0402_1%
24
49
LAN_CLKREQ#
DVDD10
DVDD10
DVDD10
ISOLATEB
14
15
38
34
35
+LAN_VDDREG
MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-
MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-
13
29
41
AVDD10
AVDD10
AVDD10
AVDD10
RSET
GND
PGND
REGOUT
27
39
12
42
47
48
21
3
6
9
45
36
Layout Note: L34 must be

within 200mil to Pin36,
C1184
C1184,C1182 must be within 4.7U_0603_6.3V6K
200mil to LL1
X5R
+LAN_REGOUT: Width =60mil
1 10K_0402_5%
1 10K_0402_5%
@
@
C1182
0.1U_0402_16V4Z
+LAN_VDD10
+LAN_EVDD10
2 0_0603_5%
+LAN_VDD10
C1187
1U_0402_6.3V4Z
+3V_LAN
C1188
0.1U_0402_16V4Z
Close to Pin 21
Rising time (10%~90%)1mS <Rising time <100mS
+3V_LAN
+3V_LAN
+LAN_EVDD10
+LAN_VDDREG
Close to Pin 12,27,39,42,47,48

2
@ L36 1
+LAN_VDD10
2 0_0603_5%
C1195
4.7U_0603_6.3V6K
+LAN_REGOUT
X5R
+3V_LAN
C1196
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
GIGA@ 0.1U_0402_16V4Z
SA00004Y700
+3VS
GIGA@ 0.1U_0402_16V4Z
+3V_LAN
ISOLATEB
ENSWREG
R1515
0_0402_5%
@
R1514
1K_0402_5%
Close to Pin 3,6,9,13,29,41,45
R1517
0_0402_5%
@
R1516
15K_0402_5%
+LAN_VDD10
1
0.1U_0402_16V4Z
Follow Vendor tunning value
NC
OSC
R02
CLK_LAN_25M
NC
H: Enable internal Regular

L: Disable
<10>
0.1U_0402_16V4Z
1
GIGA@
0.1U_0402_16V4Z
GIGA@
0.1U_0402_16V4Z
GIGA@
0.1U_0402_16V4Z
GIGA@
0.1U_0402_16V4Z
1 25MHZ_10PF_X3G025000DC1H
C1204
15P_0402_50V8J
0.1U_0402_16V4Z
2 0_0402_5%
C1205
15P_0402_50V8J
U47
8105@
2
C1203
2
C1200
2
C1199
2
C1197
2
C1201
2
C1202
2
C1198
RTL8105E-VL-CGT
SA00003PO40
www.qdzbwx.com
OSC
LAN_XTALO
Y4
2
C1189
2
C1190
2
C1191
2
C1192
2
C1193
2
C1194
GIGA@ 0.1U_0402_16V4Z
RL1
Layout Notice : Place as close

chip as possible.
11/08 Increase for LAN S5 power saving
RTL8111F-CGT_QFN48_6x6
GIGA@
LAN_XTALI
R211
0_0805_5%
2
R211 for power consumption easily rework
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
LANW AKEB
33
ENSWREG
R1512
10K_0402_5%
@
1
2
4
5
7
8
10
11
R1506 2
R1507 2
@ L35 1
CKXTAL2
28
ISOLATEB 26
30
32
CKXTAL1
44
LAN_XTALO
R1508
R1509
REFCLK_P
REFCLK_N
43
LAN_XTALI
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
PERSTB
19
20
CLK_PCIE_LAN
CLK_PCIE_LAN#
EECS
EEDI
CLKREQB
25
PLT_RST#
Pin 16 and Pin 28 are OD pins
HSIP
HSIN
+3V_LAN
+3VALW
17
18
PCIE_CTX_DRX_P0
PCIE_CTX_DRX_N0
31
37
40
<5>
<5>
LED3/EEDO
LED1/EESK
LED0
HSON
HSOP
2 0.1U_0402_16V7K PCIE_CRX_DTX_C_N0 23
2 0.1U_0402_16V7K PCIE_CRX_DTX_C_P0 22
C1186 1
C1183 1
PCIE_CRX_DTX_N0
PCIE_CRX_DTX_P0
<5>
<5>
L34
1
2
+LAN_REGOUT
2.2UH +-5% NLC252018T-2R2J-N
U47
Issued Date
Compal Secret Data
2012/01/15
2013/01/15
Deciphered Date
Title
LAN-RTL8111F/8105E
Custom
Date:
Rev
0.3
VAUS5 LA9001P M/B
Sheet
E
26
of
50
Reserve gas tube for EMI go rural solution
T71
<26>
<26>
D34
AZC099-04S.R7G_SOT23-6
1
4
I/O1
I/O3
MDI2+
MDI3+
<26>
<26>
MDI3-
GND
VDD
I/O2
I/O4
MDI3+
MDI3-
MDI3+
MDI3-
MDI2+
MDI2-
MDI2+
MDI2-
1
2
3
4
5
6
7
8
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
MDO3+
MDO3MCT
MCT
MDO2+
MDO2-
R1521
1
C1206
1
2
CHASSIS1_GND
5
75_0805_5%
BOTHHAND_NS0013LF
GIGA@
6
10P_0603_50V
MDI22
T72
Place Close to T71
<26>
<26>
MDI0+
MDI0-
<26>
<26>
MDI1+
MDI1-
MDI0+
MDI0-
1
@
2
D35
1
4
I/O1
I/O3
MDI1+
MDI0-
GND
VDD
I/O2
I/O4
C1207
0.01U_0402_16V7K
MDI1+
MDI1-
MDI0+
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
MDO0+
MDO0MCT
MCT
MDO1+
MDO1-
BOTHHAND_NS0013LF
MDI1JRJ1
ME@
Place Close to T71,T72
Place Close to T72

GND
GND
D34/D35
1'S PN:SC300001G00
2'S PN:SC300002E00
1
2
3
4
5
6
7
8
DL2
BS4200N-C-LV_SMB-F2
GAS@
MDO0+
MDO0-
MDO1+
MDO2+
MDO2-
MDO1-
MDO3+
MDO3-
GND
PR1+
GND
12
11
10
9
PR1PR2+
CHASSIS1_GND
PR3+
PR3PR2PR4+
PR4-
www.qdzbwx.com
SANTA_130460-3
DC231112261
Issued Date
Compal Secret Data
2012/01/15
Deciphered Date
2013/01/15
Title
B
Date:
LAN_Transformer
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
27
of
50
SMSC thermal sensor

placed near by VRAM
Close to DDR
REMOTE1+
+3VS
C1211
2200P_0402_50V7K
+3VS
2
R1524
10K_0402_5%
@
REMOTE1-
1
REMOTE2+
REMOTE1+
1
2
2
C1212
0.1U_0402_16V4Z
REMOTE2-
REMOTE1-
REMOTE2+
REMOTE2-
2
B
Q79
MMST3904-7-F_SOT323-3
E
REMOTE1-
U49
@ C1213
2200P_0402_50V7K
@
C1210
100P_0402_50V8J
REMOTE1+
VDD
SMCLK
DP1
SMDATA
DN1
ALERT#
DP2
THERM#
DN2
GND
10
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2
<16,31>
EC_SMB_DA2
<16,31>
Under WWAN
REMOTE2+
1
8
@
C1214
100P_0402_50V8J
7
6
Close U49
REMOTE2-
EMC1403-2-AIZL-TR_MSOP10
2
B
Q80
MMST3904-7-F_SOT323-3
E
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
Address 1001_101xb
2
H8
HOLEA
H9
HOLEA
H10
HOLEA
H11
HOLEA
H12
HOLEA
H13
HOLEA
H15
HOLEA
H_2P5
H_2P5
H_2P5
H_2P5
H18
HOLEA
H19
HOLEA
H20
HOLEA
H29
HOLEA
H_2P5
H_3P0
+5VS
H7
HOLEA
Screw Hole
FAN1 Conn
H6
HOLEA
CHASSIS1_GND
JFAN1 ME@
B
H_4P0
H_4P0
H_4P0
H_4P0
H21
HOLEA
H22
HOLEA
10U
H24
HOLEA
LAN
GPU
D
H_3P3
CHASSIS1_GND
H14
HOLEA
H16
HOLEA
H26
HOLEA
H27
HOLEA
3
C
H_3P3
H23
HOLEA
H_3P3
CPU
ACES_85204-04001
SP02000CW00
C1215
10U_0603_6.3V6M
H_2P5N
H_2P5
H_5P4X2P5
1
2
3
4
G1
G2
<31> EC_TACH
<31> EC_FAN_PWM
1
2
3
4
5
6
R1525
0_0603_5%
+FAN1
H_1P5N
H_1P5N
H_3P3
H17
HOLEA
PCB Fedical Mark PAD
H25
HOLEA
FD1
FD2
FD3
FD4
H_2P5X3P1N
H_5P4X2P5
H_2P5X3P1N
H_5P9X3P0
www.qdzbwx.com
Issued Date
Compal Secret Data
2012/01/15
Deciphered Date
2013/01/15
Title
B
Fintek-Thermal IC/FAN/screw
Document Number
Rev
0.3
VAUS5 LA9001P M/B

Sheet
E
28
of
50
SATA HDD Conn.

JHDD1
<11>
<11>
SATA_FTX_C_DRX_P1
SATA_FTX_C_DRX_N1
<11> SATA_FRX_C_DTX_N1
<11> SATA_FRX_C_DTX_P1
SATA_FTX_C_DRX_P1
SATA_FTX_C_DRX_N1
C318 1
C317 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_FTX_DRX_P1
SATA_FTX_DRX_N1
SATA_FRX_C_DTX_N1
SATA_FRX_C_DTX_P1
C319 1
C320 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_FRX_DTX_N1
SATA_FRX_DTX_P1
R1527
2
+3VS
1
2
3
4
5
6
7
1
R1526
PTH
PTH
NPTH
NPTH
23
24
25
26
@
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1+3V_HDD
0_0805_5%
+5VS
ME@
GND
A+
AGND
BB+
GND
2 +5V_HDD
0_0805_5%
3.3V
3.3V
3.3V
GND
GND
GND
V5
V5
V5
GND
RSVD
GND
V12
V12
V12
SANTA_192701-1
DC010006J00
+5V_HDD
R02
+3V_HDD
1
C1218
1000P_0402_50V7K
C1219
0.1U_0402_16V4Z
R02
C1220 @
1U_0402_6.3V6K
1
C1221
10U_0603_6.3V6M
@
C1222
0.1U_0402_16V4Z
Compal Secret Data
2012/01/15
Issued Date
2013/01/15
Deciphered Date
Title
Custom
HDD Connector
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
29
of
50
www.qdzbwx.com
600ohms @100MHz 1A
P/N: SM01000BU00
R1530
Place near Pin25
C1228
C1226
Place near Pin1
BLM15BD121SN1D_0402
R1530
0_0402_5%
@
Place near Pin9
+3VDD_CODEC
+IOVDD_CODEC
+MIC1_VREFO_L
U50
Vendor recommend. 2.2K
<12>
4
5
6
HDA_BITCLK_AUDIO
2
HDA_SDIN0
22_0402_5%
HDA_SDIN0
47
1 SDATA_IN
R1536
DVDD1
AVDD2
AVDD1
DAPD/COMB_JACK
LINE1-R(PORT-C-R)
PD#
LINE1-L(PORT-C-L)
SDATA-OUT
MIC1-R(PORT-B-R)
BIT-CLK
MIC1-L(PORT-B-L)
SDATA-IN
MIC2-R(PORT-F-R)
MIC2-L(PORT-F-L)
<12>
10
HDA_SYNC_AUDIO
11
HDA_RST_AUDIO#
HDA_RST_AUDIO#
12
PC_BEEP
2
1
R1541
20K_0402_1%
JDREF
19
20
<32>
PLUG_IN#
1
R1543
39.2K_0402_1%
SENSEA
13
18
MIC Sense
R939 place near pin13
2
C1239
2
C1240
2
C1241
Capless HP Sense
R940 place near pin34
CBN
35
1
CBP
2.2U_0402_6.3V6M
1
2.2U_0402_6.3V6M
1
4.7U_0603_6.3V6K
36
34
28
LINE2-R(PORT-E-R)
RESET#
LINE2-L(PORT-E-L)
30
31
42
43
7
Vendor recommend. 2.2u
23
22
MIC_EXTR_C
21
MIC_EXTL_C
1
C1237
1
C1238
2
2.2U_0402_6.3V6M
1
1K_0402_5%
R1534
EXT_MIC
<32>
external MIC
2
2.2U_0402_6.3V6M
17
16
15
14
PCBEEP
SPK-OUT-L+
JDREF
SPK-OUT-LMONO-OUT(PORT-H)
SPK-OUT-RSense A
SPK-OUT-R+
40
SPK_L2+
41
SPK_L1-
44
SPK_R1-
45
SPK_R2+
Internal Speaker
Sense-B
CBN
HPOUT-R(PORT-A-R)
CBP
HPOUT-L(PORT-A-L)
CPVEE
SPDIF-OUT
LDO-CAP
GPIO1/DMIC-CLK
29
+MIC1_VREFO_L
SYNC
24
COMBOJACK
0_0402_5%
EC_MUTE#_R
0_0402_5%
MIC2-VREFO
GPIO0/DMIC-DATA
33
HPOUT_R
32
HPOUT_L
75_0402_5%
HP_OUTR
R1544
75_0402_5%
<32>
HP_OUTL
R1545
Headphone
<32>
48
3
DMIC_CLK_R
DMIC_DATA_R
L172
2
L173
MIC1-VREFO-R
FBMA-10-100505-301T_2P
1
DMIC_CLK
0525 EMI request to add C83 and C84.

Close to U50 Audio IC
<32>
DMIC_DATA
DMIC_CLK
<32>
FBMA-10-100505-301T_2P
DMIC_DATA
@ C83
100P_0402_50V8J
MIC1-VREFO-L
PVSS1
VREF
PVSS2
AVSS1
DVSS
AVSS2
Thermal PAD
27
Place next to pin 27
26
37
49
C84 @
100P_0402_50V8J
C1243
HDA_BITCLK_AUDIO
0.1U_0402_16V4Z
HDA_SDOUT_AUDIO
<12>
EC_MUTE#
C1242
2
1
<12>
MIC_JD
DVDD-IO
1
R1533
1
R1538
HDA_SDOUT_AUDIO
EC_MUTE#
R1537
2.2K_0402_5%
1U_0402_6.3V6K
<31>
PVDD2
PVDD1
38
25
Power down (PD#) power stage for save power

0V: Power down power stage
3.3V: Power up power stage
<12>
Place near Pin38
46
0.1U_0402_16V4Z
+5VS_PVDD
0.1U_0402_16V4Z
C1236
C1234
2 0_0805_5%
4.7U_0603_6.3V6K
C1235
@ R1531 1
+5VS
39
C1233
C1232
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
C1231
C1230
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
1
1
10U_0603_6.3V6M
2 0_0603_5%
0.1U_0402_16V4Z
C1229
@ R1529 1
600ohms @100MHz 2A
P/N: SM01000EE00
+3VDD_CODEC
+5VDDA_CODEC
L37
1
2
FBMA-L11160808601LMA10T_2P
1
+IOVDD_CODEC
C1227
2
1
+5VDDA_CODEC
+3VDD_CODEC
1U_0402_6.3V6K
+5VS
+3VS
0.1U_0402_16V4Z
S IC ALC259-VC2-CG MQFN 48P CODEC

R1549
1
3
Location
Function
R1550
1
@
SPK-OUT (Pin40/41/44/45)
Internal
Int Speaker
R1551
1
Capless HP-OUT (Pin32/33)
External
Headphone out
MIC1(Pin21/22)
External
Mic in
2
0_0402_5%
HDA_RST_AUDIO#
2
0_0402_5%
2
0_0402_5%
HDA_SDOUT_AUDIO
1
4
3
2
1
C1251
C1250
C1249
1000P_0402_50V7K
1000P_0402_50V7K
SPK_R2+_CONN
SPK_R1-_CONN
SPK_L2+_CONN
SPK_L1-_CONN
4
3
2
1
G2
G1
ACES_88266-04001
ME@
SP02000K200
Combo Jack detect (normal open)
EC Beep
SE074102K80
R1123 47K_0402_5%
1
2
1
@
C1247
33P_0402_50V8J
BEEP#
1
C1252
2
0.1U_0402_16V4Z
FCH_SPKR
1
C1253
2PC_BEEP1
0.1U_0402_16V4Z
1
C1319
2PC_BEEP
0.1U_0402_16V4Z
R1557
1
2
33_0402_5%
@
R1558
10K_0402_5%
C1134
<12>
4.7U_0603_6.3V6K
<31>
EXT_MIC
@
D38
PACDN042Y3R_SOT23-3
SPK_L2+_CONN
3
SPK_R2+_CONN
3
HDA_BITCLK_AUDIO
27_0402_5%
PC Beep
PCH Beep
SPK_L1-_CONN
6
5
MIC_JD
SPK_R1-_CONN
GNDA
1
22P_0402_50V8J
C1246
GND
JSPK1
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
1000P_0402_50V7K
2
2
2
2
C1248
1
1
1
1
1000P_0402_50V7K
R1553
R1555
R1554
R1556
22P_0402_50V8J
C1245
1
22P_0402_50V8J
C1244
wide 25MIL
R1552
SPK_R2+
SPK_R1SPK_L2+
SPK_L1-
D39
PACDN042Y3R_SOT23-3
Issued Date
Reserve for ESD request.
Compal Secret Data
2012/01/15
Deciphered Date
2013/01/15
Title
HD Audio Codec_ALC269Q-VC
Size
C
Document Number
Rev
0.3
VAUS5 LA9001P M/B

A
EMI
HDA_SYNC_AUDIO
Sheet
E
30
of
50
www.qdzbwx.com
Pin Assignment
+3VLP
1
+3VALW
3.3V +/- 5%
Vcc
R1562 100K +/- 5%
Board ID
R1564
0
0
8.2K +/- 5%
1
18K +/- 5%
2
33K +/- 5%
3
C1254
100P_0402_50V8J
KSO[0..15]
<32>
KSO[0..15]
KSI[0..7]
<32>
KSI[0..7]
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
<12> PM_SLP_S3#
<12> PM_SLP_S5#
<12> EC_SMI#
<23> CMOS_ON#
3
<26>
LAN_WAKE#
R1588 1
2 0_0402_5%
<23>
<28>
EC_INVT_PWM
EC_TACH
<28>
EC_FAN_PWM
<25>
<25>
<12,43>
1
@ R1582
10K_0402_5%
NUM_LED#: NC
R1586 2
1 0_0402_5%
122
123
XCLKO
MP
PVT
DVT
EVT
V
V
V
BEEP#
NOVO#
ACOFF
BEEP#
NOVO#
ACOFF
R1562
100K_0402_5%
<30>
<32>
<37>
2
21
23
26
27
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
EC_VDD/AVCC
BATT_TEMP
BATT_TEMP
ADP_I
<36>
PVT
BRDID
<36,37>
1
63
64
65
66
75
76
BRDID
APU_IMON
R1564
8.2K_0402_5%
<43>
68
70
71
72
TP_CLK
R1567 1
2 4.7K_0402_5%
TP_DATA
R1569 1
2 4.7K_0402_5%
TL_CLK
R341 1
2 2.2K_0402_5%
TL_DATA
R342 1
EC_FAN_PWM
R1561 1
EC_TACH
R1581 1
2 10K_0402_5%
EC_SMB_DA2_SUS
R1575 1
2 2.2K_0402_5%
EC_SMB_CK2_SUS
R1576 1
2 2.2K_0402_5%
EC_SMB_DA1
R1577 1
2 2.2K_0402_5%
EC_SMB_CK1
R1574 1
2 2.2K_0402_5%
EC_MUTE#
R1565 1
2 10K_0402_5%
EC_PME#
R1585 1
VGA_GATE#
R1566 1
LID_SW#
R344 1
WLAN_USB_ON#
R1583 1 AOAC@ 2 100K_0402_5%
PCH_PWR_EN
R1572 1
2 2.2K_0402_5%
2 10K_0402_5%
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00
83
84
85
86
87
88
97
98
99
109
EC_MUTE#
USB_ON#
TL_CLK
TL_DATA
TP_CLK
TP_DATA
EC_MUTE# <30>
USB_ON#
<32,33>
TL_CLK <22>
TL_DATA <22>
TP_CLK <32>
TP_DATA <32>
VGATE
VGATE
VLDT_EN
NTC_V_R
2 R1571
SPI Flash ROM
GPIO
Bus
GPIO
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
ECAGND
V18R
119
120
126
128
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
110
112
114
115
116
117
118
PCH_PWR_EN
PCH_PWR_EN
AOAC_ON#
AOAC_ON#
ENBKL
AOAC@
WLAN_USB_ON#_R
BATT_CHG_LED#
CAP_LED#
R1519
BATT_LOW_LED#
SYSON
VSB_ON_R
EC_LID_OUT#
Turbo_V
H_PROCHOT#_EC
MAINPWON_R
BKOFF#
PBTN_OUT#
1 0_0402_5%
EC_RSMRST#
EC_LID_OUT#
R1580 2
R1591 2
<36>
<25>
<22>
WLAN_USB_ON#
BATT_CHG_LED#
CAP_LED#
<32>
PWR_LED#
<32>
BATT_LOW_LED#
<32>
SYSON <34,39,40>
VR_ON <43>
1
R216
WLAN_USB_ON#
2 10K_0402_5%
2 47K_0402_5%
VSB_ON
<36>
KB9012A2 work around

R343
47K_0402_5%
Turbo_V <36>
PROCHOT
<36>
MAINPWON
<36,38,7>
1 0_0402_5%
1 0_0402_5%
EMC Request
SYSON
BKOFF# <22,23>
PBTN_OUT# <12>
@
1
C1272
ACIN <16,37>
EC_ON <38>
ON/OFF
<32>
LID_SW#
<32>
SUSP# <34,39,40,41,42>
EC_SMB_CK2_SUS
C1268
2
100P_0402_50V8J
EC_SMB_DA2_SUS
C1267
2
100P_0402_50V8J
BATT_TEMP
2
100P_0402_50V8J
2
100P_0402_50V8J
+V18R
ACIN
C1266
1
C1270
4.7U_0603_6.3V6K
ACIN
R1573
1
PCH_PWR_EN
R1634
VSB_ON
KB9012QF A3 LQFP 128P_14X14
H_PROCHOT#
D
H_PROCHOT#_EC
R336
<36,43,7>
2
4.7K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
C1269
47P_0402_50V8J
R1579
2.2K_0402_5%
EC_SMB_DA2_SUS 6
EC_SMB_DA2
EC_SMB_DA2
<16,28>
EC_SMB_CK2
<16,28>
DMN66D0LDW-7 2N_SOT363-6
Q143A
EC_SMB_CK2_SUS
EC_SMB_CK2
Compal Secret Data
Issued Date
DMN66D0LDW-7 2N_SOT363-6
Q143B
2012/01/15
Deciphered Date
2013/01/15
C
0.1U_0402_10V6K
@
<12>
LID_SW#
SUSP#
2
G
Q82
2N7002H_SOT23-3
2 100K_0402_5%
<25>
+3VLP
@
2
1K_0402_1%
ACIN
EC_ON
2 10K_0402_5%
C1265
124
<32>
<12>
<12>
VGA_GATE#
ECAGND
+3VS
<43>
VLDT_EN <41>
NTC_V <36>
1 0_0402_5%
SPI Device Interface
+3VS
R1578
2.2K_0402_5%
max
+3VALW
11
24
35
94
113
C1271
20P_0402_50V8
R1587
100K_0402_5%
67
9
22
33
96
111
125
XCLKI/GPIO5D
XCLKO/GPIO5E
RTC_CLK
EC_TX
EC_RX
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
V
V
V
VAD_BID
0 V
0.289
0.538
0.875
Title

BIOS & EC I/O Port

Custom
Rev
0.3
VAUS5 LA9001P M/B
Date:
www.qdzbwx.com
<10,14>
EC_INVT_PWM
EC_TACH
EC_PME#
EC_TX
EC_RX
FCH_PWRGD
EC_FAN_PWM
FCH_PWRGD
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
typ
+3VS
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
77
78
79
80
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2_SUS
EC_SMB_DA2_SUS
<36,37> EC_SMB_CK1
<36,37> EC_SMB_DA1
<7> EC_SMB_CK2_SUS
<7> EC_SMB_DA2_SUS
AD Input
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
V
V
V
V AD_BID
0 V
0.250
0.503
0.819
+3VALW
PWM Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
min
10K_0402_5%
EC_RST#
EC_SCI#
BATT_LEN#
EC_SCI#
BATT_LEN#
VAD_BID
0 V
0.216
0.436
0.712
<12>
<36>
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
12
13
37
20
38
R1266
USB_ON# 1
U51
<10,14> CLK_PCI_EC
<10,26> PLT_RST#
2
47K_0402_5%
C1264
0.1U_0402_16V4Z
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
R1563
1
2
3
4
5
7
8
10
+3VALW
+EC_VCCA
AGND/AGND
+3VALW
R1560 2
+5VALW
69
1 22P_0402_50V8J
GND/GND
GND/GND
GND/GND
GND/GND
GND0
<12> GATEA20
<12> KBRST#
<10> SERIRQ
<10,25> LPC_FRAME#
<10,25> LPC_AD3
<10,25> LPC_AD2
<10,25> LPC_AD1
<10,25> LPC_AD0
1 10_0402_5%
@
C1263
C1259
1000P_0402_50V7K
C1260
1000P_0402_50V7K
C1261
1000P_0402_50V7K
C1258
0.1U_0402_16V4Z
C1257
0.1U_0402_16V4Z
1
C1262
0.1U_0402_16V4Z
2 ECAGND
1
2
L39
FBM-11-160808-601-T_0603
+EC_VCCA
C1256
0.1U_0402_16V4Z
+3VALW
C1255
0.1U_0402_16V4Z
L38
FBM-11-160808-601-T_0603
1
2
Sheet

E
31
of
50
+3VALW
INT_KBD Conn.
2 @ 100P_0402_50V8J
KSO1
C1279 1
2 @ 100P_0402_50V8J
KSO15
C1280 1
2 @ 100P_0402_50V8J
KSO7
C1276 1
2 @ 100P_0402_50V8J
KSO6
C1281 1
2 @ 100P_0402_50V8J
KSI2
C1282 1
2 @ 100P_0402_50V8J
KSO8
C1283 1
2 @ 100P_0402_50V8J
KSO5
C1284 1
2 @ 100P_0402_50V8J
KSO13
C1285 1
2 @ 100P_0402_50V8J
KSI3
C1286 1
2 @ 100P_0402_50V8J
C1287 1
2 @ 100P_0402_50V8J
KSO14
C1288 1
2 @ 100P_0402_50V8J
KSO11
C1289 1
2 @ 100P_0402_50V8J
KSI7
C1290 1
2 @ 100P_0402_50V8J
KSO10
C1291 1
2 @ 100P_0402_50V8J
KSI6
C1292 1
2 @ 100P_0402_50V8J
KSO3
C1293 1
2 @ 100P_0402_50V8J
KSI5
C1294 1
2 @ 100P_0402_50V8J
KSO4
C1295 1
2 @ 100P_0402_50V8J
KSI4
C1296 1
2 @ 100P_0402_50V8J
KSI0
C1297 1
2 @ 100P_0402_50V8J
KSO9
C1298 1
2 @ 100P_0402_50V8J
R91 1
C1299 1
2 @ 100P_0402_50V8J
C1300 1
KSI1
+5VS
<31> CAP_LED#
2 @ 100P_0402_50V8J
<31>
<31>
NOVO#
D40
NOVO#
ON/OFF
ON/OFF
NOVO_BTN#
1
DAN202UT106_SC70-3
For debug
SW 4
+3VLP
4
G
G
KSO12
R1592
100K_0402_5%
28
27
C1275 1
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
2 300_0402_5%
CAP_LED#
GND1
GND2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NTC017-DA1J-D160T_4P
DEBUG@
R1593
100K_0402_5%
<31>
KSO2
KSO0
<31>
KSO[0..15]
KSI[0..7]
KSO[0..15]
ME@
JKB1
6
5
KSI[0..7]
J16
ON/OFF
SHORT PADS
ACES_88514-02601-071
Power Board
2
+3VALW +5VALW
2A/Active Low
+USB2_VCCA
C1306
<31,33>
USB_ON#
R88
USB20_N0
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
W=80mils
8
7
6
5
0.1U_0402_10V6K
2
C1307
USB_OC1#
G547I2P81U_MSOP8
C1324
C8247
R02
U55
1
2
3
4
1 @
R89
USB20_N1
0.1U_0402_10V6K
15P_0402_50V8J
USB20_P0_R
USB20_N0_R
R90
1
USB20_N5
300_0402_5%
C8249
USB20_P1_R
USB20_N1_R
15P_0402_50V8J
300_0402_5%
15P_0402_50V8J
USB20_P5_R
USB20_N5_R
R1625
1
3
2
@
0_0402_5%
<30>
<30>
DMIC_CLK
DMIC_DATA
DMIC_CLK
DMIC_DATA
L52
USB20_N5
<12>
USB20_P5
USB20_P5
USB20_N5_R
USB20_P5_R
<30> PLUG_IN#
<30> HP_OUTL
<30> HP_OUTR
PLUG_IN#
HP_OUTL
HP_OUTR
<30>
EXT_MIC
W CM-2012-900T_4P
1
2
R1626
@ 0_0402_5%
EXT_MIC
25
26
R1614
R1619
2
@
0_0402_5%
L50
USB20_N0
<12>
USB20_P0
USB20_P0
2
@
0_0402_5%
USB20_N0_R
USB20_P0_R
<12>
USB20_N1
<12>
USB20_P1
USB20_N1
USB20_P1
ACES_51524-0080N-001
SP01001A900
TouchPAD Module
3
+3VS
JTP1
USB20_N1_R
USB20_P1_R
W CM-2012-900T_4P
1
2
@ 0_0402_5%
8
7
0.1U_0402_16V4Z
GND1
GND2
<31>
<31>
TP_CLK
TP_DATA
@ C1302
100P_0402_50V8J
6
5
4
3
2
1
TP_CLK
TP_DATA
FCH_SCLK1
FCH_SDATA1
<12> FCH_SCLK1
<12> FCH_SDATA1
C1303 @
100P_0402_50V8J
@ D42
PSOT24C_SOT23-3
W CM-2012-900T_4P
1
2
@ 0_0402_5%
R1624
R1615
ME@
C1301
ACES_88514-02401-071
SP010015W 00
L51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
<12>
USB20_N0
10
9
GND
GND
6
5
4
3
2
1
www.qdzbwx.com
<12>
USB20_N5
G2
G1
JCR1 ME@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NOVO_BTN#
PW R_LED#
LID_SW #
ON/OFF
8
7
6
5
4
3
2
1
ME@
<12>
C8248
<31> PW R_LED#
<31> LID_SW #
+3VS +USB2_VCCA
+3VS
470P_0402_50V7K
300_0402_5%
8
7
6
5
4
3
2
1
+USB2_VCCA
0.1U_0402_10V6K
C1305
C1321
0.1U_0402_16V7K
1
2
1 @
0.1U_0402_10V6K
C1304
+5VALW
IO Board
JPW R1
ACES_88514-00601-071
SP010014M00
+5VALW
<31>
<31>
LED Board
BATT_LOW _LED#
BATT_CHG_LED#
PW R_LED#
BATT_LOW _LED#
BATT_CHG_LED#
6
5
4
3
2
1
JLED1 ME@
8
6 G2 7
5 G1
4
3
2
1
ACES_51524-0060N-001
SP010014M10
A
Compal Secret Data
2012/01/15
Issued Date
Deciphered Date
2013/01/15
C
Title

KB /SW /LPC Debug Conn.
Size
Document Number
Custom
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
32
of
50
R1605
2
@
0_0402_5%
WCM-2012-900T_4P
USB20_LN_R
USB20_LP
I/O2
<12>
USB20_LN
USB20_LP
D45
USB20_LN
I/O4
GND
VDD
I/O1
I/O3
4
L43
1
R1608
USB20_LN_R
USB20_LP_R
1
2
@ 0_0402_5%
R86
300_0402_5%

suggestion
+USB3_VCCA
<12>
2
4
USB20_LP_R
C8245
15P_0402_50V8J
R1609
+USB3_VCCA
1
@ 2
0_0402_5%
W=80mils
WCM-2012-900T_4P
USB30_RX_R_N0
D44
9 10
USB30_RX_R_P0
USB30_TX_R_N0
USB30_TX_R_P0
@
1
1USB30_RX_R_N0
2USB30_RX_R_P0
4USB30_TX_R_N0
5USB30_TX_R_P0
<12>
<12>
USB30_RX_N0
USB30_RX_N0
USB30_RX_P0
USB30_RX_P0
YSCLAMP0524P_SLP2510P8-10-9
<12>
USB30_TX_N0
<12>
USB30_TX_P0
USB30_TX_C_P0
USB30_RX_R_N0
JUSB1
9
1
8
3
7
2
6
4
5
USB30_TX_R_P0
4
3
L44
1
2
R1612 0_0402_5%
@
R1613 1
@ 2
0_0402_5%
C1309
0.1U_0402_16V7K
1
2 USB30_TX_C_N0
C1310
0.1U_0402_16V7K
USB30_RX_R_P0
USB30_TX_R_N0
USB20_LP_R
USB20_LN_R
USB30_RX_R_P0
USB30_RX_R_N0
4
L45
2
0_0402_5%
@
R1616
LP2
10
11
12
13
GND
GND
GND
GND
TAITW_PUBAU1-09FNLSCNN4H0
ME@
WCM-2012-900T_4P
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
USB30_TX_R_N0
USB30_TX_R_P0
Place TX AC coupling Cap (C1309,C1310). Close to connector

2A/Active Low
+5VALW
C1308
0.1U_0402_16V7K
1
2
<31,32>
USB_ON#
+USB3_VCCA
U52
1
2
3
4
R02
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
For EMI request

W=80mils
8
7
6
5
USB_OC0#
<12>
G547I2P81U_MSOP8
3
C1311
1
+
1 C1312
470P_0402_50V7K
C1224
1000P_0402_50V7K
www.qdzbwx.com
220U_6.3V_M
FOR EMI
Compal Secret Data
Issued Date
2012/01/15
Deciphered Date
For EMI request

2013/01/15

Title
Custom
USB3.0 ports
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
E
33
of
50
+5VALW TO +5VS
+3VALW TO +3VS
R205 for power consumption easily rework
+1.5V_IO to +1.5VS Q91
+1.5V_IO PMV65XP_SOT23-3
C1318
1U_0603_10V6K
Q89
S 2N7002K_SOT23-3
100K_0402_5%
R1633
3VS_GATE_R
SUSP
C1322
0.01U_0603_25V7K
2
G
270K_0402_5%
1.5VS_GATE 1 R1635
D
SUSP# 2
G
C1323
0.01U_0603_25V7K
2 SUSP
G
Q96
2N7002K_SOT23-3
@
1.5VS_GATE_R
22K_0402_5%
Q98
2N7002K_SOT23-3
2 SUSP
G
Q86
2N7002K_SOT23-3
@
R1631
470_0603_5%
@
+5VALW
5VS_GATE_R
Q88
2N7002K_SOT23-3
2
G
SUSP
R1623
3VS_GATE 1
2
1
5VS_GATE 2 R1622 1
82K_0402_5%
D
R1621
270K_0402_5%
2 SUSP
G
Q85
2N7002K_SOT23-3
@
R1620
150K_0402_5%
R1618
470_0603_5%
@
C1317
10U_0603_6.3V6M
C1325
10U_0603_6.3V6M
+VSB
+1.5VS
R205
0_0805_5%
2
1
1
@
C1326
C1327
10U_0603_6.3V6M
1U_0603_10V6K
2
2
R1617
470_0603_5%
@
+1.5VS_Q 1
1
1
1
C1315
1U_0603_10V6K
1 2
C1314
10U_0603_6.3V6M
+3VS
1 2
C1313
10U_0603_6.3V6M
+3VALW
U54
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
6
3
5
C1316
10U_0603_6.3V6M
2
+VSB
+5VS
U53
8
1
7
2
6
3
5
+5VALW
C1329
0.1U_0402_16V4Z
+1.1VALW to +1.1VS
1
SYSON
SYSON
2
2
IN
GND
<31,39,40>
R1640
100K_0402_5%
Q100
@
IN
R1639 @
100K_0402_5%
OUT
SUSP#
GND
<31,39,40,41,42>
2 SUSP
G
Q29
2N7002K_SOT23-3
@
1.1VS_GATE_R
82K_0402_5%
SYSON#
Q99
Q32
S 2N7002K_SOT23-3
R391 2
SUSP
OUT
SUSP
<39,40>
@
R1638
100K_0402_5%
2
2
3
1.1VS_GATE 1
2
G
SUSP
R3861
470_0603_5%
@
S
R390
270K_0402_5%
@
R1637
100K_0402_5%
R1636
100K_0402_5%
+VSB
+5VALW
+5VALW
+RTCBATT
+1.1VALW U15
+1.1VS
8
1
7
2
1
1
1
6
3
5
C4261
C4271
C4281
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0603_10V6K
2
2
2
C4291
0.1U_0402_25V6
1 2
R1627
470_0603_5%
@
2 SYSON#
G
Q93
2N7002K_SOT23-3
@
R1629
470_0603_5%
@
2 SUSP
G
Q95
2N7002K_SOT23-3
@
www.qdzbwx.com
1 2
+0.75VS
+1.5V
2011/06/30
Issued Date
Compal Secret Data
2013/06/30
Deciphered Date
A
Title
DC-DC INTERFACE
Size
Document Number
Custom
Date:
VAUS5 LA9001P M/B
Sheet
E
34
of
Rev
0.3
50
VIN
1
2
PC104
1000P_0402_50V7K
PC103
100P_0402_50V8J
GND
GND
PL101
SMB3025500YA_2P
1
2
PC102
100P_0402_50V8J
PF101
7A_24VDC_429007.WRML
1
2 APDIN1
APDIN
PC101
1000P_0402_50V7K
JDCIN1
ACES_87302-0401-003
1
1
2
2
+3VLP
PR131
560_0603_5%
1
2
PR132
560_0603_5%
1
2
PD109
RB751V-40_SOD323-2
2
1
@ MAXEL_ML1220T10
PR127
0_0402_5%
+RTCBATT
JRTC2
+CHGRTC
RTCVREF
PD108
RB751V-40_SOD323-2
RTC Battery
www.qdzbwx.com
Compal Secret Data
Issued Date
2011/10/12
2013/10/12
Deciphered Date
Title
PWR DCIN / Vin Detector /Pre-charge
Date:
Rev
0.1
LA9001P
Sheet
1
35
of
48
VMB2
VMB
PF201
12A_65V_451012MRL
1
2
PL201
SMB3025500YA_2P
1
2
BATT+
1
2
PC202
0.01U_0402_25V7K
VL
+3VS
+EC_VCCA
1
D
1
OTP_N_002 2
@ PR209
10K_0402_1%
6
5
2
ADP_OCP_2 1
@ PR210
27.4K_0402_1%
G718TM1U_SOT23-8
2 ADP_OCP_1
G
@ PQ201
SSM3K7002FU_SC70-3
PR227
0_0402_5%
@ PR232
2
@ PR212
@PR212
0_0402_5%
1
2
PROCHOT
+3VLP
Turbo_V_2
2
PR231
0_0402_5%
PR211
10K_0402_1%
PH201
100K_0402_1%_NCP15WF104F03RC
1
@ PR230
47K_0402_1%
0_0402_5%
2
1
PR235
0_0402_5%
@ PR234
0_0402_5%
ECAGND
Turbo_V
<31>
<31>
@ PR207
21.5K_0402_1%
H_PROCHOT#
2
OTP_N_003
<31,43,7>
MAINPWON
PR205
1.65K_0402_1%
PR206
12.7K_0402_1%
@ PU201
1
VCC TMSNS1
2
GND RHYST1
3
OT1 TMSNS2
4
OT2 RHYST2
@ PR213
0_0402_5%
1
2
<31,37>
PR208
100K_0402_1%
<31,38,7>
ADP_I
A/D
BATT_TEMP <31>
1
2
PR204
10K_0402_5%
@ PC203
0.1U_0603_16V7K
<31,37>
+3VALW
<31,37>
EC_SMB_DA1
For KB930 --> Keep PU201 circuit

(Vth = 1.25V)
For KB9012 (Red circle) --> Remove PU201 circuit, but keep PR206
PH201, PR205, PR211,PQ201,PR208,PR212
PH1 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
EC_SMB_CK1
1
2
PR203
6.49K_0402_1%
PC201
1000P_0402_50V7K
@ JBATT3
SUYIN_200082GR007G201ZR
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
GND 9
GND
2
1
PR202
100_0402_1%
EC_SMCA
EC_SMDA
2
1
PR201
100_0402_1%
@ JBATT2
SUYIN_200082GR007G201ZR
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
GND 9
GND
90W(DIS) : PR205=4.42K
PR210=27.4K
65W(UMA) : PR205=402(SD034020080)
PR210=5.11K
@ PR233
2
+3VLP
+3VALW
VL
PQ203
2N7002KW_SOT323-3
<31>
<31>
SPOK
PCH_PWR_EN
@ PR229
@PR229
0_0402_5%
2
BATT_LEN#
1
@ PR228
@PR228
0_0402_5%
<31>
VSB_ON
PR224
1K_0402_5%
2
1
2
2
1
2
PC206
0.1U_0603_25V7K
2
G
PQ204
2N7002W-T/R7_SOT323-3
3
<38,41>
PR226
100K_0402_1%
@ PR225
10K_0402_1%
2
G
PC207
1U_0402_6.3V6K
PR223
10K_0402_1%
+3VLP
+VSBP
PR222
100K_0402_1%
RTCVREF
1
PU202A
LM393DG_SO8
2
G
PQ202
2N7002KW_SOT323-3
PR221
180K_0402_1%
PR220
22K_0402_1%
1
2
PC205
0.22U_0603_25V7K
BATT_OUT <37>
8
P
O
4
3
2
2VREF_8205
2
1
PR216
100K_0402_1%
2
1
2
2
1
PR215
100K_0402_1%
+VSBP
@ PJ201
JUMP_43X39
2
1
2
+VSB
1
PR236
0_0402_5%
Compal Secret Data
Issued Date
2011/10/12
2013/10/12
Deciphered Date
Title

PWR-BATTERY CONN/OTP
Date:
www.qdzbwx.com
PR218
10M_0402_5%
1
2
B+
PR214
100K_0402_1%
PR217
887K_0402_1%
PR219
10K_0402_1%
1
2
PQ205
TP0610K-T1-E3_SOT23-3
PC204
0.01U_0402_25V7K
VMB2
+3VALW
<31>
NTC_V
P2
47K_0402_1%
Rev
0.1
LA9001P
Sheet
1
36
of
48
B+
P3
P2
PQ302
AO4423_SO8
DISCHG_G
18
DH_CHG
ILIM
BTST
17
BST_CHG
2
1
2ACOFF-1
1SS355_SOD323-2
REGN
16
15
1
PD303
RB751V-40_SOD323-2
BQ24727VDD
PC376
1U_0603_25V6K
2 PACIN
G
S
PC311
0.1U_0603_25V7K
2
1
PQ310
AO4466L_SO8
PQ313
2N7002KW _SOT323-3
14
11
PR327
6.8_0603_5%
2
1 12
2
G
PR324
PC314
2.2_0603_5%
0.047U_0603_16V7M
1
2
2
1
2N7002W -T/R7_SOT323-3
PR320
0.01_1206_1%
1
BATT+
@ PR322
4.7_1206_5%
SRP
SRN
@ PC377
680P_0603_50V7K
PC372
10U_0805_25V6K
2
1
HIDRV
SA000051W00
SCL
PHASE
PL302
10UH_PCMB063T-100MS_4A_20%
1
2
CHG
PU301
BQ24727RGRR_VQFN20_3P5X3P5
LX_CHG
PC371
10U_0805_25V6K
2
1
LX_CHG
PQ312
AO4466L_SO8
SDA
2
1 13
PR328
10_0603_5%
10
19
PC313
1U_0603_25V6K
1
2
IOUT
BM
1
2
PR323
316K_0402_1%
+3VALW
BQ24727VCC
3
2
1
20
5
6
7
8
EC_SMB_CK1
21
3
2
1
<31,36>
PD301
1
ACN
ACP
PR319
10_1206_5%
LODRV
EC_SMB_DA1
<31,36>
PC310
0.1U_0603_25V7K
TP
GND
SRP
PC312
100P_0603_50V8 8
PD302
1SS355_SOD323-2
2
VCC
SRN
PC370
0.1U_0603_25V7K
5
6
7
8
1
PR310
10K_0603_1%
2
3
CMPOUT
ACDET
PR306
200K_0402_1%
2
PR309
100K_0402_1%
4
CMPIN
2
@ PR313
4.7M_0603_1%
2
1
3
ACOK
ADP_I
PR326
100K_0402_1%
D
<31,36>
PQ306
DTC115EUA_SC70-3
PQ309
P2
64.9K_0603_1%
PR321
1
2ACOFF-1 2
10K_0402_5%
BATT_OUT
1
2
PR316
2.2K_0402_5%
PR315
2.2K_0402_5%
1
2
PR314
2
1
390K_0603_1%
@ PR312
39.2K_0402_1%
2
1
PR305
47K_0402_1%
PR325
0_0402_5%
<36,37>
<36,37>
ACOFF
PQ311
DTC115EUA_SC70-3
PR317
1
+3VALW
3
PR318
47K_0402_1%
1
2
PACIN
VIN
PC309
0.1U_0603_25V7K
2
1
16251_SN
ACPRN
<37>
1
P2-2
ACON
<31>
PR308
150K_0402_1%
PQ307B
2N7002KDW-2N_SOT363-6
1
PACIN
PQ308
2N7002KW _SOT323-3
2
BATT_OUT
G
PR307
20K_0402_1%
1DISCHG_G-1
1
PC308
0.1U_0603_25V7K
1
2
+3VALW
P2-1
VIN
ACN
PQ305
DTC115EUA_SC70-3
PQ307A
2N7002KDW -2N_SOT363-6
PR304
200K_0402_1%
1
2
ACP
8
7
6
5
4
1
2
3
PC307
2200P_0402_50V7K
PC306
4.7U_0805_25V6-K
1
2
PC305
4.7U_0805_25V6-K
1
2
PC304
5600P_0402_25V7K
PQ303
AO4407A_SO8
CHG_B+
PC303
4.7U_0805_25V6-K
1
2
PR301
47K_0402_5%
PQ304
DTA144EUA_SC70-3
PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%
PL301
1UH_MNR-4018-1R0N-F_3A_30%
1
2
SH00000Q100
PR302
0.01_1206_1%
8
7
6
5
@ PC315
10U_0805_25V6K
1
2
3
1
2
3
8
7
6
5
VIN
@ PC302
10U_0805_25V6K
PQ301
AO4407A_SO8
DL_CHG
PC374
0.1U_0603_25V7K
0V
CHGVADJ
4V
4.2V
1.882V
4.35V
3.2935V
BQ24727VDD
PR337
10K_0402_1%
1
2
PR336
10K_0402_1%
PR335
47K_0402_1%
PQ316
ACPRN
2
G
3
<37>
ACIN
<16,31>
PACIN
1
PR339
2
VCHLIM need over 95mV
IREF=0.254V~3.048V
2N7002KW_SOT323-3
IREF=1.016*Icharge
CC=0.25A~3A
@ PC375
0.1U_0603_25V7K
12K_0402_1%
For disable pre-charge circuit.
2011/10/12
Issued Date
Compal Secret Data
2013/10/12
Deciphered Date
Title
Size
Date:
CHARGER
Document Number
Rev
0.1
LA9001P
Sheet
1
37
of
48
www.qdzbwx.com
Vcell
CHGVADJ=(Vcell-4)/0.10627
1
PC373
0.1U_0603_25V7K
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
PC401
1U_0603_10V6K
2VREF_8205
RT8205_B+
+5VALW P
@ PJ403
JUMP_43X118
2
1
2
1
+3VALW
PR401
13K_0402_1%
1
2
PR402
30K_0402_1%
1
2
PR403
20K_0402_1%
1
2
PR404
19.6K_0402_1%
1
2
+5VALW
RT8205_B+
5
6
7
8
PC410
0.1U_0603_25V7K
2
1
PR408 PC413
2.2_0603_5% 0.1U_0603_25V7K
2 1
2
BST_5V 1
21
UG_5V
20
LX_5V
19
LG_5V
1
2
5
6
7
8
2
PC422
0.1U_0603_25V7K
2VREF_8205
4
Typ: 175mA
+3.3VALWP OCP(min)=5.81A
+5VALWP OCP(min)=8.44A
PR414
100K_0402_1%
2
1
VL
PR418
2.2K_0402_5%
2
1
PR413
0_0402_5%
2
1
PQ406
DTC115EUA_SC70-3
PC423
4.7U_0603_6.3V6M
2
2
1
PR417
40.2K_0402_1%
<31,36,7> MAINPWON
Compal Secret Data
2011/10/12
Issued Date
Deciphered Date
2013/10/12
5
www.qdzbwx.com
PQ405A
2N7002KDW -2N_SOT363-6
PC421
4.7U_0805_10V6K
1
2
1
RT8205_B+
PC417
150U_B2_6.3VM_R35M
VL
PQ405B
2N7002KDW -2N_SOT363-6
1
2
3
2
1
1
2
PC420
1U_0603_10V6K
2
1
ENTRIP2
PR412
100K_0402_1%
@
B
+5VALWP
PC419
680P_0603_50V7K
RT8205EGQW _W QFN24_4X4
PR410
4.7_1206_5%
PL402
4.7UH +-20% PCMC063T-4R7MN 5.5A
1
2
B+
ENTRIP1
PQ402
AO4406AL_SO8
PC409
2200P_0402_50V7K
2
1
SPOK <36,41>
22
3
2
1
23
PQ404
AO4456_SO8
NC
24
18
VREG5
LGATE1
EN
PC408
4.7U_0805_25V6-K
2
1
2
FB1
ENTRIP1
REF
4
TONSEL
LGATE2
13
PC407
4.7U_0805_25V6-K
2
1
ENTRIP2
PHASE1
PR411
499K_0402_1%
1
2
1
2
3
FB2
ENTRIP2
UGATE1
PHASE2
PC418
680P_0603_50V7K
2
1
VFB=2.0V
UGATE2
<31> EC_ON
BOOT1
VIN
PQ403
AO4712_SO8
12
PGOOD
BOOT2
17
LG_3V
VREG3
1
PC415
150U_B2_6.3VM_R35M
8
7
6
5
PR409
4.7_1206_5%
2
1
PL401
4.7UH +-20% PCMC063T-4R7MN 5.5A
1
2
PR406
66.5K_0402_1%
2
VO1
GND
1
2
3
PR407
2 1
2 BST_3V 9
2.2_0603_5%
PC412
UG_3V 10
0.1U_0603_25V7K
11
LX_3V
VO2
16
15
+3VALWP
P PAD
SKIPSEL
25
14
AO4466L_SO8
PU401
PQ401
PR405
130K_0402_1%
1
2
PC411
4.7U_0805_10V6K
8
7
6
5
PC406
2200P_0402_50V7K
2
1
PC404
4.7U_0805_25V6-K
2
1
+3VLP
ENTRIP1
Typ: 175mA
PC403
4.7U_0805_25V6-K
2
1
@ PJ401
JUMP_43X118
2
1
2
1
PC402
0.1U_0603_25V7K
2
1
PC405
0.1U_0603_25V7K
2
1
B+
@ PJ402
JUMP_43X118
1
2
1
+3VALW P
Title

3VALWP/5VALWP
Size
Document Number
Custom
Date:
Rev
0.1
LA9001P
Sheet
1
38
of
48
@PJ501
@
PJ501
1
Hi
Hi
On
On
S3
Lo
Hi
On
On
On
Off
(Hi-Z)
+1.5VP
PQ503
TPCA8065-H_PPAK56-8-5
Lo
Lo
Off
Off
Off
@ PJ5025
JUMP_43X39
B+
LX_1.5V
3
2
1
S4/S5
JUMP_43X118
UG_1.5V
S0
0.75VSP
VTT_REFP
PC501
4.7U_0805_25V6-K
1.5VP
S5
S3
STATE
PC509
4.7U_0805_25V6-K
1.5V_B+
Note: S3 - sleep ; S5 - power off

2
PR507
PC502
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.5V-1
1
2
BST_1.5V
3
2
1
2
1
PC505
330U_D2_2.5VY_R9M
@ PC510
680P_0402_50V7K
PQ502
16
1
S
PR508
5.76K_0402_1%
11
2
1
PR502
5.1_0603_5%
10
+5VALW
+3VALW
+1.5VP OCP(min)=18.7A
+1.5VP OCP(max)=23.2A
PC511
1U_0603_10V6K
PGOOD_1.5V
+1.5VP
@ PJ505
JUMP_43X118
1
2
1
+1.5V_IO
<34,40> SUSP
FB=0.75V
To GND = 1.5V
To VDD = 1.8V
2
1
PR510
5.9K_0402_1%
2
1
@ PQ501
2N7002KW _SOT323-3
2
G
VDD
PR505
8.66K_0402_1%
2
1
@ PR506
4.7_1206_5%
PR501
887K_0402_1%
2
1 1.5V_B+
@ PC508
0.1U_0402_16V7K
PC512
1U_0402_16V6K
PGOOD
TON
PR504
0_0402_5%
1
2
<31,34,40> SYSON
PHASE
17
UGATE
18
BOOT
S5
8
S5_1.5V
S3
FB
VDDQ
PR503
0_0402_5%
1
2
<31,34,40,41,42> SUSP#
+1.5VP
12
VDDP
1
2
PC507
0.033U_0402_16V7K
19
VTTREF
13
CS
2
1
PR509
10K_0402_5%
PC503
1U_0603_10V6K
2
1
14
PGND
RT8207MZQW _W QFN20_3X3
LG_1.5V
GND
15
LGATE
VTTSNS
+1.5VP
VLDOIN
VTTGND
20
PAD
+VTT_REFP
VTT
PU501
21
S3_1.5V
PC504
10U_0805_25V6K
PC506
10U_0805_25V6K
+0.75VSP
PL502
1UH_PCMC063T-1R0MN_11A_20%
1
2
@ PJ506
JUMP_43X118
1
2
1
+1.5V
1.8VSP_FB
1
2
PC517
22U_0805_6.3VAM
1
2
PC514
68P_0402_50V8J
2
1
@
@ PC532
0.1U_0402_10V7K
PC516
22U_0805_6.3VAM
1
1 2
NC
1
4
PG
NC
+1.8VSP
+1.8VSP
@ PJ503
JUMP_43X118
1
2
1
+1.8VGS
1.8VSP max current=4A

FB=0.6Volt
PR515
10K_0402_1%
2
RB751V-40_SOD323-2
PR512
20K_0402_1%
+0.75VS
PR514
1M_0402_5%
FB
EN
PC515
PR511
680P_0603_50V7K 4.7_1206_5%
PD501
1
PR513
100K_0402_1%
LX
+0.75VSP
PL501
1UH_PH041H-1R0MS_3.8A_20%
1
2
1.8VSP_LX
SVIN
11
EN_1.8VSP
PC518
0.22U_0402_10V5K
<12,17,42> PXS_PWREN
LX
PVIN
TP
PVIN
PC513
22U_0805_6.3VAM
10
1.8VSP_VIN
+3VALW
PU502
SY8033BDBC_DFN10_3X3
@ PJ504
JUMP_43X118
1
2
1
Compal Secret Data
Issued Date
2011/10/12
Deciphered Date
2013/10/12
Title

PWR-+1.5VP/+0.75VSP/+1.8VSP
Custom
Date:
Rev
0.1
LA9001P
Sheet
D
39
of
48
www.qdzbwx.com
@ PJ507
JUMP_43X39
1
2
1
2
@PJ509
@
PJ509
S0
Hi
Hi
On
On
S3
Lo
Hi
On
On
0.75VSP
On
Off
(Hi-Z)
+1.5VP_DDR3L
PQ504
Lo
Off
Off
Off
PJ508
@
JUMP_43X39
B+
LX_1.5V_DDR3L
3
2
1
Lo
JUMP_43X118
UG_1.5V_DDR3L
S4/S5
VTT_REFP
PC519
4.7U_0805_25V6-K
1.5VP
S5
S3
PC520
4.7U_0805_25V6-K
1.5V_B+_DDR3L
STATE
Note: S3 - sleep ; S5 - power off

2
PR516
PC521
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.5V-1_DDR3L
1
2
BST_1.5V_DDR3L
1
+1.5VP_DDR3L
14
3
2
1
PR518
11K_0402_1%
2
1
13
1
+
2
PC525 @
680P_0402_50V7K
12
11
2
1
PR519
5.1_0603_5%
+5VALW
+3VALW
PC528
1U_0603_10V6K
PGOOD_1.5V_DDR3L
PR524
10K_0402_1%
2
1
PJ510
2
@
2
1
3
PC524
330U_D2_2.5VY_R9M
PR517 @
4.7_1206_5%
PQ505
16
PHASE
LG_1.5V_DDR3L
2
1
PR520
10K_0402_5%
PC527
1U_0603_10V6K
2
1
8
S5_1.5V_DDR3L
S5
FB
VDD
15
<BOM Structure>
PR523
887K_0402_1%
2
1 1.5V_B+_DDR3L
1
1
2
<34,39> SUSP
FB=0.75V
To GND = 1.5V
To VDD = 1.8V
JUMP_43X118
PJ511
+1.5VP_DDR3L
+1.5V
1
JUMP_43X118
PGOOD
VDDQ
PC526
0.033U_0402_16V7K
@ PC530
0.1U_0402_16V7K
@PQ506
2N7002KW _SOT323-3
2
G
17
VDDP
@ PR522
0_0402_5%
1
2
PC529
1U_0402_16V6K
UGATE
18
VTTREF
+1.5VP_DDR3L
<31,34,39,40> SYSON
CS
RT8207MZQW _W QFN20_3X3
@ PR521
0_0402_5%
1
2
<31,34,39,41,42> SUSP#
BOOT
19
20
GND
PGND
VTTSNS
10
+VTT_REFP_DDR3L
<BOM Structure>
LGATE
TON
VTTGND
PAD
VLDOIN
VTT
PU503
21
7
S3_1.5V_DDR3L
S3
1
2
PC523
10U_0805_25V6K
1
2
PC522
10U_0805_25V6K
+0.75VSP_DDR3L
PL1
1
2
PJ512
PR526
PR525
2
2
D
+0.75VS
PQ507
2N7002KW _SOT323-3
1
2
2
0_0402_5%
G
@ PR527
@ PC531
0.1U_0402_16V7K
DDR3L_EN#
<12>
@ PR528
0_0402_5%
1
2
JUMP_43X39
@
DDR3L_EN#=high
DDR3L_EN#=low
=>
=>
1.5V
1.35V
Compal Secret Data
Issued Date
2010/01/25
Deciphered Date
2012/07/11
Title

PWR-+1.5VP/+1.8VSP
Custom
Date:
Rev
0.1
LA9001P
Sheet
D
40
of
48
www.qdzbwx.com
<31,34,39,40> SYSON
+0.75VSP_DDR3L
12.7K_0402_1%
49.9K_0402_1%
PR601
2
PU601
SY8809DFC_DFN8_2X2
+1.1VALWP
1
2
PR604
+
2
PC622
22U_0603_6.3V6K
PC621
22U_0603_6.3V6K
1.1V_LX
PC605
2
GND
GND
PL601
0.47UH_PCMC063T-R47MN_17.5A_20%
47U_0805_6.3V6M
JUMP_43X118
LX
PC604
2
LX
PG
1 2
PJ607
2
+3VALW
FB
IN
JUMP_43X118
PC602
22U_0603_6.3V6K
1.1V_LX
EN
47U_0805_6.3V6M
PC603
2
47U_0805_6.3V6M
PC620
PJ601
2
+5VALW
D
150U_B2_6.3VM_R45M
1M_0402_5%
PC606
680P_0603_50V7K
PR602
PR603
4.7_1206_5%
0_0402_5%
PC601
@
0.1U_0402_10V7K
SPOK
<36,38>
8.45K_0402_1%
1
+1.1VALWP
PJ602
2
PC607
1
PR605
10K_0402_1%
+1.1VALW
1
JUMP_43X118
2
220P_0402_50V
@ PJ603
2
2
1
PC611
4.7U_0805_25V6-K
PC610
4.7U_0805_25V6-K
2
1
1
2
3
2
1
+1.2VSP
+5VALW
3
2
1
PR612
470K_0402_1%
1
+
2
PC616
2
1
PC613
1U_0603_6.3V6M
1U_0603_10V6K
11
TPS51212DSCR_SON10_3X3
PC615
TP
LG_+1.2VSP
220U_D2_4VY_R15M
DRVL
+1.2VSP_5V
RF
B+
PL602
1
2
V5IN
SW_+1.2VSP
4.7_1206_5%
VFB
JUMP_43X118
680P_0603_50V7K
SW
UG_+1.2VSP
PR611
RF_+1.2VSP
DRVH
EN
BST_+1.2VSP
PC617
2
1
FB_+1.2VSP
TRIP
10
AO4456_SO8
VBST
5
6
7
8
EN_+1.2VSP
PGOOD
PQ602
TRIP_+1.2VSP
PR610
2
47K_0402_1%
PC614
2
1
SUSP#
PR609
300K_0402_1%
1
2
1
<31,34,39,40,42>
VLDT_EN
0.1U_0402_16V7K
<31>
PR607
1
2
75K_0402_1%
PC612
0.1U_0603_25V7K
1
2
2.2_0603_5%
PU602
1
@ PR606
0_0402_5%
1
2
PR608
PC609
2200P_0402_50V7K
2
1
PC608
0.1U_0402_25V6
2
1
AO4406AL_SO8
PQ601
5
6
7
8
+1.2VSP_B+
+1.2VSP
@ PJ604
2
2
1
+1.2VS
1
JUMP_43X118
PR613
7.15K_0402_1%
2
1
+1.2VSP OCP(min)=15.34A
B
PU603
APL5508-25DC-TRL_SOT89-3
IN
OUT
GND
1
2
PC618
1U_0603_10V6K
PJ606
+2.5VSP
+2.5VSP
+2.5VS
@ JUMP_43X39
(0.38A,20mils ,Via NO.=1)
PR615 @
10K_1206_5%
2
@ JUMP_43X39
PC619
4.7U_0805_6.3V6K
PJ605
+3VS
Compal Secret Data
Issued Date
2011/10/12
Deciphered Date
2013/10/12
Title
Size
C
Date:

PWR +1.1VALWP/+1.2VSP/+2.5VSP
Document Number
Rev
0.1
LA9001P
Sheet
1
41
of
48
www.qdzbwx.com
PR614
10K_0402_1%
@
2
VGA_CORE_B+
<12,17,39,42>
B+
16
PC805
4.7U_0805_25V6-K
+VGA_COREP
EN
PC816
0.1U_0603_25V7K
2
BOOT2_2_VGA1
3
2
1
PR808
2.2_0603_5%
2
1
11
BOOT2_VGA
PC814
10U_0603_6.3V6M
2@
PC813
10U_0603_6.3V6M
PC812
10U_0603_6.3V6M
@ PC815
680P_0603_50V7K
PC810
330U_D2_2VM_R9M
PC811
330U_D2_2VM_R9M
UGATE2_VGA
12
PC809
330U_D2_2VM_R9M
13
1
@ PR806
4.7_1206_5%
2
PC808
1U_0603_10V6K
14
+5VALW
5
GND
MODE
17
3
2
1
18 PC807
1
LGATE2_VGA
2
10
VREF
1
93.1K_0402_1%
10K_0402_1%
PR811
VID1
BST
VID0
SW
V0
2
1
DRVH
TPS51518RUKR_QFN20_3X3
V1
1 1
PR810
DRVL
V2
1
VGA_PWRGD
<12,15>
15
+VGA_COREP
Iocp=32.5A
PC817
0.1U_0402_10V7K
PR809
6.04K_0402_1%
V3
+3VS
PR812
0_0402_5%
1
2
TRIP
V5IN
PGOOD
4
5
GSNS
21
PR807
10.7K_0402_1%
PL801
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
2
PQ802
TPCA8057-H 1N PPAK56-8
2
PR805
10.7K_0402_1%
21
100K_0402_1%
VSNS
PR803
41.2K_0402_1%
SLEW
20
21
PAD
PU801
PR804
2
4700P_0402_25V7K
19 1
2
PC801
PR801
0_0402_5%
1
2
10P_0402_25V8J
5
2
1
2
PQ801
TPCA8065-H_SOP-ADV8-5
10P_0402_25V8J
1
2
PC806
PC804
4.7U_0805_25V6-K
2
1
PC803
2200P_0402_50V7K
2
1
PC802
0.1U_0402_25V6
2
1
1
PR802
0_0402_5%
PJ801
2
JUMP_43X118
+VGA_COREP
PJ802
2
+VGA_COREP
Seymour
+VGA_CORE
@ JUMP_43X118
GPU_VID1
GPU_VID0
Core Voltage Level
0.9V
1.0V
1.1V
1.15V
PJ803
<16>
GPU_VID0
GPU_VID0
PR824
0_0402_5%
1
2
<16>
GPU_VID1
GPU_VID1
PR825
0_0402_5%
1
2
PR813
16K_0402_1%
2
@ JUMP_43X118
PXS_PWREN
PR814
@ 0_0402_5%
1
2
VRON_VGA
SUSP#
+1.5V_IO
<31,34,39,40,41>
+1.0VGS
3
PC819
1U_0402_6.3V6K
JUMP_43X79
@
+VGA_PCIEP
PJ804
JUMP_43X79
1
PC818
0.1U_0402_16V7K
PJ805
+5VALW
VOUT
PXS_PWREN
PXS_PWREN
PR816
40.2K_0402_1%
EN
FB
VIN
+VGA_PCIEP
3
2
9
APL5912-KAC-TRL_SO8
PR818
20K_0402_1%
PR817
1.15K_0402_1%
VGA_PCIE
1.0V
1.1 V
PR819
4.53K
3K
PC821
0.01U_0402_25V7K
PR819
4.53K_0402_1%
2
PC822
0.1U_0603_25V7K
2
1
<12,17,39,42>
PC823
22U_0603_6.3V6K
2
1
VOUT
PC820
4.7U_0805_6.3V6K
PR823
10K_0402_5%
1
2
GPU_VID1
VIN
PR821
10k_0402_5%
1
2
POK
PU802
7
+3VS
PD801
RB751V-40_SOD323-2
1
2
VCNTL
PR822
10K_0402_5%
1
2
GND
GPU_VID0
Compal Secret Data
Issued Date
2011/10/12
Deciphered Date
2013/10/12
Title
Size
Document Number
Rev
0.1
LA9001P
Date:

PWR-VGA_CORE/VGA_PCIE
D
Sheet
42
of
48
www.qdzbwx.com
@ PR820
10k_0402_5%
1
2
+3VS
PC901
PR901
330P_0402_50V7K 2K_0402_1%
2
1
2
1
PR906
PC903
PR907
0_0402_5% 1000P_0402_50V7K 301_0402_1%
2
1 <BOM Structure>
2
1
2
1
3
2
1
UGATE_NB1
1
+
32
LGATE_NB1
PQ902
3
2
1
PC918
0.22U_0603_25V7K
PC912
2200P_0402_50V7K
2
1
4.7_1206_5%
+APU_CORE_NB
+APU_CORE_NB
Iocp=39A
PR929
30
2
1
0_0402_5%
PR932
2
1
@ 0_0402_5%
PHASE1
25
UGATE1
PC920
26
LGATE1
+5VALW
+5VS
1U_0603_16V6K
27
PC919
2
1
28
PR931
2
1
1_0603_5%
29
TP
+3VS
CPU_B+
UGATE1
PC937
0.01U_0402_25V7K
PR958
2
1
0_0402_5%
PR959
2
1
0_0402_5%
PC925
2200P_0402_50V7K
2
1
PC924
0.01U_0402_25V7K
2
1
PC923
10U_0805_25V6K
2
1
LGATE1
PQ906
PC931
PR948
0.22U_0603_25V7K
2 2
1
BOOT1 1
2.2_0603_5%
PQ905
3
2
1
PR956
10_0402_5%
2
1
PL903
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PHASE1
PR950
PC932
137K_0402_1% 390P_0402_50V7K
2
1
2
1
PR953
PC933
2K_0402_1% 680P_0402_50V7K
2
1
2
1
@ PC936
820P_0402_50V7K
@ PR957
100_0402_1%
2
1
2
1
3
2
1
@ PR946
32.4K_0402_1%
2
1
3
2
1
PR949
1.62K_0402_1%
2
1
PC927
100P_0402_50V8J
2
1
PC930
330P_0402_50V7K
PC929
0.1U_0402_25V6
2
1
PC928
0.047U_0402_25V6
1
2
2
1
PR947
11K_0402_1%
PC935
0.1U_0603_25V7K
PR954
698_0402_1%
2
1
PC926
PR945
1000P_0402_25V6K301_0402_1%
2
1
2
1
PQ904
PR951
4.7_1206_5%
VSUM+
+APU_CORE
PR952
3.65K_0402_1%
2
1
PC934
680P_0603_50V7K
VSUM-
PR955
1_0402_1%
2
1
+APU_CORE
APU_VDD_SEN_H
<7>
APU_VDD_SEN_L
<7>
1
PR960
10_0402_5%
Compal Secret Data
Issued Date
2011/10/12
Deciphered Date
2013/10/12
Title
PWR-CPU_CORE/CPU_CORE_NB
Custom
Date:
www.qdzbwx.com
PH904
10K_0402_5%_ERTJ0ER103J
2
1 2
1
PR944
2.61K_0402_1%
VSUM+
PQ903
3
2
1
<31>
VGATE
1 2
BOOT1
ISEN2
PR940
100K_0402_5%
PR943
10K_0402_1%
31
1
PR941
0_0402_5%
VSUM-
PR917
1_0402_1%
1
VSUMN_NB 2
<BOM Structure>
PC922
10U_0805_25V6K
2
1
PC917
PR920
2
1 2
1
0_0603_5%
34
33
ISEN3
PR942
10.5K_0402_1%
PR921
3.65K_0402_1%
1
VSUMP_NB 2
680P_0603_50V7K
PR923
49
24
23
FB
BOOT1
UGATE1
PGOOD
PHASE1
NTC
COMP
IMON
BOOT_NB1
35
1U_0603_16V6K
38
39
40
37
UGATEX
PHASEX
LGATEX
42
43
44
45
41
PWM2_NB
FCCM_NB
PGOOD_NB
COMP_NB
FB_NB
47
46
VSEN_NB
ISUMN_NB
48
ISEN1_NB
LGATE1
22
PR939
0_0402_5%
2
1
PH903
470K_0402_5%_TSM0B474J4702RE
2
1
PWROK
21
PR938 27.4K_0402_1%
2
1
FCH_PWRGD
+5VS
PWM_Y
FB2
<12,31>
12
@ PR937 0_0402_5%
2
1
VDD
ENABLE
ISEN3
PC921
1000P_0402_25V6K
1
2
SVT
20
11
After rev1.1 must change to 133k
VDDP
RTN
APU_PWRGD
VDDIO
19
VR_ON
LGATE2
ISL6277HRTZ-T_TQFN48_6X6
VSEN
APU_SVT
SVD
18
<10,7>
0_0402_5%
<31>
PHASE2
ISUMN
UGATE2
VR_HOT_L
17
2@ PR961
SVC
ISUMP
<7>
+3VS
BOOT2
13
PR934
0_0402_5%
2
1
PR936
133K_0402_1%
1
2
+1.5VS
VIN
IMON_NB
36
PC916
PR919 0.22U_0603_25V7K
1
2 2
1
2.2_0603_5%
BOOT_NB1
CPU_B+
BOOTX
NTC_NB
ISEN1
@ PR927
100K_0402_5%
APU_SVD
3
0_0402_5%
1 SVC
4
0_0402_5%
1
5
0_0402_5%
1 SVD
6
0_0402_5%
1 VDDIO
7
0_0402_5%
1 SVT
8
0_0402_5%
1 ENABLE 9
0_0402_5%
1 PWROK 10
16
APU_SVC
<7>
PL902
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
APU_IMON
<7>
PR918
2
PR924
2
PR926
2
PR928
2
PR930
2
PR933
2
PR935
2
ISEN2_NB
ISUMP_NB
PR925
10.5K_0402_1%
<31>
ISEN2
+5VS
PH902
470K_0402_5%_TSM0B474J4702RE
2
1
<31,36,7> H_PROCHOT#
PR916
0_0402_5%
2
1
15
PC915
1000P_0402_25V6K
14
PU901
27.4K_0402_1%
1
PHASE_NB1
2
1
PC909
10U_0805_25V6K
2
1
UGATE_NB1
PHASE_NB1
PC910
0.01U_0402_25V7K
2
1
LGATE_NB1
After rev1.1 must change to 133k
PR922
PC908
10U_0805_25V6K
2
1
PQ901
FCCM_NB
PR910
649_0402_1%
2
1
PR914
2
1
10K_0402_1%
PR915
133K_0402_1%
CPU_B+
@ PR913
@ PC914
100_0402_1% 220P_0402_50V7K
2
1
2
1
PC913
0.1U_0603_25V7K
CPU_B+
PC907
0.1U_0402_25V6
2
1
PC906
0.047U_0402_25V6
1
2
VSUMN_NB
@ PC905
1000P_0402_50V7K
1
2
PR909
11K_0402_1%
PH901
10K_0402_5%_ERTJ0ER103J
2
1 2
1
PR908
2.61K_0402_1%
VSUMP_NB
PC904
100P_0402_50V8J
2
1
PC939
15U_D2_25VM_R90
PR905
10_0402_5%
2
1
+APU_CORE_NB
PL901
HCB4532KF-800T90_1812
1
2
B+
PC902
PR903
@ PR904
137K_0402_1% 390P_0402_50V7K 32.4K_0402_1%
2
1
2
1
2
1
PR902
2.87K_0402_1%
2
1
PC938
33U_D2_25VM_R60
APU_VDDNB_SEN_H
2
1
PR912
0_0402_5%
<7>
PC941
15U_D2_25VM_R90
PC940
33U_D2_25VM_R60
Rev
0.1
LA9001P
Sheet
1
43
of
48
2
1
PC1051
330U_D2_2VM_R9M
2
+
Issued Date
2011/10/12
2
PC1030
0.22U_0402_10V6K
PC1018
22U_0603_6.3V6K
2
1
PC1019
22U_0603_6.3V6K
2
1
PC1032
330U_D2_2VM_R9M
Deciphered Date
2013/10/12
Compal Secret Data
Title
Date:
Size
PC1026
180P_0402_50V8J
2
1
PC1025
180P_0402_50V8J
2
1
PC1024
180P_0402_50V8J
2
1
PC1023
0.22U_0402_10V4Z
2
1
PC1022
0.22U_0402_10V4Z
2
1
PC1021
22U_0603_6.3V6K
2
1
PC1020
10U_0603_6.3V6K
2
1
PC1017
22U_0603_6.3V6K
2
1
PC1016
22U_0603_6.3V6K
2
1
PC1008
22U_0603_6.3V6K
2
1
PC1007
22U_0603_6.3V6K
2
1
PC1006
22U_0603_6.3V6K
2
1
PC1014
22U_0603_6.3V6K
2
1
PC1015
22U_0603_6.3V6K
2
1
PC1005
22U_0603_6.3V6K
2
1
PC1004
22U_0603_6.3V6K
2
1
PC1012
22U_0603_6.3V6K
2
1
PC1013
22U_0603_6.3V6K
2
1
PC1003
22U_0603_6.3V6K
2
1
PC1011
22U_0603_6.3V6K
2
1
PC1031
330U_D2_2VM_R9M
PC1044
10U_0603_6.3V6K
2
1
PC1037
0.01U_0402_25V7K
PC1029
0.22U_0402_10V6K
PC1043
10U_0603_6.3V6K
2
1
PC1036
0.01U_0402_25V7K
1
PC1028
0.22U_0402_10V6K
PC1002
22U_0603_6.3V6K
2
1
PC1010
22U_0603_6.3V6K
2
1
PC1042
10U_0603_6.3V6K
2
1
PC1035
0.01U_0402_25V7K
PC1041
10U_0603_6.3V6K
2
1
PC1034
0.01U_0402_25V7K
1
PC1027
0.22U_0402_10V6K
+CPU_CORE
PC1040
10U_0603_6.3V6K
2
1
PC1039
22U_0603_6.3V6K
2
1
PC1038
10U_0603_6.3V6K
2
1
PC1048
180P_0402_50V8J
PC1047
180P_0402_50V8J
PC1046
180P_0402_50V8J
2
PC1033
0.01U_0402_25V7K
4
2
+APU_CORE
A
A
PWR - PROCESSOR DECOUPLING
Document Number
LA9001P
Sheet
44
of
48
Rev
0.1
www.qdzbwx.com
PC1052
330U_D2_2VM_R9M
PC1050
330U_D2_2VM_R9M
PC1045
180P_0402_50V8J
PC1001
22U_0603_6.3V6K
2
1
PC1049
330U_D2_2VM_R9M
PC1009
22U_0603_6.3V6K
2
1
5
1
+CPU_CORE_NB
+APU_CORE
D
+APU_CORE_NB
+1.2VS
Version change list (P.I.R. List)

Item
Page 1 of 1
for PWR
Reason for change
PG#
Modify List
Date
Phase
1
D
2
3
4
5
6
7
8
C
9
10
11
12
13
14
B
16
17
A
2011/10/12
Issued Date
Compal Secret Data
Deciphered Date
2013/10/12
Title
Custom
Date:
PIR (PWR)
Rev
0.1
LA9001P
Sheet
1
45
of
48
www.qdzbwx.com
15
VAUS5 HW PIR List
DATE
PAGE
3/22
26
SDV TO SIV
MODIFICATION LIST
PURPOSE
Change C1204, C1205 from SE071120JN0 to SE071120J80
SE071120JN0 is for A58 only
NOTE
3/22
27
Modify DL2 from @ to GAS@
For Gastube BOM control
3/22
12
Delete FCH_SEL BOM control
AMD formal announce FP2 only support A70M3
3/22
10
Delete U2 A60MR1 BOM control
3/22
12
Change R117 from PX@ to @, change R155 from @ to always mount
Clock request from GPU will not meet power sequence
3/22
12
Change R1606, R1607 from USBL2@ to @, change R1610, R1611 from USBL3@ to always mount
3/26
10
Change GPIO31 pull high from +3VALW to +3VS
This GPIO pin is Core power rail
4/2
07
Add R215 to pull high +1.5V_APU & @ R36
AMD suggest
4/6
24
Add C1223 1000p
For EMI
10 4/6
33
Add C1224 1000p
For EMI
11 4/6
26
Change C1204, C1205 from 12p to 15p
For Vendor tunning value
12 4/6
16
Change C341, C350 from 15p to 8.2p
For Vendor tunning value
13 4/6
33
Swap D45
For layout
14 4/9
31
Change R1564 from 33k to 18k
DVT Board ID
15 4/9
30
Swap JSPK1
For swap speaker cable
16 4/9
31
Add VSB_ON on GPIO127
For S5 power saving
17 4/11
29
Change R1527 to R-short
For cost down
18 4/11
31
Change R1580, R1586 to R-short
For cost down
19 4/11
13
For cost down
20 4/11
31
Change R1591 to always mount
For MainPowerON power control
21 4/11
For cost down
22 4/11
12
For cost down
23 4/11
17
For cost down
24 4/11
22
Mount R200, @ L171, C238, C239
For LVDS Translator 1.2 power rail
25 4/11
26
For cost down
26 4/11
27
Delete J17, J19
For LAN surge solution change
27 4/12
Change A6, A10 APU R1 PN
From PC sample to PR sample
28 4/13
17,19
Change BIF_VDDC to VGA_CORE and move C343 to Page 19
For PX5 only
29 4/16
27
Change CHASSIS2_GND to GND & CHASSIS1_GND
For common LAN surge solution
30 4/17
33
Mount L43, L44, L45, @ R1605, R1608, R1609, R1612, R1613, R1616
For EMI (USB3.0 choke)
31 4/17
32
Add L50, L51, L52
For EMI (USB2.0 choke from SB to MB)
32 4/17
30
Change R937, R1548 from 0 ohm to L172, L173 300ohm Bead
For EMI (DMIC DATA , CLK)
33 4/17
Change R26,R28 from 1k to 10k
For APU_SIC, SID 0'C shut down issue workaround
34 4/18
Change back R26,R28 from 10k to 1k, and mount C5988
For APU_SIC, SID 0'C shut down issue
@ R1614, R1615, R1619, R1624, R1625, R1626
Compal Secret Data
2012/01/15
Issued Date
Deciphered Date
2013/01/15
Title
Custom
Date:
HW-PIR
Rev
0.3
VAUS5 LA9001P M/B
Sheet
1
46
of
50
www.qdzbwx.com
NO
VAUS5 HW PIR List
NO
DATE
PAGE
5/11
2
3
SIV TO SIT
MODIFICATION LIST
PURPOSE
16
Change Q64 from SB00000EO10 to SB00000DH00
For BOM reduce
5/11
23
Reserve R1466
For factory requirement to prevent DISPOFF# damage
5/11
25
Add BOM structure SSD@ for SSD function
For BOM option
5/14
24
Reserve ESD component D1,D2 for HDMI signal
For HDMI hot-plug protection
5/21
7
13
25
26
30
0402 R-Shot modify

R24,R160,R161,R158,R163,R171,R169,R166,R1491,R1492
0603 R-Shot modify
R157,R164,R170,R172,R168,R159,R1529,L35,L36
0805 R-Shot modify
R162,R165,R1531
For BOM reduce
5/21
31
Change R1564 from 18K to 8.2K
For Board ID change
5/22
Change back R24 from R-shot to 0ohm
5/22
24
Reserve ESD component D69 for HDMI SMBus
For APU damage when HDMI hot-plug
NOTE
5/24
25
Reserve R1493
For Intel 2230 WLAN Card Support
10 5/24
20
Add VRAM Samsung 1G K4W2G1646E-BC11 strap setting
For customer request
11 5/24
24
Un-mount D1, D2
12 5/24
12
Change back R1610, R1611 footprint to 0ohm
13 5/25
30
Add C83, C84 for DMIC noise issue
For EMI request
14 5/25
27
Change DL2 PN to SCV00001D00
15 5/25
10
25
Add BT_OFF# for other BT combo card
16 5/29
26
Un-mount C1197. C1198 and mount C1200,C1203
For LAN power trace rounting
17 5/29
Change Q3,Q4 PN from SB501110010 to SB501380050
For PUR request
18 5/29
30
Change R1530 PN from SM01000DI00 to SM010005X00
For PUR request
19 5/31
23
25
32
33
Change C8244,C8245,C8246,C8247,C8248 and C8249 from 10p to 15p
For AMD suggest
2012/01/15
Issued Date
Compal Secret Data
Deciphered Date
2013/01/15
Title
Custom
Date:
HW-SIT PIR
Rev
0.3
VAUS5 LA9001P M/B
Sheet
1
47
of
50
www.qdzbwx.com
SYSTEM
D
VGA
B
www.qdzbwx.com
Compal Secret Data
Issued Date
2012/01/15
2013/01/15
Deciphered Date
Title

Power sequence
Rev
0.3
VAUS5 LA9001P M/B
Date:
Sheet
1
48
of
50
DESIGN CURRENT 0.1A
DESIGN CURRENT 6A
+3VLP
+EC_VCCA
+5VALW
DESIGN CURRENT 4.5A
+5VS
DESIGN CURRENT 1A
+3VALW
DESIGN CURRENT 1A
+3V_LAN
DESIGN CURRENT 1.9A
+1.8VGS
DESIGN CURRENT 1.2A
+1.1VALW
DESIGN CURRENT 4A
+1.1VS
DESIGN CURRENT 4A
+3VS
DESIGN CURRENT 0.1A
B+
SUSP
N-CHANNEL
DMN3030LSS-13
1
Jump
PXS_PWREN
SY8033BDBC
RT8205LZQW
SPOK
SY8809DFC
SUSP
N-CHANNEL
SUSP
DMN3030LSS-13
N-CHANNEL
DMN3030LSS-13
TL_ENVDD (LCD_ENVDD#)
DESIGN CURRENT 1.5A
+LCD_VDD
DESIGN CURRENT 0.1A
+3VGS
DESIGN CURRENT 0.75A
+2.5VS
DESIGN CURRENT 8.5A
+1.2VS
DESIGN CURRENT 60A
+APU_CORE
DESIGN CURRENT 44A
+APU_CORE_NB
Direct out Net Name
+1.5VP
Internal LDO
DESIGN CURRENT 1.3A
+0.75VS
RT8207MZQW
DESIGN CURRENT 3A
DESIGN CURRENT 3.2A
+1.5V
+1.5V_APU
For translate Net Name
+1.5V_IO
DESIGN CURRENT 1.2A
+1.5VS
DESIGN CURRENT 4.5A
+1.5VGS
DESIGN CURRENT 3A
+1.0VGS
Direct out Net Name
+1.5VP_DDR3L
Direct out Net Name
+0.75VSP_DDR3L
DESIGN CURRENT 19A
+VGA_CORE
P-CHANNEL
PMV65XP
PXS_PWREN
P-CHANNEL
AP2301GN-HF
LDO
APL5508-25DC
SUSP#
TPS51212DSCR
VR_ON
ISL6277HRTZ
SYSON
RT8207MZQW
3
Jump
SUSP
P-CHANNEL
PMV65XP
PXS_PWREN
N-CHANNEL
AO4430L
PXS_PWREN
SYSON
APL5912
RT8207MZQW
Internal LDO
PXS_PWREN
RT8207MZQW
TPS51518RUKR
Compal Secret Data
2011/12/30
Issued Date
2013/10/05
Deciphered Date
Title

Power Map
Custom
Date:
Rev
0.3
VAUS5 LA9001P M/B
Sheet
E
49
of
50
www.qdzbwx.com
Jump
VAUS5 Power on / off sequence (AC mode)

S5 - S0 -S5
+RTCBATT
+RTCBATT
+RTCBATT
5.74ms
+5/3VALW
+5/3VALW
+5/3VALW
39.90ms
SPOK
SPOK
SPOK
11.58ms
+1.1VALW
+1.1VALW
+1.1VALW
EC_ON
EC_ON
ON/OFF
ON/OFF
EC_ON
ON/OFF
10ms (EC)
9ms
RSMRST#
RSMRST#
120ms (EC)
RSMRST#
RTCCLK will be issued out from FCH after RSMRST# deasserted

25.4ms
RTCCLK
RTCCLK
RTCCLK
131ms
120ms (EC)
200ms
PBTN_OUT#
PBTN_OUT#
PBTN_OUT#
SLP_S5#
SLP_S5#
SLP_S3#
SLP_S3#
SLP_S5#
SLP_S3#
140ms (EC), PBTN_OUT# high edge issued out first, then mornitor SLP_S5# signal and count for 140ms to pull high SYSON
121ms
SYSON
203ms
SYSON
SYSON
686us
40ms
+1.5V
+1.5V
+1.5V
20ms (EC)
20ms
SUSP#
51ms
SUSP#
8.83ms
+0.75VS
SUSP#
344us
+0.75VS
+0.75VS
756us
1.2ms
+5VS
+5VS
+5VS
1.57ms
+3VS
4.8ms
+3VS
35.16ms
+2.5VS
2.756ms
+1.5VS
+3VS
1.25ms
+2.5VS
+2.5VS
3.08ms
+1.5VS
+1.5VS
4.580ms
+1.1VS
17.56ms
+1.1VS
38.4ms
+1.2VS
+1.1VS
14.85ms
+1.2VS
+1.2VS
210ms (EC)
299ms
+VR_ON
124ms
VR_ON
+VR_ON
6.06ms
85.8ms
+APU_CORE
+APU_CORE
+APU_CORE
6.06ms
123.8ms
+APU_CORE_NB
+APU_CORE_NB
+APU_CORE_NB
240ns
VGATE
VGATE
VGATE
10ms (EC)
6.76ms
FCH_POK (FCH_PWRGD)
5.28us
FCH_POK (FCH_PWRGD)
FCH_POK (FCH_PWRGD)
37.6ms
APU_CLK/
DISP_CLK
APU_CLK/
DISP_CLK
APU_CLK/
DISP_CLK
145.6ms
99.2ms
26.9ms
APU_PWRGD
(From FCH to APU)
APU_PWRGD
(From FCH to APU)
APU_PWRGD
(From FCH to APU)
10ms (EC)
20.79ms
KB_RST#
125.2ms
3
KB_RST#
KB_RST#
102ms
26.904ms
PLT_RST# (A_RST#)
PLT_RST# (A_RST#)
PLT_RST# (A_RST#)
2ms
26.904ms
APU_RST#
(From FCH to APU)
APU_RST#
(From FCH to APU)
APU_RST#
(From FCH to APU)
Issued Date
Compal Secret Data
2009/10/02
Deciphered Date
2010/10/02
A
www.qdzbwx.com
Title
S5_Power Sequence
Size
Date:
Document Number
Rev
0.3
Sheet
H
50
of
50

0e82b Compal LA-9001P

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A

VIUS5 LA-9001P M/B Schematics Document

Compal Electronics, Inc.

Compal Secret Data

VAUS5 LA9001P M/B

Thursday, May 31, 2012

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X 1

AMD FP2 APU

1.5V DDRIII 1333MT/s

Single Digital MIC

Audio Combo Jack

CMOS Camera page 23

USB(reserve for WiMAX)

Card Reader RTS 5178 (2in1)

USB PORT 2.0 x2(Right)

SATA2.0 HDD CONN

Compal Secret Data

Compal Electronics, Inc.

VAUS5 LA9001P M/B

USB Port Table

USB 2.0 USB 3.0

USB Port (Right Side 1)

USB Port (Left Side)

FCH SM Bus address

USB20 port0 port1

APU PCIE PORT LIST

FCH PCIE PORT LIST

CMOS Camera part

Compal Electronics, Inc.

Compal Secret Data

BOM Structure Table

Board ID / SKU ID Table for AD channel

VAUS5 LA9001P M/B

Tuesday, May 29, 2012

SMBUS Control Table

Without BACO option :

PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation

"Thames" has the following requirements with regards to power-supply sequencing

dGPU Power Pins

BACO Mode Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and

BIF_VDDC (current consumption = 55mA@1.0V, in

Global ASIC Reset

Compal Secret Data

Short PX_MODE and PX_PWREN

Compal Electronics, Inc.

VAUS5 LA9001P M/B

Friday, May 25, 2012

Compensation Resistor to VDDP

Compensation Resistor to VSS

Power Sequence of APU

A6 SERIES ZM212169E2451 2.1G BGA813

A10 SERIES ZM202268E4451 2G BGA813P

A4 SERIES AM4355SHE23HJ 1.9G BGA813

A6 SERIES AM4455SHE24HJ 2.1G BGA813 A10 SERIES AM4655SIE44HJ 2G BGA813P

Compal Electronics, Inc.

Compal Secret Data

VAUS5 LA9001P M/B

Tuesday, May 29, 2012

Place them close to APU within 1"

0.75V reference voltage