1.

SRAM ARCHITECTURE
SRAM stands for static random access memory here the static indicates that in the memory
data remains stored as long as the power is applied this means that there is no need

for continuously refreshing the memory cells.

The complete block diagram of the SRAM is as shown in Figure 1.

Figure 1 BLOCK DIAGRAM OF SRAM ARCHITECTURE

1.1

ROW AND COLUMN DECODER:

These two blocks are used to decode the address given and select specific word in the
memory array (set of bit cells). The memory system uses a n bit address system which is
split into two sets and given to the row and column decoders here the address is split into
two units so as to obtain a two dimensional system which will reduce the time response
and also area of the system. The row decoder output is connected to the word lines of
the memory array and the column decoder output connects to the bit lines of the memory
array through a pass transistor system which is a form of a mux these two decoders
together form the address selection unit for the memory.
1.2.INPUT AND OUTPUT DATA CONTROL: The input and output data control units are
concerned with the arrival of data into and out of the different blocks of the memory

system. Like the decoder needs to be pre charged only after the address changes and
sense amplifiers have to be activated after the data arrives on the bit lines, etc. These
aspects are taken care of by the data control blocks
1.3.SENSE AMPLIFIERS: This part of the memory system is the costliest part and this
part is the one concerned with the detection of the data stored in the memory array. The
sense amplifiers detect whether the data stored is a logic 1 or a logic 0. This it does by
checking the which bit line discharges .
The major aspect of consideration at the architectural level is the arrangement
of memory cells in the form of array.

2.BIT CELL:
2.1. BIT CELL WORKING:
The bit cell of a SRAM can be implemented using six transistors as shown in the
figure 2.1. It can also be implemented using four transistors and load resistors in place of
transistors M2 and M4 in the figure. These type of RAM cells reduce the cell size
significantly but the problems associated with these type of ram cells is that in order to
attain acceptable noise margins and output pull up times of the resistive load inverter low
values of resistance are needed where as on the other hand a large value of resistance is
needed to reduce the amount of standby current drawn by the cells. Thus, there is a trade
off between the power consumption and high speed along with noise margins. So the most
used circuit is the 6 transistor cross coupled inverter cell as shown below

FIGURE 2.1 6T SRAM BIT CELL

Here the memory cell, which consists of a latch made of cross coupled inverters, stores the
data as long as the power is applied and the word line drives the transistors M5 and M6
(complementary access transistors) on which in turn connect the inverter O/Ps to the bit lines
there by putting the data on the bit lines during the read cycles and during the write operations.
The main advantage of these cells is low static power dissipation. Here the power dissipation
is limited to only to the leakage currents of the PMOS transistors. Thus the memory cell draws
power only during a switching transition.

2.2.CELL DESIGN: To design the W/L ratio of the SRAM cell a number of criteria are to be
taken care of. The two basic requirements are
1.The data read operation should not destroy the stored information in SRAM cell.
2. The data write operation should allow the stored information to be modified.

2.2.1 CMOS SRAM-Read Operation

Assume that 1 is stored at Q. We further assume that both bit lines are precharged to 2.5 V before the
read operation is initiated. The read cycle is started by asserting the word line, enabling both pass
transistors M5 and M6 after the initial word-lone delay. During a correct read operation, the values
stored in Q and Q bar are transferred to the bit lines by leaving BL at its precharged value and by
discharging BL through M1-M5. A careful sizing of the transistors is necessary to avoid accidentally
writing a 1 into the cell. This type of function is frequently called a read upset. This is illustrated in

Figure 2.2. Consider the BL side of the cell. The bit line capacitance for larger memories is in the pF
range. Consequently, the value of BL stays at the precharged value Vdd upon enabling of the read
operation (WL1).This series Combination of two NMOS transistors pulls down the BL towards
ground. For a small-sized cell, we would like to have these transistor sized as close to minimum as
possible, which would result in a very slow discharge of the large bit line capacitance. As the difference
between BL and BL builds up, the sense amplifier is activated to accelerate the reading process.

Figure 2.3 Simplified model of CMOS SRAM cell during read (Q=1, V precharge=Vdd).

Initially, upon the rise of the WL, the intermediate node between these two NMOS transistors, Q is
pulled up toward the precharged value of BL. This voltage rise of Q must stay low enough not to
cause a substantial current through the M3-M4 inverter, which in the worst case could flip the cell. It is
necessary to keep the resistance of transistor M5 larger than that of M1 to prevent this from happening.
The boundary constraints on the device sizes can be derived by solving the current equation at the
maximum allowed value of the voltage ripple V. We ignore the body effect on transistor M5 for
simplicity and write
kn,M5(( VDDV VTn)VDSATn V2DSATn/2)=kn,M5(( VDDVTn) V V2/2)
This simplifies to

Where CR is called the cell ratio and is defined as

The value of voltage rise V as a function of CR is plotted in Fig 3.4. To keep the node voltage from
rising above the transistor threshold (of about 0.4V), the cell ratio must be greater than 1.2.For large
memory arrays; it is desirable to keep the cell size minimal while maintaining read stability. If the
transistor M1 is minimum sized, the access pass transistor M5 has to be made weaker by increasing its
length. This is undesirable, because it adds to the load of the bit line. A preferred solution is to minimize
the size of the pass transistor, and increase the width of the NMOS pull-down M5 to meet the stability
constraint. Beyond adjusting the size of the cell transistors, the erroneous toggling can be prevented by
pre charging the bit lines to another value, such as Vdd/2. This effectively makes it impossible for Q to
reach switching threshold of the connecting inverter. Pre charging to the midpoint of the voltage range
has some performance benefits as well, since it limits the voltage swing on the bit lines.

Figure Voltage rise inside the cell upon read versus cell ratio (ratio of M1/M5)

2.2.2 CMOS SRAM Write Operation

In this example, we derive the device constraints necessary to ensure a correct write operation.

Assume that a 1 is stored in the cell (or Q = 1). A 0 is written in the cell by setting BL to 1 and BL
to 0, which is identical to applying a reset pulse to an SR latch. This causes the flip-flip to change
state if the devices are sized properly. During the initiation of a write, the schematic of the SRAM
cell can be simplified to the model of Figure 3.4. It is reasonable to assume that the gates of
transistors M1 and M4 stay at Vdd and GND, respectively, as long as the switching has not
commenced. While this Condition is violated once the flip-flop starts toggling.
Note that Q side of the cell cannot be pulled high enough to ensure the writing of 1.
The sizing constraint, imposed by the read stability, ensures that this voltage is kept below 0.4
Therefore; the new value of the cell has to be written through transistor M6. A reliable writing of
the cell is ensured if we can pull node Q low enough this is, below the threshold value of the
transistor M1. The conditions for this to occur can be derived by writing out the dc current
equations at the desired threshold point, as follows:
kn,M6(( VDD VTn)VQ V2Q/2)=kn,M4(( VDD |VTp| ) VDSATp V2DSATn/2)

Figure Simplified model of CMOS SRAM cell during write (Q=1)

Solving for Vq leads to

Where the pull up ratio of the cell, PR is defined as the size ratio between the PMOS pull up and the
NMOS pass transistor:

The dependence of Vq on PR for is plotted in Figure. The lower PR, the lower the value of Vq. If
we wish to pull the node below Vth, the pull up ratio has to be below 1.8.
This constraint is met, by a large margin, when using minimum-sized devices for both the PMOS
pull-up M4 and NMOS access transistor M6. Our initial assumption was that the transistors M1 and M2
do not participate in the writing process. This is not completely true in practice. As soon as one side of
the cell starts switching, the other side eventually follows, engaging the positive feedback.

Voltage written into the cell versus pull-up ratio (size ratio between the PMOS pull-up and access
transistor)

5.6. CALCULATED W/L RATIOS : During read operation, The equations can be re written
as

During the write cycle

Using the Above equations We arrive at a ratio of1:1:3 where in the ratios are in the order
of PMOS: Access Transistor: Pull down NMOS.

3. CONTROL BLOCK DESIGN FOR ASYNCHRONOUS MEMORY:

Now considering the design of control block for memory of type asynchronous of size
8x8. As we cited before, there is no clock signal for the memory chip. We have following
input signals to the chip.
Signals

Meaning

W/R_bar

Read /Write enable

Addresses

A0 A7
TABLE 3.1.
CONTROL
SIGNALS

Using these signals we have to start and end a memory operation.

Sense amplifier enable: This signal should be activated whenever the read operation is
there that too after the bit line has been pre charged so for this purpose the bit line
pre charge signal and the W/R_bar signal is ANDed and the output obtained is the
Sense Amplifier Enable (SE).
Write enable: When W/R_bar signal goes high, we can use as WRITE ENABLE signal
directly.

Read enable : When R/W signal goes low the inverted W/R_bar will give the Read
enable.
Bit line pre charge: This signal has to be asserted when we have read or write , before the
word line asserted.

Figure 3.1 Control logic for 8x8 SRAM

4.PRECHARGE CIRCUIT:

The pre charge circuit is one of the essential component used in SRAM. The function of SRAM is
to charge the bit and bitbar lines to Vdd=1.8v.The pre charge circuit enables the bit lines to be
charged high at all times except during read and write operation. The width required for PMOS is
minimum i.e 240n and length is fixed to 180nm. For each column single pre charge circuit is used.
Here the Bitlines will begin to be charged by the MP1 and MP2 as soon as the pre signal is
enabled and the task of the central pmos is to balance the charge on the bitlines when the pre
signal is enabled so if by a process mismatch one line gets charged more than the other then the
central pmos balances it.

Figure.4.1.Pre Charge circuit

5. SENSE AMPLIFIER CIRCUIT :
Basically the sense amplifiers are used to speed up the memory read cycle and to reduce the
power consumption in the memory which can be increased due to the complete discharge on the bit
and bit' lines and the need to recharge them completely during the next cycle. Since for this project
speed as power weren't much of a concern and also as the memory size is relatively small the bit
line cap is also pretty small. Hence even these factors will be much less significant. Thus the Sense
amplifier we are using here is a tristate inverter controlled by the SE signal.

Figure 5.1 Sense amplifier circuit

6.Write Driver Circuit

The function of the SRAM write driver is to quickly discharge one of the bit lines from the
precharge level to below the write margin of the SRAM cell. Normally, the write driver is enabled
by the Write Enable (WE) signal and drives the bit line using full-swing discharge from the
precharge level to ground.
When write enable goes to high, and thenPM6&NM3 gets ON, which makes a way into bit or bit
bar line for data.
Hence when write enable = 1; write operation.

Figure 6.1 Write driver circuit

7. 3x8 Decoder
A row decoder is used to decode the given input address and select the wordline.
When performing a write or, read operation only one of the row is selected and 8 bits of
data is transmitted. There are 8 rows and row contained 8 cells each. The row decoder
selects one of those rows, depending on the 3 bit address given to it. In order to design
an 8X8 SRAM a 3x8 decoder is used. Number of wordline equals to the number of rows
in the SRAM cell array.
The decoder selects 1 of 8 wordlines, with respect to the input address. The output
of the decoder is fed to a 2-input AND. This AND is the wordline driver. This AND

supports a large capacitance on the wordline. Each cell loads the wordline with two
transistors. Therefore, in the design there would be 16 transistors per wordline forming a
large capacitance on the wordline. Other input to this AND is the Clock. Only when
both Clock and decoder output signals are enabled, the AND enables a wordline to the
rows of SRAM cell arrays. In a typical SRAM design, the output from the decoder
would directly enable the wordline. This AND was introduced in the design to achieve a
clock enabled design.
A NAND based decoder is used in the design. NAND based design is suitable as
it faster. Table 2 shows the truth-table of a 3x8 decoder. Three input addresses to the
decoder are represented by ABC inputs, where A is the most significant bit. As you see,
each combination of ABC inputs only activates one output out of A0 A7.

Figure 7.1

Figure 7.2

Address Inputs
A2(MSB) A1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

A0(LSB)
0
1
0
1
0
1
0
1

OUT0
1
0
0
0
0
0
0
0

OUT1
0
1
0
0
0
0
0
0

OUT2
0
0
1
0
0
0
0
0

OUT3
0
0
0
1
0
0
0
0

OUT4
0
0
0
0
1
0
0
0

OUT5
0
0
0
0
0
1
0
0

OUT6
0
0
0
0
0
0
1
0

Table 7.1

Figure 19 presents the 3x8 decoder gate level design. The decoder was designed
to satisfy the outputs as presented in Table 2. The inputs to the decoder are A, B and C.
An inverter is placed before the NAND gates so that all 8 combinations could be formed
(A, B, C, and there inverses, A', B' and C').

OUT7
0
0
0
0
0
0
0
1

1 BIT COMPLETE SRAM CELL

Combining the circuits namely, SRAM cell, precharge, write drive and
sense amplifiers, one write and read cell is obtained. The complete schematic of one write
and read cell is shown in figure. This schematic shows all the different peripheral
circuits combined with the static RAM cell, forms a complete working SRAM write and
read cell. As shown in the block diagram schematic in figure 13, the input signals are
write _enable that allows writing of data to the cell, sense that allows reading of data
from the cell, word_enable that decides to/from which address data will be written or
read from and the signal data is the one bit data either high or low that is to be stored to
or read from the cell. The two output signals are readout corresponding to the data signal
and readoutbar is the inverse of readout. Figure 14 shows the transistor level design of
one write and read cell.

Simulation Result:
8. 8x8 SRAM

Simulation result for 8x8 SRAM