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International Journal of Electrical and

Electronics Engineering Research (IJEEER)


ISSN(P): 2250-155X; ISSN(E): 2278-943X
Vol. 6, Issue 4, Aug 2016, 29-34
TJPRC Pvt. Ltd

DESIGN AND IMPLEMENTATION OF AREA EFFICIENT AND LOE


POWER SHIFT REGISTER USING PULSED LATCH
S. S. KHOT & PEDGAONKAR SNEHAL
Siddhant College of Engineering, Sudumbare, Pune, Maharashtra, India
ABSTRACT
This paper introduced a design and implementation of shift register using pulsed latches and flip-fliops. As
flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock switching
activity and then increases time latency. Flip-flops also engages fifty percent power out of total circuit power in clocking.
To reduce such power consomptions and to achieve area optimisation flip-flops are replaced by pulsed latches.
The design is impemented with 250nm technology in Tanner EDA Tool. With Vdd=1.8V, Freq=100MHz. Avereage
power of total circuit is 0.465uW and delay of 0.312 us.
KEYWORDS: Flip-Flops, Area Efficient, Pulsed Clocks, Pulsed Latches, Shift Register, Tanner

1. INTRODUCTION
The rapid growth in semiconductor devices and VLSI designs has led to the development of high
performance designs with enhanced reliability, customized size and low power, and because of the power
dissipiation is critical issue for battery operated systems. Therefore the designs are needed to be consume less

Original Article

Received: Jun 06, 2016; Accepted: Jun 28, 2016; Published: Jul 05, 2016; Paper Id.: IJEEERAUG20163

power while maintaining comparable performance. So everyone in VLSI design must think about area utilization
and power dissipation
In low power digital design, mainly shift registers are designed using flip-flops of diffrent types. To
achieve area optimization and power consumption different techniques are introduced like use of double edge
triggered flip-flip, single feed through scheme based flip-flop, use of multiple voltage supply, clock gating, voltage
scaling etc. As it is a type of synchronous circuit all the flip-flops are clocked simultaneously. The flip-flop is
basic data storage element.
The operation of flip-flop is depend on clock frequency, which consumes 50% power out of total power
in a digital design. At present, by decreasing CMOS technology process stated by Moore's law, more transistors
can be integrated on the same die [1]. Applying more transistors is accompanied by more switching that brings out
more energy dissipation in the form of heat and radiation [2].
The heat and consistency of integrated circuits are addressed as important drivers of low power design
procedures in RFID applications [3-7]. The packaging and cooling cannot remove additional heat, so the matter of
heat is significant issue in the era [8]. FFs are addressed as fundamental storage element which is vastly finds
application in all types of digital design [9].

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S. S. Khot & Pedgaonkar Snehal

Flip-Flop based shift registers are used in digital filters [10], image processing [11]. As the size of image data
goes on increasing continuously, the demand of word size of shift registers also goes on increasing to process large image
extraction 4K-bit [12].
The Shift registers are formed by cascade connection of flip-flops, sharing the same clock as it is a type of
sequential circuit. That means the output of first flip-flop is given as the Data input of next flip-flop due to which shifting
takes place. The speed of flip-flop is less important than area and power consumption because there is no any circuit
between flip-flops in shift register. To reduce power and area smallest flip-flop is selected. Recently pulsed latches have
been replaced the flip-flops in many applications, because latches are smaller than flip-flops.
This paper proposes a design implementation of shift register using non overlapped pulsed latches, to achieve low
power and area optimization. Latches cannot be used in shift register design because of timing problem.
The reminder of this paper is organized as follows. Section II presents problem statement. Section III presents
Proposed Shift register. Section IV presents SSASPL working. Section V presents simulation designs. Section VI presents
Conclusion. Section VII presents Experimental results.

II. PROBLEM STATEMENT


The main challenges for designing low power area efficient shift registers using latches is to optimize power &
reduce the area without affecting the response or timing problem.

Solving Timing Problem: The pulsed latch can not be used in shift registers due to their timing problem.
The output signal of first latch changes correctly because input signal of first latch is constant during the clock
pulse width TPulse. But the second latch Q2 has uncertain output signal because input from Q1 changes during
clock pulse width. So to avoid this timing problem a delay circuit is introduced. As a result, all latches have
constant input signals during the clock pulse width and no timing problem occurs between the latches.

Reduced Area: Area required for Shift register using flip-flops is twice than that of shift registers using latches
because a flip-flop consists of two latches. Thus area is reduced by 50% by replacing flip-flops with latches.

Reduced Power: Flip-flop consumes near about 50% of total power because in sequential circuit. By replacing
flip-flops with latches in proposed shift register, the power is saved by using clock pulsed instead of clock signal.
Because of all these reasons, static differential sense amplifier shared pulsed latch is an attractive choice for
efficient design of shift register.

III. PROPOSED SHIFT REGISTER


The proposed design is about shift register using pulsed latches instead of conventional flip-flops. It optimizes
power & area as compared to conventional flip-flops. The design is discussed using Static Differential Sense Amplifier
Shared Pulse Latch (SSASPL) & Power PC/Style Flip-flop (PPCFF) building blocks. 64 bit shift register using SSASPL is
implemented. Here the timing problem of latch is overcome by using non overlapping clock pulse signals. Another design
of 64 bit shift register using PPCFF is also implemented. The SSASPL design is compared with PPCFF in reference to
Area, Power & Delay.

Impact Factor (JCC): 6.1843

NAAS Rating: 2.40

Design and Implementation of Area Efficient and


LOE Power Shift Register using Pulsed Latch

31

Both the designs are realized using Tanner EDA tool (14.1 version) & approximate results of area & power are
calculated.

.
Figure 1: Proposed Shift Register

IV. SSASPL WORKING


The above diagram is n-bit shift register using SSASPL. The actual design is with 9 transistors & here it is
modified to 7 transistors by removing inverter to generate a complimentary data input Db from D. From differential output
data Q & Qb of previous latch, differential data inputs D & Db are generated. Here 7 transistors consume lowest clock
power as single transistor is driven by pulsed clock signals. Out of 7 transistors first 3 NMOS (M1-M3) updates data & two
invertors holds data. The data is updated when pulsed clock signal is high.
Software Design
Tanner EDA consists of 5 tools, namely S-Edit, T-Spice, W-Edit, L-Edit & LVS. The S-Edit is used to draw
schematic of proposed design. T-Spice gives simulation results of the respective design while W-Edit provides waveforms
of the circuit. L-edit is used to design the layout & LVS provides Layout Vs Schematic results.
Implementation of Shift Register using SSASPL & PPCFF
The design is achieved by two methods.
I: SSASPL consists of 7 transistors out of which 3 NMOS updates the data & 2 invertors holds the data. Out of
these 7 transistors, the clock pulse is applied to only one transistor.
II: PPCFF consists of 16 transistors out of which 8 transistors are allotted for clock signal & remaining are used
for flip-flop.
Total word length of both the designs is 64 bit & word length of sub-shift register is 8 & 4 respectively. The word
length of sub-shift register is decided by considering area, speed & power. Area is reduced according to word length (K) &
power increases as word length of sub-shift register reduces.
Figure 2 shows schematic of 64 bit shift register with 4 bit sub-shift register word length using SSASPL. 250nm
CMOS technology is used for the design of the shift register.

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S. S. Khot & Pedgaonkar Snehal

Figure 2: Schematic Design of Shift Register by SSASPL

Figure 3: Simulation Results of SSASPL is as Shown Above

Figure 4: Schematic Design of Shift Register by PPCFF


Impact Factor (JCC): 6.1843

NAAS Rating: 2.40

Design and Implementation of Area Efficient and


LOE Power Shift Register using Pulsed Latch

33

Figure 5: Simulation Results of PPCFF is as Shown Above

CONCLUSIONS
This paper proposed a review of different methodologies for designing a shift register. Clock signal is major
component in power consumption which is being handled using various techniques like clock gating, usage of double edge
triggered flip-flops, clock tree migration & using many supply voltages, pulsed latches etc. The main aim while doing this
survey is low power and minimum area as it is of first priority according to CMOS technology. The low power and area
efficient shift register of 64 bit is designed, with Vdd=1.8V Another design of PPCFF shift register of 64bit is also
implemented using Tanner EDA tool with 250nm technology. The SSASPL design saves 50% area 30% power than
PPCFF design.

EXPERIMENTAL RESULTS
Comparison of two design methods shows that the average area of PPCFF is reduced by approximately 50% in
SSASPL & power is reduced by 33%. For Vdd= 1.8V and Fmax= 100MHz with delay of 0.312 us (SSASPL) and 0.790 us
(PPCFF). Avereage power of SSASPL is 46.52 uW and for PPCFF design it is 66.23 mW.

ACKNOWLEDGEMENTS
We acknowledge the hard work and efforts by the experts who have contributed towards advancement of the
design of Shift Registers. We also grant the efforts of Principal Dr. S. S. Khot, HoD, SCOE, Pune and for their constant
support, modifications and suggestions to improve the quality of the paper and to help prepare the camera-ready copy of
our paper.
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Impact Factor (JCC): 6.1843

NAAS Rating: 2.40

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