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Quiz Questions: NPTEL
Microprocessor and Microcontrollers
Q1. A Workstation is a powerful, single-user computer. T/F
Q2. IBM's AS/400e is an example of ________ computer.
Q3. Bandwidth refers to number of bits processed in a single instruction. T/F
Q4. __________ determines how many instructions per second the processor can execute.
Q5. RISC means _________________.
Q6.MPP stands for__________________.
Q7. Microprocessor has CPU, RAM, ROM, I/O ports and timers in a single chip. T/F
Q8. Microcontroller has CPU, RAM, ROM, I/O ports and timers in a single chip. T/F
Q9. Identify the odd one: PCI, ISA, DMA, and SCSI
Q10.____________ is a single chip computer.
Q11.______________ processor is specifically designed for digital signal processing.
Q12.In _________ architecture, there is separate program and data memory.
Q13. SIMD stands for _______________.
Q14. Von Neumann architecture has ____________and ____________ memory is same.
Q15.8085 is a ______bit microprocessor.
Q16.The size of a PC in 8085 is _______.
Q17.Name the DMA pins in 8085.
Q18.8085 has ________number of address lines.
Q19.The pin used in de multiplexing in 8085 is_____________.
Q20. The size of flag register in 8085 is ___________.

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Q21. The number of flags in 8085 is ___________.

Q22. AC flag stands for____________.
Q23. All jump/branch instructions in 8085 use ____________addressing.
Q24.Stack grows downwards in 8085. T/F
Q25. Name the maskable 8080A compatible interrupt in 8085.
Q26. CALL is a ________byte instruction in 8085.
Q27. TRAP is a___________type of interrupt in 8085.
Q28. Name the pair of registers in 8085.
Q29. Immediate addressing mode is not supported in 8085. T/F
Q30. 8086 microprocessor has ______ address pins and ________ data pins.
Q31. The pin that is used in 8086 to configure minimum and maximum mode is _________.
Q32.The interrupt pins in 8086 are ________ and ____________.
Q33. The size of the pre fetch queue in 8086 is __________.
Q34. The registers used in pointing to an instruction in 8086 are _________ and _________.
Q35. The index register DI is associated with ________ segment and SI is associated with
________________segment.
Q36. The architecture of 8086 is divided into _________ unit and ___________.
Q37. The BIU in 8086 uses a mechanism known as an instruction stream queue to implement a
_________architecture.
Q38. During the execution of the instruction, the ________tests the status and control flags and
updates them based on the results of executing the instruction.
Q39. 8086 is a ________pin IC.
Q40.During I/O or memory read or write operations, in which T state, the address is available on
the address bus.
Q41. The values S4=0; S3=1 means which segment?

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Q42. The ____ signal is used to indicate the transfer of data over the higher order ( D15-D8 )
data bus.
____
Q43. TEST pin is examined by which instruction?
Q44. Identify the minimum and maximum mode pins:
__ __
HOLD, RQ/GT, HLDA, QS0
Q45.________pin distinguishes the memory and I/O operations in 8086.
Q46. ________signal is used to insert wait states into the bus cycle such that it is extended by a
number of clock periods.
Q47. The _________input is used to provide a hardware reset for the 8086.
Q48.__, __, __ are input to the external bus controller device, so that the bus controller generates
the appropriately timed command and control signals in 8086.
Q49.Most of the registers in 8086 is of size ______ bits.
Q50.Which register is used as a count register in 8086?
Q51. The string processing is controlled by _____flag.
Q52._______ flag is used in single-step execution.
Q53. In MUL BX instruction, which is the implied operand?
Q54. The segments in 8086 can have maximum ______size.
Q55. The overlapping of segments in 8086 is possible. T/F
Q56. The total number of segments with 64KB size possible in 8086 is ________.
Q57. Short Jump in 8086 refers to jump within a _________.
Q58. Long Jump in 8086 refers to jump within _____ memory. (size)
Q59. Each interrupt vector is a ___-bit pointer in format segment: offset.
Q60. STI instruction enables the interrupt. T/F
Q61. ____ instruction disables the interrupt.
Q62.Total number of interrupt types available in 8086 is ______.
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Q63.Example of a processor exception in 8086 is ________.

Q64.8085 can address up to _____memory.
Q65.8086 can address up to ____ memory.
Q66. ____ instruction in 8086 converts the result of the addition of two valid unpacked BCD
digits to a valid 2-digit BCD number and takes the AL register as its implicit operand.
Q67. _______ instruction in 8086 converts unpacked BCD digits in the AH and AL register into
a single binary number in the AX register in preparation for a division operation.
Q68._______ instruction in 8086 converts the result of the multiplication of two valid unpacked
BCD digits into a valid 2-digit unpacked BCD number and takes AX as an implicit
operand.
Q69. _______ instruction in 8086 converts the result of the subtraction of two valid unpacked
BCD digits to a single valid BCD number and takes the AL register as an implicit operand.
Q70.In this instruction ADD AL, 74H; identify the addressing mode of the source operand.
Q71.Name the logical instruction used for masking of bits in a data.
Q72.______ instruction in 8086 is equivalent to divide by 2.
Q73. SHL instruction in 8086 is equivalent to _________.
Q74. Which category of instructions does not affect the flags?
Q75. CBW Instruction stands for _______________.
Q76. Name the instructions used for setting and clearing the CARRY flag.
Q77. Shift and Rotate instructions are one and the same. T/F
Q78. Name the assembler directive used to declare an array of N bytes.
Q79. Identify the odd one: END, ENDP, EXIT, ENDM, ENDS
Q80.Name the assembler directive which helps in Aligning on Even Memory Address.
Q81.Name the assembler directive which is used to give a name to some value or to a symbol.

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Q82.Identify the instruction that does not affect the location counter:
a. X DB 5
b. ORG 100
c. END
d. ADD AL,BL
Q83. Identify the assembler directive in the following instruction:
INC BYTE PTR [BX]
Q84.INT ___ H is a DOS interrupt.
Q85. The DOS function calls are given in ____ register.
Q86.EEPROM is a ________ memory.
Q87.SRAM stands for ___________.
Q88.DRAM needs memory refresh. T/F
Q89. For addressing the 4K bytes of memory, ___ address lines are required.
Q90. The Refresh cycle is different from the memory read cycle. T/F
Q91.A typical 4K bit dynamic RAM chip has an internally arranged bit array of dimension
a. 64 * 64 b. 12*12 c. 32*32 d.8*8
Q92. Name the strobe pins in DRAM.
Q93. Which port of 8255 is used in handshaking?
Q94. Port A of 8255 has an 8 bit ______and 8 bit _____ latch.
Q95. Name the modes in which port A of 8255 can be operated.
Q96. Name the mode in which bidirectional data transfer is allowed.
Q97. Name the two basic modes of operations of 8255.
Q98. The size of the data bus in 8255 is _____.
Q99. IBF signal stands for ____.
Q100. _______ pin is used in 8255 to latch the input data.
Q101. 8254 supports _______ number of Programmable Counter Modes.

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Q102. The size of the counters in 8254 is ____.

Q103. The counters in 8254 can handle clocks up to ____.
Q104. With the help of 8254, motor controller can be developed. T/F
Q105. The Control Word Register and the three Counters have separate addresses and selected
by the ___, __ inputs in 8254.
Q106. The counters in 8254 can count in _____ or _____ .
Q107. Name the mode in 8254: Interrupt on Terminal count.
Q108.The Mode 2 of 8254 acts as __________.
Q109. Match the following:
a. Hardware triggered strobe

i. Mode 3

b. Software triggered strobe

ii. Mode 5

c. Square wave mode

iii. Mode 4

Q110. What is the meaning of the keyboard debounce unit debouncing the key entry.
Q111.With the use of 8255, the interfacing keyboard and display with 8086 is that the processor
has to refresh the display and check the status of the keyboard periodically using
______technique.
Q112. Name the Intels general purpose keyboard display controller.
Q113. What is the size of the FIFO/Sensor RAM in 8279?
Q114. What is the use of scan lines in 8279?
Q115.________ pin is used to blank the display.
Q116. ____________ bits are used to mask the individual nibble in 8279.
Q117. ISR in 8259 stands for ________.
Q118. ___________ register stores the bits required to mask the interrupt inputs in 8259.
Q119. To connect more devices to the interrupt line of the microprocessor, the 8259 chips can be
cascaded. T/F

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Q120. 8259 supports ________ devices for interruption.

Q121. AEOI means _________.
Q122. OCW and ICW are one and the same in 8259. T/F
Q123. Name the default mode of 8259.
Q124. What is the priority of the IR0 and IR7 in the fully nested mode in 8259?
Q125. Name the commonly available types of LCD.
Q126. Name the signals used with ADC conversion.
Q127. The Coprocessor 8087 is compatible with ____ and ____ microprocessors.
Q128. The size of the status register in 8087 is ___.
Q129. The DE bit in the status register of 8087 indicates _______.
Q130. Which instruction is used to load the value into the control register in 8087?
Q131. The PC bit in control register of 8087 indicates ________.
Q132. The RC = 10 bit value in 8087 means ___________.
Q133. NUE in 8087 stands for ____________.
Q134. The different exception conditions detected by 8087 during instruction execution are
a. INVALID OPERATION
b. OVERFLOW
c. ZERO DIVISOR
d. All of the above
Q135. The data types supported by 8087 are
a. Integer Data Type
b. Packed BCD
c. Real data type
d. All of the above
Q136. The 8087 instruction mnemonics begins with the letter ___ which stands for Floating
point and distinguishes from 8086 instructions.
Q137. The 8087 instructions for load and store for real data are_____ and ____.

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Q138. The instruction FBLD stands for ________________.

Q139. The RAM size on chip in 8051 microcontroller is ________.

Q140.The MCS-96 supports a instruction set which includes

a. bit operations
b. byte operations
c. word operations
d. All of the above
Q141. The 8096 has two ___ bit timers.
Q142. The ______Timer in 8096 is an internal timer that resets the system if the software fails to
operate properly.
Q143.The 8096 ___unit can record times of external events with a 9 state time resolution.
Q144.The PWM output waveform is a variable duty cycle pulse in 8096 that repeats every ___ state
times.
Q145. How many number of interrupt vectors is present in 8096?
Q146. ________ byte configures the 8096 to operate in different modes.
Q147. MOV direct, direct is a valid instruction in 8051. T/F
Q148. Name the instruction logically complements the value of the specified destination operand and
stores the result back in the destination operand.
Q149. ADD A,@R1 means adding the content of 8-bit internal RAM data addressed through R1 with
accumulator and result in A. T/F
Q150. SWAP A is equivalent to RR A or RL A four times. T/F
Q151. When data is pushed onto the stack the SP is decremented by one. T/F
Q152. The instruction DJNZ reg, label is used for
a. Control transfer
b. Looping
c. Decrements and Compares with zero
d. All of the above
Q153. The ACALL instruction uses 11 bits of address to address within _____ byte range.
Q154. 74C922 is a ________that performs keypad scanning and de-bouncing.
Q155. ADC1031 from National semiconductor is a __ bit ADC.

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Q156. AD7303 is dual channel 8 bit ___.

Q157. LCD module LM015 displays one line of ___ characters.
Q158. MC14489 is a multi character ___ driver.
Q159. The Memory Management unit is present in 80386 processor. T/F
Q160. How many numbers of General purpose and special purpose registers are present in the
Execution unit of 80386?
Q161. The size of the instruction pre fetch queue in 80386 is ______ bytes.
Q162. The Memory management unit in 80386 consists of a ___ unit and a ____unit.
Q163. The Paging unit in 80386 organizes the physical memory in terms of pages of 4kbytes size
each. T/F
Q164. In 80386, AX represents the lower 16 bit of the 32 bit register EAX. T/F
Q165. Name the data segment registers in 80386 processor.
Q166. How many numbers of debug registers are present in 80386 processor?
Q167. Which flag has to be set in 80386 when it is in protected mode?
Q168. TSS in 80386 stands for _______.
Q169. How many addressing modes are supported in 80386?
Q170. The interrupt vector table of 80386 has been allocated 1Kbyte space starting from___ to ___.
Q171. Which pin in 80486 provides a memory system that functions like the 1M byte real memory
system in the 8086 processor?
Q172.Which parity is generated by 80486 during every write cycle? EVEN/ODD
Q173. Which bit controls the on-chip cache in 80486?
Q174. ___________ is a cache that memory management hardware uses to improve virtual
address translation speed.
Q175. Name the cache test registers in 80486.

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Test Your Skills:

&
Quiz questions:
Microprocessors and Microcontrollers
Key Answers
Q1. T

Q2. Mini

Q3. T

Q4. Clock Speed

Q5. Reduced Instruction Set Computer

Q6. Massively Parallel Processing

Q7. F

Q8. T

Q9. DMA

Q11. DSP

Q12. Harvard

Q13. Single Instruction Multiple Data

Q14. Program data

Q15. 8

Q16. 16

Q17. HOLD HLDA

Q18. 16

Q19. ALE

Q20. 8 bits

Q21. 5

Q22. Auxiliary Carry

Q23. Absolute

Q24. T

Q25. INTR

Q26. 3 byte

Q10. Microcontroller

Q30.20

16

Q27. Non-maskable Q28.BC DE HL Q29. F

__
____
Q31. M / IO
Q32. INTR INTA Q33. 6 bytes

Q34.CS

IP

Q35. Extra Data

Q36.BIU EU

Q37.pipeline

Q38. BIU
____
Q42. BHE

Q39. 40

Q40. T1

Q41. Stack

Q43. WAIT
___ ___
Maximum mode pins: RQ/GT0 QS0

Q44.Minimum mode pins: HOLD, HLDA

__
_____
Q45.M/IO
Q46. TEST

Q47. RESET

Q48. S2 S1 S0

Q49. 16

Q50. CX

Q51. DI

Q52. TRAP

Q53. AX

Q54. 64KB

Q55. T

Q56. 16

Q57.segment

Q58. 64 MB

Q59. 32

Q60. T

Q61.CLI

Q62. 256

Q63. Divide by zero

Q64. 64KB

Q65. 1MB

Q66. AAA

Q67. AAD

Q68. AAM

Q69. AAS

Q70. Immediate

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Q71. AND

Q72. SHR

Q73.multiply by 2

Q75. Convert signed Byte to signed word

Q76. STC CLC

Q74. Data Transfer

Q77. F

Q78. DB

Q79. EXIT

Q80. EVEN

Q81. EQU

Q82. C

Q83. BYTE PTR

Q84. 21

Q85. AH

Q86. flash

Q87.static Random Access Memory

Q89. 12

Q90. T

Q93. port C

Q94. latched/buffered O/P

Q96. Mode 2
___
Q100. STB

Q97.BSR and I/O

Q98. 8 bits

Q99. Input Buffer Full

Q101. 6

Q102. 16

Q103.10 MHz

Q104. T

Q105. A0, A1

Q106.Binary BCD Q107. Mode 0

Q91. a
input

Q88. T
____ ____
Q92. CAS, RAS
Q95. Mode0, Mode1, Mode2

Q108. Rate Generator Q109. a-ii; b-iii; c-i Q110.wait for 10 ms Q111. Polling
Q112. 8279
display

Q113. 8 bytes

Q114. used to scan the key board matrix and

digits.

Q115. BD

Q116. IW (inhibit write flag)

Q117.In-service register Q118.IMR (Interrupt Mask Register)

Q119. T

Q120. 8

Q122. F

Q121. automatic end of interrupt

Q123. Fully Nested Mode

Q124. IR0 has the highest priority and IR7 has the lowest one.

Q125. dynamic scattering and field-effect

Q127. 8086 and 8088 Q128. 16 bits
Q130. FLDCW

Q126. SOC and EOC

Q129.Denormalized error

Q131. Precision control Q132. Round up towards plus infinity

Q133. Numeric Execution Unit

Q134. D

Q135. D

Q136. F

Q137. FLD and FST Q138. Load BCD

Q139. 128 bytes

Q140. D

Q141. 16

Q142. Watchdog

Q143. HIS

Q144. 256

Q145. 8

Q146. Chip Configuration Byte

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Q147. T

Q148. CPL

Q149. T

Q150.

Q151. F

Q152. D

Q153. 2K

Q154. 16 key encoder

Q155. 10

Q156. DAC

Q157. 16

Q158. LED

Q159. T

Q160. 8 general purpose and 8 special purpose registers

Q161. 16

Q162. Segmentation and Paging

Q163. T

Q164. T

Q165. DS, ES, FS, GS

Q166. 8

Q167. VM

Q168. Task state segment descriptor Q169. 11

Q170. 00000H to 003FFH

Q171. A20M3

Q172. EVEN Q173. PCD

Q174. Translation Look aside

Buffer

Q175. TR3, TR4, TR5

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