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Lecture 30:
Prof J. S. Smith
Department of EECS
Prof. J. S. Smith
Context
In todays lecture, by request, we will
look at more single transistor active
circuits and example problems, and
start multi-stage amplifiers
Department of EECS
Prof. J. S. Smith
Reading
z
Department of EECS
Prof. J. S. Smith
Lecture Outline
z
z
z
LED driver
Peak detector
CS amplifier with active pullup
z
z
z
z
z
Department of EECS
Transimpedance Amplifier
Source Follower
Current Mirror
Push-Pull Amplifier
Multistage Amplifiers
University of California, Berkeley
Prof. J. S. Smith
z
z
Department of EECS
Prof. J. S. Smith
R=330 ohms
Department of EECS
Prof. J. S. Smith
R=330 ohms
Department of EECS
Prof. J. S. Smith
Department of EECS
Prof. J. S. Smith
+
R2
Vout
Prof. J. S. Smith
R3
R1
R2
We will do this better
later with a two stage C
amplifier and negative
feedback
Vout
Prof. J. S. Smith
z
z
z
1/gm2 << ro
Low frequency operation
the body effect can be neglected in both transistors.
Department of EECS
Prof. J. S. Smith
The amplifier gain is the ratio of the ss output voltage to the ss input
voltage:
i 1g
v
g
Av = out = d
= m1
1
vin
id g
gm2
m2
m1
Taking into account the finite resistance of the FET (ro) gives:
1
ro1 ro 2
v
g m1
g
Av = out =
=
1
vin
g m 2 + r 1r
g
m2
o1
Department of EECS
o2
m1
Prof. J. S. Smith
Frequency Response
To find the frequency response of the active pull up common source
Amplifier, we need to put in the parasitic capacitances:
Prof. J. S. Smith
Figure 22.5
z
1
RS (CMI + C gs1 )
CMI = C gd 1 1 +
g m1
gm2
Department of EECS
1
2 g m 2 (C gs 2 + C MO + Cdb1 + Cdb 2 )
1
CMO = C gd 1 1 +
gm2
g m1
Prof. J. S. Smith
Transimpedance Amplifier
Figure 22.8
id g1
vout
W1 L3
= W3mL21 =
iin
g m 2W3 L1
id W1L3
Department of EECS
Prof. J. S. Smith
Source Follower
Figure 22.11
Gain:
Department of EECS
v
Av = out =
vin
1
g m1
1
g m1
1
gm 2
1
1
=
g m1
1 + g m 2 1 + WW1LL2
2 1
University of California, Berkeley
Prof. J. S. Smith
Av =
z
2 1
g m1
=
1
1
(1 + 2 ) I D
ro1 + ro 2
Department of EECS
Prof. J. S. Smith
Current Mirror
Department of EECS
I D 2 W2 L1
=
I D1 W1 L2
Prof. J. S. Smith
Push-Pull Amplifier
Gain:
Av =
vout id (ro1 ro 2 )
=
= ( g m1 + g m 2 ) (ro1 ro 2 )
vin
id g1m1 g1m 2
Department of EECS
Prof. J. S. Smith
Multistage Amplifiers
Necessary to meet typical specifications for any of the 4 types
We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and
the npn versions of CE, CB, and CC (for a BiCMOS
process)
What are the constraints?
1. Input/output resistance matching
2. DC coupling (no passive elements to block the signal)
Department of EECS
10
Prof. J. S. Smith
Rout
Voltage:
Current:
Transconductance:
Transresistance:
Department of EECS
Prof. J. S. Smith
CS1
CS1,2
11
Prof. J. S. Smith
Cascading stages
CS2
CS1
CD3
Input resistance:
Voltage gain (2-port parameter):
Av = g m1 ( ro1 || roc1 ) g m 2 ( ro 2 || roc 2 )
Output resistance:
Rout =
1
g m + g mb
Department of EECS
Prof. J. S. Smith
CB2
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12
Prof. J. S. Smith
Two-Port Models
Prof. J. S. Smith
Common-Gate
2nd
Stage
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13
Prof. J. S. Smith
3.2V
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Prof. J. S. Smith
3.2V
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14
Prof. J. S. Smith
CG Cascade: DC Biasing
Two stages can have different supply currents
Extreme case:
IBIAS2 = 0 A
Department of EECS
Prof. J. S. Smith
Department of EECS
15
Prof. J. S. Smith
DC bias:
Department of EECS
16