a al

a | Sami Nuuttila
Mikko Pank

Cadence Circuit Design Tools

TUCS Technical Report

No 831, June 2007

Cadence Circuit Design Tools

a al
a
Mikko Pank

University of Turku, Department of Information Technology

Joukahaisenkatu 3-5, 20520 Turku, Finland
mtpank@utu.fi

Sami Nuuttila

University of Turku, Department of Information Technology

Joukahaisenkatu 3-5, 20520 Turku, Finland
samnuut@utu.fi

TUCS Technical Report

No 831, June 2007

Abstract
This document is an attempt to give a short description of available Cadence tools
for circuit design through Europractise (2006/2007 Release) at the University of
Turku. It tries to answer two questions: What kind of tools we have? and What
are they for? Moreover, a selected set of the most important system files and
directories related to analog IC design are examined more closely.

Keywords: CADENCE, IC design

TUCS Laboratory
Microelectronics

1 Introduction and Objectives

We have two objectives for writing this document. First, to increase the knowledge of available Cadence circuit design tools among users at our department.
Second, we provide information what are the tools for.
However, the purpose is not to provide an exhaustive study of all available tools,
but merely to give a short description of the main features of each tool and thereby
to encourage users to find out more of the tools that could be useful for their purposes. The focus is on analog circuit design tools, but some tools for digital design
are also introduced to get a more comprehensive insight of Cadences tool repertoire.
One of the reasons that gave rise to writing this document was that by providing
the basic knowledge about the most important Cadence related system files (for
analog IC design) could help people to fix the most common problems by themselves.

2 Cadence Circuit Design Tools

This chapter introduces different Cadence circuit design tools available at the University of Turku. Tools are provided by Europractice and the 2006/2007 release
is of specific interest. A more or less complete list of this release can be found at
http://www.msc.rl.ac.uk/europractice/software/cadence 06 07.html. If you look
at the webpage, most of the software listed under IC Package are installed and
the rest can (probably) be installed by request. The contents of the IC Package is
replicated in tables 1 and 2 on the next pages. Table 1 lists the tools for digital and
mixed-mode design and table 2 for analog and mixed-mode design respectively. It
can be expected that even more than before, more specialized tools are introduced
as processing technology develops towards smaller and smaller devices. But that
is another story. Next we will take a look where we are now. After the list, the
main features of each tool are discussed.
Notice that most of the tools are embedded tightly to the Cadence Design Framework and do not have specific graphical user interface (GUI) of their own. The
only cue of their existence can be an additional menu in some other tool. To get
an idea of the tools available at your current set up start CIW (eg. with command
icfb), choose CIW > Options > License. . . and check the list of available
licenses.
1

From IUS 5.7/QSR2:

Verifault-XL simulator
Cadence Export Model Packager
Incisive(TM) Design Team Simulator
From SPMN 5.0.3:
Incisive Enterprise Specman Elite
From VMGR 1.3.1:
Incisive Enterprise Manager
From CCD 6.1:
Encounter Conformal Constraint Designer - XL
From CONFRML 6.1:
Release Information for System Admins
From SOC 5.2/USR3:
Release Information for System Admins
Route Accelerator Multi-Threaded Route Option
From EXT 5.1/USR1(5.1.1):
Release Information for System Admins
Advanced Option to Fire & Ice (gate) or Fire & Ice
(gate & transistor)
From SEV 4.1/USR3(4.1.3):
Release Information for System Admins
From TSI 5.2/USR2:
Release Information for System Admins
SignalStorm NDC Nanometer Delay Calculator
SignalStorm Library Characterizer Expansion Pack
From ASSURA3.1.5/USR1:
Release Information for System Admins
Assura(TM) Layout Vs. Schematic Verifier
Assura(TM) RCX Field Solver Option
Assura(TM) RCX Multiprocessor Option
Assura(TM) Multiprocessor Option

64bit Verifault-XL simulator

AMS Option to Incisive(TM)
Release Information for System Admins

Encounter (TM) Conformal - GXL

Cadence SoC Encounter - GXL

Fire & Ice QX (gate)

Nanometer Option to Fire & Ice (gate) or
Fire & Ice (gate & transistor)
VoltageStorm PE
CeltIC NDC Crosstalk Analyzer with Delay
Calculator
SignalStorm Library Characterizer

Assura(TM) Design Rule Checker

Assura(TM) Parasitic Extractor
Assura(TM) RCX Parasitic Inductance Option
Assura(TM) RCX High Frequency Option

Table 1: Tools for digital and mixed-mode design delivered with the IC Package

From IC 5.1.41/ISR:
Cadence Design Framework II
64bit Cadence Design Framework Int
Virtuoso Simulation Environment
Virtuoso Schematic Editor Verilog Interface
Virtuoso-XL Layout Editor
Virtuoso Compactor
Virtuoso Analog Oasis Run-Time Option
Virtuoso Electronic Design for Manufacturability
Option
Spectre Verilog-A Simulation Option
Spectre-RF IC Package Modeler Option
Virtuoso Schematic Editor
Spectre-RF Substrate Coupling Analysis Option
Virtuoso Analog ElectronStorm Option
Structure Compiler
Cadence(R) RC Network Reducer Option
Dracula Design Rule Checker
Dracula Layout Vs. Schematic Verifier
Dracula Parasitic Extractor
Diva Design Rule Checker
Diva Layout Vs. Schematic Verifier
Diva Parasitic Extractor
Cadence SKILL Development Environment
Virtuoso EDIF 300 Schematic Reader/Writer
From ICC 11.2.41/USR3:
Virtuoso Chip Assembly Router
From MMSIM 6.0/ISR:
Virtuoso Spectre Circuit Simulator
Virtuoso Spectre-RF Simulation Option
Virtuoso UltraSim Full-chip Simulator
Release Information for System Admins
From AES 1.0:
Cadence Advanced Encryption Standard-64bit
From NEOCKT 3.3/ISR(3.3.4):
Virtuoso NeoCircuit DFM
ELDO Interface to Virtuoso NeoCircuit
ADS Interface to Virtuoso NeoCircuit
From VSDE 4.1/USR1:
Virtuoso Parallel Analysis Option
Virtuoso Characterization & Modeling option
for
3
the Specification-driven Environment

Cadence Design Framework Integrators

Toolkit
Virtuoso Preview
Virtuoso Schematic VHDL Interface
Virtuoso Schematic Editor HSPICE Interface
64bit Virtuoso Layout Editor
Virtuoso Layout Editor Turbo
Cadence OASIS for RFDE
Spectre Third-party Simulator Interface
Spectre/-RF - Cadence SPW Model Link
Option to Spectre RF
Virtuoso Analog HSPICE Interface Option
Virtuoso Analog Design Environment
Virtuoso Analog VoltageStorm Option
Virtuoso Layout Migrate
Virtuoso Schematic Composer to design
compiler integration
Virtuoso AMS Designer Environment
64bit Dracula Design Rule Checker
64bit Dracula Layout Vs. Schematic
64bit Dracula Parasitic Extractor
64bit Diva Design Rule Checker
64bit Diva Layout Vs. Schematic Verifier
Release Information for System Admins
Virtuoso
EDIF
300
Connectivity
Reader/Writer
Cadence team design project administrator

Virtuoso Spectre Model Interface Option

Spectre/-RF - Cadence SPW Model Link
Option to Spectre RF
Virtuoso RelXpert

Release Information for System Admins

HSPICE Interface to Virtuoso NeoCircuit

Virtuoso Specification-driven Environment

Virtuoso Optimization option for the
Specification-driven Environment

Table 2: Tools for analog and mixed-mode design delivered with the IC Package

2.1 Tools for Digital and Mixed-mode design

The tools listed in the following are divided into two gategories. The first set of
tools is for front-end digital design (logic design and verification) and the second
is for back-end design (place & route, delay calculation, timing analysis etc.). The
list is not comprehensive, but tries to cover the most relevant tools.
2.1.1 Logic Design and Verification
NCLaunch
NCLaunch provides you with a graphical user interface to configure and launch
your Cadence simulation tools.
NC-VHDL simulator
The Cadence NC-VHDL simulator C Interface (CIF) is part of the Open Architecture of the Cadence NC-VHDL simulator product. The Open Architecture is a
collection of libraries that allow access to the NC-VHDL simulator environment.
The Open Architecture includes:
The C Function Call library (CFC)
The CFC library lets you call C functions from the simulator command line.
The Foreign Model Import library (FMI)
The FMI library enables models written in the C programming language
and VHDL subprograms to be executed by the simulator.
The VHDL Design Access library (VDA)
The VDA library contains a set of routines and definitions for manipulating
VHDL objects, scopes, values, and types.
SimVision
SimVision is a unified graphical debugging environment for Cadence simulators.
You can use SimVision to debug digital, analog, or mixed-signal designs written
in Verilog, VHDL, SystemC, or a combination of those languages.
NC-Verilog simulator
The Cadence NC-Verilog simulator is a Verilog digital logic simulator that combines the high-performance of native compiled code simulation with the accuracy,
flexibility, and debugging capabilities of event-driven simulation. The NC-Verilog
simulator is based on Cadences Interleaved Native Compiled Code Architecture
(INCA).
NC-SystemC simulator
SystemC, as an industry standard for system-level design modeling, supports the
description of the architecture of complex systems consisting of both software and
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hardware components. The SystemC environment is the C++ programming language with additional semantics introduced by the SystemC Class Library. This
library provides the constructs necessary to model system architecture, including
hardware timing, concurrency, and reactive behavior.
The Cadence SystemC Design and Verification environment, as part of the IncisiveTM unified simulation platform, consists of a set of simulation and debugging
capabilities that allows you to address your needs in both the design and verification of system hardware and software. The NC-SystemC simulator is a platform
for simulation and debugging SystemC models, either pure or mixed with Verilog
or VHDL.
Verifault-XL
Verifault-XL is a fault simulation system that operates within the Verilog-XL environment using the same libraries that Verilog-XL uses. Verifault-XL allows chip,
board, and system designers to simulate the faults that can occur in the hardware
represented by their design descriptions and to develop test vectors that can detect
those faults.
Verifault-XL simulates faults at the gate-and-switch, or structural, level. However,
your circuit descriptions may contain elements that are described using behavioral constructs. Therefore, Verifault-XL lets you propagate the effects of faults
through both structural and behavioral constructs, making it a true mixed-level
fault simulator.
Verifault-XL supports bit annotation, which lets you place buses in specific blocks
for timing constructs. As a result, you do not need to split the individual bits of a
bus to apply timing information to them.
Cadence HDL analysis and lint (HAL)
HAL is a design rule checker for Verilog Hardware Description Language (HDL),
Very High-speed integrated circuit Hardware Description Language (VHDL), SystemC and Mixed Language designs.
HAL helps you find coding errors early in your design process, before you simulate your design. The tool identifies coding errors and improper register transfer
level (RTL) design styles through a comprehensive analysis of your HDL source
code.
IP Model Packager
The IP Model Packager is a model export tool that creates a protected model. You
can simulate a packaged model in standard HDL simulation environments with
the model manager software that is included in the packaged model.
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Note: To use the IP Model Packager most effectively, you should be familiar
with performing digital design and analysis using either the Verilog Hardware
Description Language (HDL), or the Very High Speed Integrated Circuit Hardware Description Language (VHDL), and you should be familiar with either the
Verilog-XL simulator or the Cadence NC simulator.
Incisive Coverage
Coverage analysis at the RTL or behavioral level is analogous to fault coverage
at the gate level. Performing coverage analysis prior to synthesis reduces the test
verification cycle by moving the process to a higher level of abstraction where the
testbench is more easily understood with regard to the code it is testing.
Without code coverage, the design engineer can only guarantee that the outputs
from functional simulation match the expected results for a given set of test vectors; there is no way to ensure the effectiveness of the test vectors. Without knowing how well the test vectors are exercising the design, the designer does not know
if more test vectors are needed, where more test vectors are needed, or when to
stop simulating. Incisive Coverage Technology enables the designer to answer all
of these questions.
Using Coverage Technology prior to synthesis is the most productive way of using the tool. The coverage tool supports coverage analysis at all levels of design
abstraction and for all Verilog/VHDL language constructs. The coverage tool enables designers and design verification engineers to generate a quantitative answer
to the question: Have we simulated our design enough to commit it to synthesis?
Incisive Coverage Technology works in conjunction with HDL simulation to quantify how well the test vectors exercise the design and to identify parts of a design
that require more testing. Coverage analysis reports identify
Design areas not completely tested,
Redundancy in testing, and
Unused portions of the design that can be removed before synthesis.
The Finite State Machine (FSM) monitoring capability gives you a unique way
of quantifying coverage of the control portions of the design. USX technology
performs a synthesis interpretation of the control logic and provides analysis using FSM representation. Together with code coverage analysis, The coverage tool
provides a comprehensive, quantitative measure of the quality of the simulation
tests applied to a design.

FormalCheck Model Checker

The Cadence FormalCheck Model Checker verifies synthesizable Verilog Hardware Description Language (Verilog HDL) and Very High-Speed Integrated Circuit Hardware Description Language (VHDL) designs. FormalCheck is designed
to operate as a companion to any digital simulator for Verilog or VHDL.
FormalCheck functionally verifies a VHDL or Verilog design against a design
specification by answering the question: Does my design function according to
its specification? FormalCheck does this through model checking, rather than using test vectors or testbenches.
Model checking is an algorithmic procedure to verify that a design possesses designated properties. The procedure analyzes all possible behaviors of a design, and
can verify properties with mathematical certainty. Applying model checking to
a design corresponds to simulating the design for every possible test vector sequence for an infinite number of arbitrarily long tests.
Using model checking techniques, FormalCheck finds design errors that are difficult or impossible to detect using traditional simulation tools. These errors include
those that occur under complex, hard-to-anticipate sequential conditions. While
such errors are notoriously difficult to find, either with designed or random test
vectors, they are routinely detected by a model checker.
The FormalCheck Model Checker detects errors in a fully automated fashion. This
means that a FormalCheck automated verification run does not require you to anticipate errors. Thrashing (livelock) conditions, which cannot be detected directly
by simulators at all, are also found with fully automated model checking.
Model checking is most effective on control-intensive designs (designs without
extensive data paths). You may verify properties that you define in FormalCheck
with a digital simulator on those portions of a design where model checking is
less effective. This is supported by a utility that transforms the properties into a
testbench for the simulator.
It is not necessary to have any specialized mathematical knowledge, nor is it necessary to learn a specific model checking language to use FormalCheck. FormalCheck can be used with familiar HDL language constructs and command-line
interface (CLI) commands to verify designs.

Figure 1: Cadence design flow with tools introduced in this chapter

2.1.2 Encounter Family for Back-end Design

Figure 1 presents Cadence design flow with the tools introduced in the following.
SoC Encounter - GXL
The Encounter family consists of four products:
First Encounter Ultra silicon virtual prototyping solution
Nano EncounterTM implementation system for flat designs
Nano Encounter Demand-Based Savings (DBS) system
SoC EncounterTM hierarchical RTL-to-GDSII physical implementation solution
(NanoRouteTM Ultra SoC routing solution)
The First Encounter Ultra product includes the following features:
RTL synthesis
Creates a gate-level netlist from Register Transfer Language (RTL) input.
Virtual prototyping and placement
Provides quick feedback on the design performance. With this feature, you
first create a block-and-cell placement, then perform trial routing, analyze
timing, and refine the design to meet your specifications.
Hierarchical partitioning and block placement
Lets you create a hierarchical design consisting of a top-level floorplan
that contains blocks you implement separately. At the top level you define
blocks, analyze congestion and timing, and refine the design as needed. The
system automatically creates timing budgets and optimized pin locations to
use in physical implementation.
Timing optimization
Provides in-place optimization, which improves timing by inserting buffers
and resizing gates, without changing the designs logic. Includes a physical
synthesis solution to close timing for difficult blocks.
The Nano Encounter product includes the following features for flat design flows:
Support for 90 nm and 130 nm process rules
Virtual prototyping and placement
Physical synthesis optimization
Note: You cannot perform RTL synthesis.
9

 WRoute router
Provides traditional grid-based global and detailed routing of signal and
clock nets.
Power router
Provides the ability to create power rings and stripes, and perform power
routing.
NanoRoute router
Provides high-speed graph-based global and detailed routing for large-capacity
designs.
Geometry, connectivity, and antenna verification
Signal wire editing
Block antenna abstract creation
GDSII generation
An optional Route Accelerator license provides multi-thread capability that lets
you run WRoute and NanoRoute on multiple CPUs.
Nano Encounter Demand-Based Savings (DBS)
The Nano Encounter DBS product is a cost-saving alternative to Nano Encounter
that provides all of the major features of Nano Encounter, but for smaller designs.
Each Nano Encounter DBS license supports designs with up to 300,000 placeable instances (excluding filler cells). If your design grows beyond that limit,
Encounter can check out additional Nano Encounter DBS licenses to support the
larger design.
The Nano Encounter DBS user interface provides access to all of the major Nano
Encounter components, including NanoRoute, WRoute, SRoute, and ClockWise.
However, with the exception of WRoute, the interface does not support use of
these tools in standalone mode, and it does not support the Coyote field solver.
Additionally, support for multi-threading with Nano Encounter DBS requires a
separate Route Accelerator license for each additional thread.
NanoRoute Ultra
The NanoRoute Ultra product is a self-contained, block-level and top-level routing solution for system-on-chip (SoC) designs. It has the same features as Nano
Encounter, except for virtual prototyping and placement.
The SoC Encounter product is a full hierarchical floorplanning and routing solution. It provides a broad spectrum of features, including the following features
contained in First Encounter Ultra and Nano Encounter:
10

 RTL synthesis
Virtual prototyping and placement
Hierarchical partitioning and block placement
Timing optimization
Virtual prototyping and placement
Physical synthesis optimization
WRoute router
Power router
NanoRoute router
Geometry, connectivity, and antenna verification
Signal wire editing
Block antenna abstract creation
GDSII generation
SoC Encounter also includes the following feature, which is not included in the
other Encounter products:
Sign-off signal integrity
The CeltICTM crosstalk analyzer for cell-based design prevents, calculates,
and repairs crosstalk noise caused by interconnect coupling. This tool can
also calculate and repair glitch noise and the delay effects of noise for static
timing analysis.
SoC Encounter provides an easy upgrade path from the Silicon Ensemble family,
with legacy support.
Voltage Storm PE
VoltageStorm PE is designed to help you verify that the power-grid network on
your chip does not suffer from IR drop, ground bounce, or electromigration problems.
Because VoltageStorm PE does not require the signal routing of your design to
be complete before power-grid analysis, it enables you to verify and change your
power grid early in the design cycle.
VoltageStorm PE offers the following features:
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 Multi-level hierarchical power-grid verification

Pass/fail power-grid validation
Accurate embedded 130 nanometer and below parasitic extraction that models effects resulting from advanced copper processes, such as chemical mechanical polishing (CMP), such as erosion, dishing, and slotting, and optical
effects, such as non-trapezoidal wires and wire-edge enlargement.
Integration with Cadence SoC Encounter
Integration with CeltIC NDC
Support for multiple design formats such as LEF/DEF, GDSII, a mixture of
DEF and GDSII, or OpenAccess 2.2
Static and dynamic gate-level power-grid analysis
Instance-based static and dynamic power-consumption analysis, including
IP and memories
Hierarchical power-grid analysis and signoff for cell-based designs
Power distribution estimation for hard IPs and macros
Power planning
User-selectable power-ground short detection
Via clustering
What if analysis using PGS Exploration, which enables you to interactively experiment to fix problems and optimize the power distribution network
Use of power-grid views to efficiently support designs that contain custom
or IP blocks
Selective accuracy to support early verification and signoff accuracy
Standard interfaces
Package modeling
CeltIC NDC Crosstalk Analyzer with Delay Calculator
The CeltICTM crosstalk analyzer analyzes and fixes crosstalk-related functional
and timing problems for cell-based designs. It calculates noise-induced delay
changes for static timing analysis and generates repairs for place-and-route.
CeltIC offers the following features:
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 Characterize the cell library for noise.

Calculate crosstalk noise caused by interconnect coupling.
Filter out false noise failures.
Calculate crosstalk-induce delay and slew changes for Static Timing Analysis (STA).
Generate ECO repairs for optimization.
Physically Knowledgeable Synthesis (PKS)
Cadence Physically Knowledgeable Synthesis (PKS) is a Cadence physical synthesis product and a part of the unified synthesis and place-and-route (SP&R)
flow. PKS provides physical placement and timing information in combination
with logic synthesis (BuildGates Synthesis) to resolve the timing closure issues
that currently plague conventional synthesis. Its purpose is to provide logic synthesis technology with a means to accurately predict timing based on the incremental physical placement of cells during the optimization process.
Fire & Ice QX (gate)
Fire & Ice QX (QX) is an accurate, high-capacity, high-performance gate-level
parasitic resistance and capacitance extractor that is fast enough to use after every
detailed routing session.
In 0.13m and below processes, signal delay due to interconnect parasitics becomes much more significant than the contribution to signal delay due to the inherent cell delays. Approximately 80% of the delay for most paths is now due
to interconnect delays. Therefore accurate modeling of the parasitics on the interconnects is vital for high performance chip designs. Also, signal integrity analysis
requires accurate coupling capacitance extraction. However, accuracy of parasitic
extraction comes at a cost - in terms of run time for performing the extraction. It
is a function of design size, process, desired results, and the number and configurations of systems that are available to do the extraction.
Three-Dimensional Interconnect Modeling and RCgen
Cadence tools use analytical modeling to model the interconnect parasitic capacitance and resistance of an integrated circuit design. QX uses a technology file,
created from the fabrication process information, along with cell library data and
the design itself, for resistance and capacitance extraction. The fabrication process information is entered into an ASCII-format interconnect technology (ICT)
input file from which RCgen generates a technology file for QX. This technology
file is often created and validated by the major foundries. This file contains interconnect models used by QX to extract the interconnect parasitic capacitance and
13

resistance. For resistance extraction, it contains resistance information on each interconnect layer and via; for capacitance extraction, it contains three-dimensional
interconnect models.

2.2 Tools for Analog and Mixed-mode design

Cadence IC package includes a wide variety of different tools for analog and
mixed-mode design, as can be seen in table 2. The most important tools are discussed next.

2.2.1 AMS Environment

The AMS flow uses the AMS environment and a set of tools tuned to facilitate the
development of mixed-signal designs. The flow gives you a mixed-signal, mixedlanguage, block-based design solution featuring the following characteristics.
A top-down or bottom-up development methodology for both analog and
mixed-signal designs.
The ability to mix blocks at different levels of abstraction for an optimized
balance of simulation accuracy versus speed
The ability to create Verilog-AMS netlists for an entire library with a single
command
Automatic, non-destructive conversion of existing analog primitive libraries
A design capture environment that facilitates both text and schematic data
entry
Support for the Verilog-AMS, VHDL-AMS, Spectre, and SPICE languages
Flexible and accurate representation of analog/digital interface boundaries
and accurate, automatic insertion of interface elements
Flexible and accurate representation of mixed-language boundaries
Flexible design configuration, which allows easy switching from one design
representation to another
Accelerated, automatic netlist generation from schematics
A single debugging environment for analog, digital, and mixed-signal parts
of your design
14

 Stand-alone simulation when desired

A single unified waveform display for analog, digital, and mixed signal nets
in your design
The tools in the AMS flow work smoothly together, so you can move from one
tool to another without worrying about whether your data is in the necessary format. For example, when you work within the flow, you can develop a schematic,
define a configuration, and then simulate without working through a netlisting
step: the flow netlists the design for you as needed or uses a netlist created by
someone else for a block you are referencing.

2.2.2 Cadence analog design environment(ADE)

The features of the Cadence analog design environment
Consistent User Interface
Analog Design Entry
Design Hierarchy
Annotation
Interactive Simulation
Simulation Output and Analysis
Parametric Analysis
2.2.3 Waveform Calculator
The Waveform Calculator is a scientific calculator with both algebraic and Reverse
Polish Notation (RPN) modes. You can use it to
Build, print, and plot expressions containing your simulation output data
Enter expressions, which can contain node voltages, port currents, operating
points, model parameters, noise parameters, design variables, mathematical
functions, or arithmetic operators, into a buffer
Store the buffer contents into a memory and then recall the memory contents
back into the buffer
Save calculator memories to a file and load those memories back into the
calculator
15

2.2.4 Cadence mixed-signal circuit design environment (icms)

The features of the Cadence mixed-signal circuit design environment let you create, simulate, and analyze designs containing both analog and digital components.
Mixed-signal design examples are available for you to try out the mixed-signal
flow on CDBA. They are located in
/soft/cadence/ic5033usr2/tools/dfII/samples/artist/mixSig. See README file.
2.2.5 SKILL language
The Cadence SKILL language is a high-level, interactive programming language
based on the popular artificial intelligence language, Lisp. However, the SKILL
language supports a more conventional C-like syntax. This support allows a
novice user to quickly learn to use the system, while expert programmers can
access the full power of the Lisp language. At the simplest level, SKILL is as
easy to use as a calculator. At the most sophisticated level, SKILL is a powerful
programming language whose applications are virtually unlimited.
SKILL brings to the command line a functional interface to the underlying subsystems. SKILL lets you quickly and easily customize existing CAD applications
and helps you develop new applications. SKILL has functions to access each Cadence tool using an application programming interface.

2.2.6 Open Command Environment for Analysis (OCEAN)

OCEAN lets you set up, simulate, and analyze circuit data. OCEAN is a textbased process that you can run from a UNIX shell or from the Command Interpreter Window (CIW). You can type OCEAN commands in an interactive session,
or you can create scripts containing your commands, then load those scripts into
OCEAN. OCEAN can be used with any simulator integrated into the Cadence
Analog Design Environment.
Typically, you use the Cadence analog design environment when creating your
circuit (in Composer) and when interactively debugging the circuit. After the
circuit has the performance you want, you can use OCEAN to run your scripts
and test the circuit under a variety of conditions. After making changes to your
circuit, you can easily rerun your scripts. OCEAN lets you
Create scripts that you can run repeatedly to verify circuit performance
Run longer analyses such as parametric analyses, Corners Analyses, and
statistical analyses more effectively
16

 Run long simulations in OCEAN without starting the Cadence analog design environment graphical user interface
Run simulations from a nongraphic, remote terminal
OCEAN examples are located in
/soft/cadence/ic5033usr2/tools/dfII/samples/artist/OCEAN. See README file.
2.2.7 Virtuoso Specification-driven Environment (SdE)
The Virtuoso Specification-driven Environment (SdE) is an interactive design environment for the analysis, characterization, and verification of analog, digital,
and mixed-signal circuits. The SdE is also integrated with the Virtuoso Schematic
Editor and can be used with multiple designs simultaneously.
Note: The Virtuoso Specification-driven Environment is OpenAccess compliant.
The Virtuoso Specification-driven Environment helps you:
Set up simulation parameters
Execute simulation jobs (using parallel processing)
Generate results
Analyze results using data analysis scripts
The following tasks are performed in the environment:
Create test benches
Explore design characteristics
Run experiments and corners analyses
Perform optimization and Monte Carlo analysis
View, plot, and analyze results
Perform pass/fail validation of operational and performance specs
Create silicon-calibrated behavioral models
Create or modify plans for characterization, model calibration, etc.
Set up optimizations and create synthesis plans
17

For ease of reuse, and organizing design data and results, projects are organized
into workspaces using a lib/cell/view hierarchy. One or more related projects (or
designs) can be made available in the environment at the same time. Multiple
tests can be used to characterize a design, and a sweep analysis can vary one or
more parameters over multiple tests in a project. The Spec Sheet tool can be used
to verify whether a circuits target behavior and performance goals are met. The
environment supports distributed simulation to execute multiple tests and experiments in parallel. Silicon-calibrated behavioral models help to reduce simulation
times significantly. The environment promotes reuse of design components and
the capture of design Intellectual Property.

2.2.8 Virtuoso Schematic Composer

The Virtuoso Schematic Composer is a design entry tool that supports the work of
logic and circuit design engineers, including drafters. Physical layout designers
and printed circuit board designers can use the information as background material to support their work.

2.2.9 Virtuoso layout

You use Virtuoso layout tools to prepare custom integrated circuit designs. The
layout editor is the base editor in the Virtuoso set of tools.
The layout editor lets you perform the following tasks:
Create and edit polygons, paths, rectangles, circles, ellipses, donuts, pins,
and contacts in layout cellviews
Place cells into other cells to create hierarchical designs
Connect a pin or group of pins in a net internally or externally
Automate each stage of the design task using the Virtuoso XL Layout Editor
Create special parameterized cells (called pcells) containing data that you
want to modify quickly or that you want to set with Cadence SKILL language commands
2.2.10 Virtuoso Layout Migrate
Virtuoso Layout Migrate (Migrate) is a software tool that can quickly and automatically migrate an existing integrated circuit (IC) layout to a new layout for a
target process.

18

Migrate enforces all design rules of the target process and all device and wire parameters for the target circuit. However Migrate does more than design rule and
circuit parameter enforcement, it also optimizes the layout by minimizing the total layout area, reducing wire length and capacitance, and decreasing contact and
power routing resistance.
Note: Migrate does not need design rules for the source layout to operate. However, to make best use of Migrates features, you will need to have access to a .qtt
file which describes the design rules to be enforced for the target process.
Virtuoso Layout Migrate (Migrate) is fully integrated into Cadences Virtuoso layout editing tools and can perform layout migration and/or optimization directly on
your Cadence database library.

2.2.11 Virtuoso Preview

Virtuoso Preview is a flexible floorplanner that helps you plan your physical design. You use Virtuoso Preview to predict and assess the effects of physical layout
before you place and route your design. This speeds up the design process by
minimizing costly iterations.
Using Virtuoso Preview, you can design from the top down or from the bottom
up. The physical hierarchy can be independent of the logical hierarchy. You can
flatten some or all of a logical design, or you can create soft blocks that you later
synthesize, place, and route.
Virtuoso Preview lets you perform operations such as chop, reshape, stretch, and
move on the rectilinear blocks. Using Virtuoso Preview, you can move and align
pins, and differentiate between analog and digital blocks. You can, therefore, use
Virtuoso Preview for mixed signal floorplanning as well.
Virtuoso Preview can be used as a floorplanner at different stages of your design:
For high-level floorplanning at the behavioral level to predict size and performance.
For gate-level or cell-level floorplanning, when you place and route the design.
When you use Virtuoso Preview before placement, you use it to assess the
floorplan, die size, and delay estimates. When you use it after placement and
before routing, you use Virtuoso Preview to re-evaluate timing and congestion.
19

 For floorplanning at any other time in the design

The Virtuoso Preview floorplanner links the logic design tools to the place
and route tools at the gate, cell, or block level. It breaks down the traditional
wall between the front-end logic and back-end physical design as follows.
Floorplanning gives the front-end logic designer more control over the backend physical design process. For example, the logic designer can communicate design requirements by partitioning the design to provide a starting
point for physical layout.
Virtuoso Preview lets the logic designer identify critical timing paths and
modify the design and floorplan accordingly, before the design is placed and
routed. Virtuoso Preview provides more accurate timing estimates than the
logic timing analyzer at the front end, because it generates delay estimates
based on wire length in addition to estimates based on fanout.
Virtuoso Preview lets the logic designer accurately predict the size and performance of the physical layout.
Virtuoso Preview lets you backannotate the logical design with the floorplanning results.
See Virtuoso Preview multimedia demonstrations page:
/soft/cadence/ic5033usr2/doc/previewWN/examples/ virtuoso preview demos.html
2.2.12 Virtuoso XL layout editor
The Virtuoso XL layout editor (Virtuoso XL) is a connectivity-based editing tool
that automates each stage of the design task, from component generation through
automatic/interactive routing. When used as part of an automated custom physical
design methodology, Virtuoso XL lets you generate custom layouts from schematics or netlists and edit layouts that have defined connectivity.
Virtuoso XL continuously monitors connections of components in the layout and
compares them with connections in the schematic. You can use Virtuoso XL to
view incomplete nets, shorts, invalid connections, and overlaps to help you wire
your design. It lets you both speed up and customize the layout process.
Virtuoso XL extends the Virtuoso layout editor with advanced interactive editing
capability and provides a design environment that integrates automated place-androute functionality. Virtuoso XL combines the schematic connectivity information
with the physical layout data to create an automated method for generating physical layout data. Virtuoso XL is compatible with legacy design data. Once pin
information has been added to legacy layout design data, Virtuoso XL can use the
cells in the connectivity mode.

20

2.2.13 Virtuoso custom placer

The Virtuoso custom placer is an automated solution for placing components and
cells in both block and cell-level designs. You control placement using topological
and geometric constraints. You can enter constraints into the Constraint Manager
from either the Constraint Manager or layout cellviews. All placement activity is
initiated from within Virtuoso XL.
The main features of the placer are the following:
Re-entrant automated batch placement capability within the Virtuoso Layout environment
Connectivity and constraint-driven placement to achieve overall shortest
wiring length
Supports a wide variety of placement styles automatically
Row-based MOS
Row-based standard cell
Area-based analog
Supports any combination of the above placement styles concurrently
Manual capabilities to partition placement
Accelerates engineering change orders
Placement constraints supported: Distance
Alignment
Grouping
Symmetry
Fixed
Automatic row generation for both device-level MOS and standard cells
designs
Automated pin placement positioning user interface
Assigns pins to any edge of placement boundary
Supports ordered and unordered pins
Provides the ability to fix pin positions
Place groups of pins at any given spacing
Multiple pins of the same net
2.2.14 Virtuoso custom router and Chip assembly router
The Virtuoso custom router is a multi-pass, rip-up and re-route, re-entrant router.
The multi-pass aspect of the Virtuoso custom router lets the routing algorithm
21

change variables and focus on different aspects of the design. During each successive pass, the Virtuoso custom router has a new set of parameters and a new
partially routed problem to complete. The rip-up and re-route aspect allows the
Virtuoso custom router to leave violations during a route pass and come back and
try to resolve them in successive passes. The re-entrant aspect lets you stop the
Virtuoso custom router at any point during the autoroute session, make modifications by hand and then start the Virtuoso custom router again.
The Virtuoso custom router lets you set many controls to help achieve a good routing solution. The Router Rule menu is set in order of precedence with the items
at the bottom of the menu having the greatest rule precedence.
Many of the Virtuoso custom router features are targeted for chip assembly, and
may be unnecessary when working at the device-level.
The key to success with the Virtuoso custom router is iteration and experimentation. Many users find that quickly iterating through the design many times will
result in a design close to or better than if the design were routed by hand. If
you get frustrated with the design progress, stop to review the documentation and
analyze your data.
Chip assembly is a design methodology that involves specific routing requirements that fall between the requirements for semi-custom automation and fullcustom, tight control. Using the routing tools, you can meet the requirements
demanded by a chip assembly design for manufacturing, density, design quality,
speed, noise sensitivity, and productivity.
A chip assembly design is generally described as a top-level routing task, where
the physical interconnects are created at the highest physical level. The design
flow can be tuned for chip assembly or for timing driven chip assembly. A variation of these flows might also be used.

2.2.15 Virtuoso Compactor

The Virtuoso Compactor is a symbolic compactor that compacts symbolic objects
as closely as possible to achieve smallest cell size. Compaction is such that design rules are not violated in the final layout. Parameterized cells (pcells) built
with ROD constructs are supported by the compactor. The compactor can handle
designs up to 100k transistors using less than 900MB of memory.

22

2.2.16 Virtuoso Analog VoltageStorm/ElectronStorm

The Virtuoso Analog VoltageStorm Option (VAVO) and the Virtuoso Analog ElectronStorm Option (VAEO) are for power-grid and electromigration (EM) analysis.
VAVO enables you to verify the integrity of your power and ground networks in
analog blocks within the Cadence Analog Design Environment (ADE). VAEO
enables you to find signal nets that could fail electromigration specifications in
analog blocks.

2.2.17 Diva
The Diva verification product is a set of physical verification tools that lets you
find and correct design errors. Using layer processing to prepare data, this set of
verification tools checks physical design and electrical functionality and performs
layout versus schematic comparisons. This tool helps you find errors early in the
design process and lets you view them interactively to help speed error diagnosis
and correction. This product also allows you to perform incremental checks on
areas that you change.
The Diva verification tool set has five interactive products:
Design Rule Checker (iDRC)
Layout Parasitic Extractor (iLPE)
Parasitic Resistance Extractor (iPRE)
Electrical Rules Checker (iERC)
Layout Versus Schematic program (iLVS)
2.2.18 Dracula
Dracula offers a complete set of integrated applications for verifying IC layout
designs.
Design Rules Checker (DRC)
Electrical Rules Checker (ERC)
Layout Versus Schematic (LVS)
Layout Versus Layout (LVL)
Schematic Versus Schematic (SVS)
Layout Parameter Extraction (LPE)
23

 Parasitic Resistance Extraction (PRE)

Pattern Generation (Dracula pattern generation option II)
Plotting
You run the Dracula applications using the preprocessor, PDRACULA. PDRACULA controls execution and most of the file management functions, eliminating
the need for complex job control languages. PDRACULA provides tools for both
the IC process engineer who maintains the design rules and the designer who runs
Dracula and interprets the results.

2.2.19 UltraSim
UltraSimTM is a fast and multi-purpose single engine, hierarchical simulator, designed for the verification of analog, mixed signal, and digital circuits. Covering
a wide range of applications, UltraSim can be used for functional verification
of billion-transistor memory circuits, as well as for high-precision simulation of
complex analog circuits. Because of its true hierarchical simulation approach, UltraSim is faster and uses less memory than traditional circuit simulators, while
maintaining near SPICE accuracy. UltraSim has powerful deep-submicron analysis capabilities, including timing, power, noise, and reliability. UltraSim recognizes a variety of netlist formats, including HSPICE (registered trademark of
Synopsys, Inc.), Spectre, and supports RELXPERT format for reliability simulation.
The main features of UltraSim include
Plus or minus one percent accuracy with respect to SPICE using the most
accurate mode
Ten to more than 10,000 times faster than SPICE
Virtually limitless capacity for hierarchically structured designs [dynamic
random access memory (DRAM), static random access memory (SRAM),
and flash memory]
Outstanding performance with logic and mixed signal circuits [such as multipliers, adders, analog to digital converters (ADC), digital to analog converters (DAC), and phase-locked loops (PLLs)]
Pre-layout and post-layout simulation, with compaction and reduction algorithms for extracted postlayout netlists
Analog and digital simulation modes for analog and mixed signal circuit
simulation
24

 Timing checks for verifying setup, hold, edge, and pulse width checks
Power analysis at the element and subcircuit level
Noise analysis, which monitors voltage overshoot (VO) and voltage undershoot (VU) effects on nodes
Reliability simulation, including hot carrier degradation, negative bias temperature instability, and aged simulation
Fully recognized HSPICE format including analysis cards
Native support for the most popular metal oxide semiconductor field-effect
transistor (MOSFET) models, including BSIM3 and BSIM4
Simulation of silicon-on-insulator (SOI) designs with the partial-depletion
MOSFET (BSIMPD) Berkeley SOI model
Support of the Cadence high-voltage MOS (HVMOS) model for high-voltage
applications, such as Flash and power circuits
Support of Spectre netlist format for transient analysis
Support of all major Spectre device models
UltraSim C-macromodel interface (UCI) for implementing user-specific analog or digital macromodels, such as PLL, memory block, analog to digital
converter (ADC), and digital to analog converter (DAC)
UltraSim reliability interface (URI) for implementing user-specific reliability models
UltraSim waveform interface (UWI) for customizing output of waveform
formats
Recognizes RELXPERT format commands for reliability simulation
Integration into the Cadence analog design environment (ADE)
Support of structural Verilog netlists
Support Verilog A models
Accept digital vector format and VCD format files
Support post-layout RC files
Consult /soft/cadence/usim41/doc/UltraSim User/UltraSim UserTOC.html and
/soft/cadence/usim41/doc/UltraSim tutorial/UltraSim tutorialTOC.html for usage
questions.
25

2.2.20 NeoCircuit
NeoCircuit enables you to size and bias a circuit. The circuit is verified using your
own simulation environment.
Within the NeoCircuit application, you can define performance specifications and
design variables for the circuit, then synthesize your circuit, or simulate a number
of points. Then back-annotate your schematic with the synthesis information.
Neocircuit provides an interface to the following items
Variables
Use the Variables page to set the device relationships and independent variables.
Simulations
In the Simulations page, you specify simulation information and extract
simulation outputs.
Goals
In the Goals page, you can enter computations on the simulation outputs
and set design goals.
Area Calculations
You can use the Areas page to create formulas for computing area for devices.
Corners
You can specify information for corners in the Corners page. The Corners
dialog box enables you to specify parameters to vary for each corner case.
Operating Regions
Use the OpRegions page to define specific expressions that ensure your devices are operating in a desired region (saturation, triode, etc.).
Results
On the Results pane, you can view the results of any synthesis run.
DFM
The DFM page enables you to specify and correlate statistical variables, and
to view the results of Monte Carlo analysis.
Diagnostics
The Diagnostics pane gives information on machine utilization, the average
time for a simulation run, and other runtime information including the total
elapsed time of the synthesis run, the number of points run thus far, the total
number of nodes in use, etc.
26

Consult /soft/cadence/neockt31/tools/NeoCircuit/docs/neocircuit user.pdf for usage questions.

3 Cadence Tools for Analog IC Design

3.1 General
The most frequently used (and well-known among users) tools introduced in chapter 2.2, Tools for Analog and Mixed-mode design, are:
Virtuoso Schematic Composer
Cadence analog design environment(ADE)
Virtuoso layout
In practice, these tools provide access to other tools mentioned in chapter 2.2,
Tools for Analog and Mixed-mode design, excluding programming languages
SKILL and OCEAN. Notice that, all tools are not available for Alcatel 0.35m
technology.
The Command Interpreter Window (CIW) is the first window you see and interact
with using Cadence software. It contains menus with commands that allow you to
do any operation Cadence supports.
Cadence documentation can be invoked by selecting CIW > Help > Cadence Documentation or directly from the shell by typing cdsdoc & after
any Cadence related use function. Notice that, the contents of the documentation
vary depending on set environment. See chapter 3.3, Use Functions, for more
information.
The most important system files and directories used by Virtuoso Schematic Composer, Cadence analog design environment(ADE) and Virtuoso layout are discussed next.

3.2 Getting Familiar with Your Unix files

The key to succesfully run different tools at your Unix machine is to know how
system administrator has planned them to be used. Besides there are many different tools, there are also four (at the moment of writing this document) different
processing technologies that require different environment setups etc. Available
technologies at the University of Turku are:
Alcatel CMOS 0.35m

27

 STMicroelectronics CMOS 0.18m

Documentation index: /tech/stmicro/hcmos8d/ DK hcmos8d 6.1.3/doc/
html/index.html
STMicroelectronics CMOS 0.13m
Documentation index: /tech/stmicro/hcmos9gp 902/
DK hcmos9gp A M6 3V3 HSLL 9.0.2/doc/Manuals/Manuals index.html
STMicroelectronics CMOS 90nm
Documentation index: /tech/stmicro/cmos090 40b1/
DK cmos090gp 7M2T 50A 4.0b1/doc/html/index.html
CMOS 0.35m is used mainly for education and the rest are for research purposes.
Currently support for CMOS 0.18m is only marginal. To get rid of complicated
tool and technology specific start scripts USE functions were introduced for some
time ago. The use functions also facilitate easier use of combinations of various
tools from different vendors.
It is a good practice to create a new directory for each technology before you start
working with any circuit design tool. This helps you to keep your technology
dependent setup files in good order and to avoid conflicts between various technologies. As an example, lets assume that you are planning to use 0.13m CMOS
technology. You can create a new directory for this technology by typing mkdir
<working directory>, e.g. mkdir cadence 013.
Next well examine the most important files and directories related to Cadence
circuit design tools.

3.2.1 .bashrc and .profile

.bashrc and .profile are hidden system files located in your home directory. You
can have one of of these files or both of them in your home folder.
Go to your home directory by typing cd.
Type more .bashrc (or .profile) to list the contents of your .bashrc file. It
should contain at least the following lines:
export LM_LICENSE_FILE=5280@arbiter:1717@mixer:27000@mixer:27000@dct
function use ()
{
. /net/idwt/export/sun/etc/use.sh
}

The contents of .profile and .bashrc files may be identical. The only difference
is that .profile file is processed by a login shell and the .bashrc by an interactive shell. If you dont want this distinction you may e.g. link one to the other
to guarantee that your environment is the same regardless of the shell type this
28

most probably is the case.

The LM LICENSE FILE variable contains information about the location of the
software licenses. More specifically, the variable holds the information about
what machines are the license servers and respectively at what port the license
server listens at on each server. The following list describes what licenses each
port@host part of the variable grants.
5280@arbiter holds the licenses for Cadence tools as well as tools from
Handshake Solutions.
1717@mixer holds the licenses for Mentor tools.
27000@mixer holds the licenses for Synopsys tools.
27000@dct holds the licenses for Matlab and Aplac.
If any Cadence software at any situation reports an error related to license server
or license manager you should first check that your environment has the correct
license setup. You can verify this by issuing e.g. the following command in a
terminal window set | grep LM which should give you the current value
of the LM LICENSE FILE environment variable.
The other important thing is the definition of the use function itself. If use functions do not appear to work as stated in chapter 3.3, Use Functions, check that
the four rows function use (). . . are included in your .bashrc or .profile file. If not,
you can add them. Care is advised when editing these files you may mess up
your environment unless you know what youre doing.

3.3 Use Functions

The use functions were created to help people to invoke applications (including
Cadence tools) with good configurations. The main purpose of each use function
is to set up the environment properly for the application or technology that is about
to be used. Additionally, some use functions also copy some necessary files to the
current directory, when used the very first time. For example:
1) Go to your working directory that you created in chapter 3.2, Getting Familiar with Your Unix files. cd cadence 013
2) Type use hcmos9gp. This sets the environment correctly and asks:
Set-up a work directory at: /<your home directory>/cadence 013 [y/n]?
3) Press y. Text: OK, copying necessary files to /<your home directory>
/cadence 013, done. appears on the screen
29

4) Type ls -a to get a list of the copied files. It should look like this:
.

..

.cdsinit

.simrc

.ucdprod

cds.lib

It is important to note that the use functions are shell-specific. Because of this
there are a few things to consider. Although most use functions can be given
(and in some cases must be given) one after the other, this is not true for all
use functions. For instance, if you have finished working with 0.13m (use hcmos9gp) technology and closed all programs, and then decide to start working
with 90nm technology. Typing use cmos090 from the same shell causes unpredicted behaviour when you start working with icfb, icms etc. This is because
the environment set with use hcmos9gp conflicts with the environment set by use
cmos090. If you notice that, for example, the menus in the Analog Design Environment or some other Cadence tool look weird, the most probable reason is
the situation described above. Therefore, always start with a fresh terminal when
you change technology. Working with two or more technologies in parallel is OK
as long as they are set with different terminals (and your machine can handle the
heavy burden). Typically the use functions are compatible with one another. The
mentioned ST technology specific use functions are the main exception to this
rule.
Typing use without any parameters gives a list of all available use functions.
All tools are not available for all technologies and due to that different set of use
functions must be given to invoke desired tools.
use ic
Tools like icfb, icms can be invoked without technology dependent environment settings and libraries. This can be used e.g. for educational purposes
without NDA problems. Includes rfExamples library that contains several
useful tutorials for simulating rf-circuits.
use alcatel
Sets the environment for Alcatel 0.35m technology. Note that with the
Alcatel technology use ic must also be given as the technology setup itself
doesnt contain any configuration for the actual tools.
use hcmos9gp
Sets the environment for STMicroelectronics 130nm technology
use cmos090
Sets the environment for STMicroelectronics 90nm technology
use icc, use anacad (or use ams), . . .
Can be used with use hcmos9gp and use cmos090 to set the enviroment
30

for optional tools like Virtuoso Custom Router or e.g. Eldo simulator from
Mentor Graphics.
NOTE: For use ic, use hcmos9gp and use cmos090 you must specify the software or the design kit version as well! It is highly recommended to create a new
working directory for the new design kit to avoid confusions between different
versions. (Otherwise, for instance your cds.lib file will be overwritten.) After this
you can add you own libraries to the end of the cds.lib file. See chapter 3.3.4,
cds.lib, for details.
Typing unidoc & after use hcmos9gp or use cmos090 provides access to technology dependent documents for CMOS 0.13m and CMOS 90nm.
The following commands can be given after use ic, use hcmos9gp, use cmos090
to invoke CIW with different set ups.
icde, which includes the schematic editor, symbol editor, and plotting
icds, which includes all of the above, plus digital simulator interfaces
icms, which includes all of the above plus mixed-signal functionality
msfb, which encompasses mixed-signal front-to-back functionality
icfb, which encompasses full-chip design functionality
In practice, icfb (or msfb) is the recommended choice as it guarantees that you
have all tools and features in full force.
3.3.1 .cdsinit
.cdsinit file is for customizing your Cadence tools. It is located in your working
directory. With .cdsinit file, you can for instance
Define specific bind keys for different programs
Set user preference options
Define SKILL procedures etc.
Actually, .cdsinit is often used just to load some specific customization files that
end with .il. For example adding the following lines to .cdsinit file allows you
to use strokes when drawing layout with the Virtuoso.
load(prependInstallPath( "etc/sted/stroke.il"))
load(prependInstallPath( "etc/sted/defstrokes.il"))
hiLoadStrokeFile("def.strokes" "Layout")

31

Programming language in .cdsinit file is Cadence SKILL language. See chapter

3.4, Skill language, for more information.
Hint. To see currently set bind keys for a specific application choose from the
Command Intepreter Window (CIW) Options > Bindkey. . . . Choose desired
application from the pull-down menu and press Show Bind keys-button.
Please read the entire .cdsinit file and the comments before you start customizing
the file. Default .cdsinit file is copied to your working directory when you type for
instance use hcmos9gp for the first time, see chapter 3.3, Use Functions. Type
more .cdsinit to see the contents of your .cdinit file. The hard path for the
referenced <cds install dir> is /soft/cadence/ic5033usr2/tools/dfII/
Remember that settings in the .cdsinit file override settings in the .cdsenv file.
More information about customizing your environment variables can be found at
Cadence help: Cadence Design Framework II User Guide => 4 Setting Cadence
Environment Variables: The .cdsinit File.
If you wish to use Calibre instead of Diva or Assura for checks like design rules
checks (DRC), layout versus schematic (LVS) etc. when you draw layout with
Virtuoso or VirtuosoXL, make sure that the following two lines at the end of
.cdsinit file are uncommented.
load(strcat(getShellEnvVar("MGC_HOME") "/shared/pkgs/icv.ss6/tools/queryskl/cal
ibre.skl"))
mgc_rve_init_socket(9189)

This establishes an interface between Calibre and Virtuoso (adds Calibre menu
in to the Virtuoso). If you get a Calibre error about not being able to initialize
layout server socket. You may need to change the socket number from 9189 to
something else (e.g. 9188). There are two cases when this error is likely to come
up 1) you are running the software on a server where some other user may already
be using the same socket number 2) you are running two technologies in parallel.
3.3.2 .cdsenv
.cdsenv file is to set application environment variables. It is located in your home
directory. If you wish to specify and save new default settings, you can do it directly by manipulating your .cdsenv file or create a new .cdsenv file to your working directory (and thereby create technology dependent default settings). Listing
the contents of your current .cdsenv file (more .cdsenv) gives you a brief overview
what can be done with .cdsenv file. Functions in .cdsenv file are given vith SKILL
language. See chapter 3.4, Skill language, for more information.

32

Direct manipulation of .cdsenv file is equivalent of choosing CIW > Options

> Save Defaults.
Remember that settings in the .cdsinit file override settings in the .cdsenv file.
More information can be found at Cadence help: Cadence Design Framework
II User Guide => 10 Customizing DFII and 11 Saving and Recalling Default
Values.
3.3.3 .artist states
.artist states is for storing the states saved in Analog Design Environment (simulator). The default location is your home directory. To change the default location
choose from Analog Design Environment Session > Options. Edit path given
at row State Save Directory.
WARNING! Saving states with all optional boxes checked can create very
large files in .artist states directory. This is especially true with long transient
Monte- Carlo simulations, so think carefully what you want to save.
3.3.4 cds.lib
cds.lib keeps track of your design libraries. It is located in your working directory.
Default contents of the cds.lib is listed below:
DEFINE
DEFINE
DEFINE
DEFINE

analogLib $CDS_INST_DIR/tools/dfII/etc/cdslib/artist/analogLib
functional $CDS_INST_DIR/tools/dfII/etc/cdslib/artist/functional
basic $CDS_INST_DIR/tools/dfII/etc/cdslib/basic
US_8ths $CDS_INST_DIR/tools/dfII/etc/cdslib/sheets/US_8ths

These files are technology independent, thus same for all technologies. To create
a new library, simply add a new line to cds.lib file. For example:
DEFINE opamps /<working directory>/opamps

and create respective entry to your working directory. In this case

mkdir opamps. This is equivalent of selecting CIW > File > New
> Library. . . . Notice, when creating a new library via CIW, attachment to a
Technology File is requested (, only needed when working with layouts, as stated
in the box). If you create a new library by directly editing the cds.lib file attachment to a Technology File is never requested. However, if you want to establish
this connection, choose CIW > Tools > Technology File Manager and
press Attach-button. Then make appropriate selections.
In some cases you may have an existing library that you want to work with (e.g.
A design made with different technology). You can simply edit your cds.lib file
or use CIW to add the existing library to your system. From CIW, choose Tools
> Library Path Editor. . . . A window saying
33

The file /<working directory>/cds.lib is not edit locked.

pops up. Press OK and choose Edit > Exclusive lock. Now, choose Edit
> Add Library. . . and make selections you wish to make. Before exit, remember to save changes you have made and remove the exclusive lock.
Sometimes your design library may contain a lot of unnecessary cellviews. Deleting a cellview from the library with rm cellview physically removes the cellview, but does not update the list of available cellviews in the CIW. To fix this
choose CIW > File > Defragment Data > Library and make appropriate selections. Finally press OK.
More information can be found at Cadence help: Cadence Application Infrastructure User Guide => 5 Cadence Library Definition File: cds.lib
3.3.5 adsanalogsimulation
adsanalogsimulation stores the data created with Analog Design Environment,
such as netlists, Monte Carlo simulation data and psf data.
Hint. If your simulation results do not appear to be consistent with your schematics, one reason might be that simulation files in your adsanalogsimulation directory are corrupted, defragmented etc. In that case you can try to delete your entire
adsanalogsimulation directory (rm -r adsanalogsimulation) and simulate your design again (new adsanalogsimulation directory is automatically created).
3.3.6 CDS.log
CDS.log keeps track of events happened during your current session. It is located
in your home directory. It is a typical log-file that registers basically everything
you do during your session. If you run multiple parallel sessions simultaneously,
different log files are separated by .x ending (x=1,2,3. . . ) and respective lock
files with the same principle are created. For example, opening two parallel sessions produces the following log- and lock-files:
CDS.log

CDS.log.1

CDS.log.1.cdslck

CDS.log.cdslck

Hint. If your start up phase (e.g. after giving icfb &) takes much longer than
usually, the most probable reason is that the size of your CDS.log file is enormous
for some reason. Due to this, the start up can take up to five minutes. In that
case, delete all CDS.log files (rm CDS.log*). Respective lock files should
be deleted automatically when icfb (or respective) sessions are closed. Function
use ic deletes CDS.log files automatically.

34

Hint. If your icfb or whatever session crashes for some reason it can create a lock
file that prevents e.g. opening schematics in an edit-mode (opens in a read-only
mode). In that case, check if there are any lock files that are responsible for this
kind of behaviour by typing find . -name \*.cdslck. Type find .
-name \*.cdslck |xargs rm to get rid of all suspicious lock files.
3.3.7 display.drf
display.drf (display resource file) defines necessary layout layers for a given technology. A good place to store the display.drf file is your working directory, because all technologies have different one. If you have attached your library to the
correct technology file, see chapter 3.3.4, cds.lib, but display.drf file is missing,
Virtuoso opens with only one visible drawing layer (bkground). To get the layers
correct do the following: Choose CIW > Tools > Display Resource Manager. . . and press Merge. Select appropriate display.drf file From Library,
e.g. cmos090/display.drf and give the path corresponding your working directory
to Destination DRF, e.g. <working directory>/display.drf).
See Cadence help: Technology File and Display Resource File User Guide => 12
Editing, Reusing, and Merging Display Resources for more information.
Hint. By default, the Layer Selection Window (LSW) in Virtuoso contains many
unnecessary layers. To work more efficiently without having to search for a desired layer among all visible layers, do the following: Choose LSW > Edit
> Set Valid Layers. . . . Make your selections and press OK. Then choose LSW
> Edit > Save. . . . Choose either Save To Techfile or File. Techfile saves all
layers listed in the LSW as valid layers in the technology file used for this library.
File saves all layers in the LSW to a file that you can later load with the Edit Load command in the LSW.

3.4 SKILL
As was said in chapter 2.2.5, SKILL language, the applications of the SKILL
language are virtually unlimited. Using SKILL language is a wide-ranging topic
and therefore is not in the scope of this report. Here, only two examples and the
most relevant references are given.
There are many ways to use SKILL. For instance, you can type functions directly
to the command line of CIW or create a script and then load it from the CIW.
Example 1

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If you have difficulties to access the menus that require a double click, do the following:
Type hiGetMultiClickTime( ) to the command line of CIW.
This function returns the number of milliseconds that must elapse before a mouse
click is recognized as a separate single click rather than the second click of a double click.
To set a new value, type hiSetMultiClickTime( x milliseconds ).
The valid range is 50-1000.
Example 2
Sometimes you may want to try what if scenarios like what happens if I replace
high-speed transistors with low-leakage transistors. Of course, you can do it manually or use search and replace form in virtuoso, but here is a script that does the
same thing (for 90nm technology).
Create a file my sch and rep skill.il with the following content, and save it to your
working directory.
schHiReplace( t "master" "==" "cmos090 nlvt symbol" "master" "cmos090 nhvt symbol" )
schHiReplace( t "master" "==" "cmos090 plvt symbol" "master" "cmos090 phvt symbol" )

Type load(my sch and rep skill.il) to the command line of

CIW, and you are done.
See SKILL Language User Guide and SKILL Language Reference Manual to
probe further.

36


Lemminkaisenkatu
14 A, 20520 Turku, Finland | www.tucs.fi

University of Turku
Department of Information Technology
Department of Mathematics

Abo
Akademi University
Department of Computer Science
Institute for Advanced Management Systems Research

Turku School of Economics and Business Administration

Institute of Information Systems Sciences

ISBN 978-952-12-1924-5
ISSN 1239-1891