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Verilog HDL

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Introduction to Verilog

Verilog
Coding Styles
Behavioral C-like constructs
RTL Register Transfer Logic.
Refers to the subset of constructs that is said
to be synthesizable.
Structural Gate instantiations; Netlist
2/1/02

Introduction to Verilog

Sample Verilog Code


Behavioral

RTL

`timescale = 1n/1p
module testbench;
reg clk, reset, enable;
wire [15:0] dout;
counter i1( clk, reset, enable, dout);
initial begin
clk = 0;
forever #20 clk = !clk;
end
always @(dout)
$display (value = %d, dout);
initial begin
reset = 1;
enable = 0;
# 10 reset = 0;
# 100 enable = 1;
repeat(100) @(posedge clk);
$finish;
end

module counter(clk,reset, enable,dout);


input clk, reset, enable;
output [15:0] dout;
reg [15:0] dout;

always @(posedge clk or reset) begin


if (reset)
dout = 0;
else begin
if(enable) begin
dout = dout + 1;
end
end
end
endmodule

endmodule

2/1/02

Introduction to Verilog

Sample Verilog Code


Behavioral

Structural

`tim escale = 1n/1p

module shifter(clk, din, dout);

m odule testbench;

input clk, din;


output [7:0] dout;

reg clk, din;


reg [4:0] cnt;
reg [31:0] pattern;

reg [7:0] dout;

w ire [7:0] dout;


shifter i1( clk, din, do ut);
initial begin
pattern = 32h1055_A2C3;
cnt = 0;
clk = 0;
forever #20 clk = !clk;
#1000 $finish;
end
alw ays @ (do ut)
$display (value = % d, do ut);

dff ff0(.clk(clk), .d(din), .q(dout[0] )


dff ff1(.clk(clk), .d(dout[0]), .q(dout[1] )
dff ff2(.clk(clk), .d(dout[1]), .q(dout[2] )
dff ff3(.clk(clk), .d(dout[2]), .q(dout[3] )
dff ff4(.clk(clk), .d(dout[3]), .q(dout[4] )
dff ff5(.clk(clk), .d(dout[4]), .q(dout[5] )
dff ff6(.clk(clk), .d(dout[5]), .q(dout[6] )
dff ff7(.clk(clk), .d(dout[6]), .q(dout[7] )
endmodule

alw ays @ (posedge clk) begin


din = pattern[cnt];
cnt = cnt + 1;
end
endm odule

2/1/02

Introduction to Verilog

Verilog Simulation
module testbench;
reg clk;

module testbench;
reg clk;

initial
begin
clk = 0;
forever #20 clk = !clk;
end

initial
begin
clk = 0;
forever #20 clk = !clk;
end

// include for non-GUI simulation


initial
begin
$shm_open(testbench.shm);
$shm_probe(AS); //probe all signals
end

// include for non-GUI simulation


initial
begin
$dumpfile(testbench.vcd);
$dumpvars; //probe all signals
end

some_module dut(clk)

some_module dut(clk)

endmodule

endmodule

2/1/02

Introduction to Verilog

Verilog Simulation
verilog testbench.v design.v
or
verilog testbench.v design.v +gui -s

2/1/02

Introduction to Verilog

Verilog Simulation
Libraries

Structural netlists contain instantiations of


component models (cells).
Cell models are generally organized into cell
libraries.
A cell library is usually organized as either a:
1.
2.

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library file one file containing verilog module


descriptions for all cells in the library
library directory a unique file for each module, all
living in the same directory.
Introduction to Verilog

Verilog Simulation
Referencing Cell Libraries
Example 1. Referencing a library directory
Options:
-y <directory name>
+libext+<extensions>+

Species the extensions of files to be used.


Filename must match the module name.

verilog testbench.v design.v y /home/cad/libs/stdcells +libext+.v+

Example 2. Referencing a library file


Options:
-v <filename>
verilog testbench.v design.v v /home/cad/libs/stdcells/stdcells.v

2/1/02

Introduction to Verilog

Verilog Simulation
Library References: The `uselib Directive

The `uselib directive allows the designer to


specify the required reference library
directly in the source code.
Referenced libraries may be redefined as
often as necessary.

2/1/02

Introduction to Verilog

Verilog Simulation
Library References: The `uselib Directive
Syntax:
uselib <LIB_REF>
where LIB_REF includes any of the following:
file=<libfile.v>
dir=<libdir>
libext=<libext>
<empty>
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Verilog Simulation
Library References: The `uselib Directive
Example:
`define BEH_LIB file=/home/cad/custom/cells.vb
module top(portlist.)
// use RTL models
`uselib dir=/home/cad/custom libext=.vr
asic1
asic2
asic3

u1(portlist);
u2(portlist);
u3(portlist);

// RTL model

// use behavioral models


`uselib `BEH_LIB
asic1

u4(portlist); // Behavioral model

endmodule
`uselib
`resetall

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//cancel the current `uselib


//cancel any current compiler directive

Introduction to Verilog

11

Waveform Viewers
Signalscan
Undertow

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Introduction to Verilog

12

Waveform Viewers
Typical capability

Navigate Hierarchy
View selected signals
Group signals
Bundle Signals into buses
Expand buses into bits
Search for events
Save/restore do files

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Introduction to Verilog

13

Waveform Viewers
Demo

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Introduction to Verilog

14

Verilog HDL
Language Basics

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Introduction to Verilog

15

Lexical Conventions
White Space
Verilog is a free format language
White space characters include spaces, tabs,
and carriage returns
Use white space to enhance readability.

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Introduction to Verilog

16

Comments
Single line comments
Begin with // and end with a carriage return
May begin anywhere on the line

Multiple line comments

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Begin with /* and end with */


May begin and end anywhere on the line
Everything in between is commented out
Cannot be nested
Introduction to Verilog

17

Identifiers
Identifiers include module names, variable
names, task names, function names, etc.
Identifiers are case sensitive.
Identifiers must begin with a alphabetical
character (a z , A Z)
Identifiers may contain letters, numbers,
underscores, and dollar signs
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Case Sensitivity
Verilog is case sensitive
Identifiers
Identifiers that differ in case are considered
unique

Keywords
All Verilog keywords are lowercase

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Introduction to Verilog

19

Data Types

Logic Values
Nets, Registers, Vectors
Integer, Real, Time
Arrays
Memories
Parameters
Strings

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Logic Values
Verilog has 4 logic values

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0
1
z or Z
x or X

zero, low, false, not asserted


one, high, true, asserted
high impedance
unknown

Introduction to Verilog

21

Nets
Represent connections between h/w elements
Are continuously driven by device outputs
Do not store data, only propagate it
Keyword: wire
Syntax:
wire datain;
wire [15:0] some_bus;
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Introduction to Verilog

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Registers
Represent data storage elements
Retain their value until updated
Can be declared inside of named blocks
Keyword: reg
Syntax:
reg data_out;
reg [15:0] bus_driver;
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Introduction to Verilog

23

Vectors
Nets and registers can be declared as
vectors having multi-bit widths.
Can be declared as:
[high# : low#] or [low# : high#]
The left-hand value always specifies
the index of the msb
Bit accessible
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Introduction to Verilog

24

Memories
Declared as two-dimensional array of registers.
Syntax:
reg [msb : lsb] <memory name> [first_addr : last_addr];
where:
msb:lsb - specifies the width (word size)
first_addr : last_addr - specifies the depth (address range)

Example:
reg [15:0] my_mem [0:1023] // 1k x 16
reg [7:0] your_mem [0:511] // 512 x 8
Rarely synthesized
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Introduction to Verilog

25

Memories
Memories are word accessible.
A bit or subrange is not directly accessible
May be initialized from a file using system
tasks:
$readmemb
$readmemh

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Introduction to Verilog

26

Memories
$readmemh(<file_name>,
<register_array>,
[<start_addr>,[<end_addr>]])
Open file for reading, and loads the contents into a
register memory array
File must be ASCII with values represented in hex
($readmemh) or binary ($readmemb)
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Numbers
Integer Constants
Syntax:
Width:

widthradix value
optional, defaults to 1

Radix:

optional
D or d :
H or h :
O or o :
B or b :

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Decimal (default)
Hexidecimal
Octal
Binary
Introduction to Verilog

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Numbers
Integer Constants
Examples:
16h A725
5b 11001
7o 155
5d 25

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//16-bit number with hex value A725


// 5-bit number with binary value 11001
// 7-bit number with octal value 155
// 5-bit number with decimal value 25

Introduction to Verilog

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Numbers
Real Constants
Decimal Notation
Scientific Notation
Examples:
Y = 105.6
Y = 1.2e-6

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Numbers
Parameters
Defined inside a module
Local scope
May be overridden at instantiation time
If multiple parameters are defined, they must be
overridden in the order they were defined. If an
overriding value is not specified, the default parameter
declaration values are used.

May be changed using the defparam


statement
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Numbers
Parameters Using Defparam
module secret_number;
parameter my_secret_number = 0;
initial
$display(Hello World, my secret number is %d, my_secret_number);
endmodule
--------------------------------------------------------------------------------------------module top;
defparam inst1.my_secret_number = 37,
inst2.my_secret_number = 16;
secret_number inst1();
secret_number inst2();
endmodule

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Numbers
Parameter Overriding Values
module secret_number;
parameter my_secret_number = 0;
initial
$display(Hello World, my secret number is %d, my_secret_number);
endmodule
--------------------------------------------------------------------------------------module top;
secret_number #(37) inst1();
secret_number #(16) inst2();
endmodule

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Numbers
Parameter Overriding Values
module secret_numbers;
parameter sn1 = 0;
parameter sn2 = 0;
parameter sn3 = 0;
initial
$display(Hello World, my secret numbers are %d %d %d, sn1, sn2, sn3);
endmodule
-----------------------------------------------------------------------------------------------module top;
secret_number #(37, 54, 23) inst1();
secret_number #(16, 20) inst2();

// sn1 = 37, sn2 = 54, sn3 = 23


// sn1 = 16, sn2 = 20, sn3 = 0 (default)

endmodule
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Introduction to Verilog

34

Compiler Directives
`define
Specifies an alias that is resolved at compile time.
References to the alias are preceded with a ` (back
tick). These are commonly used as state names in
state machines
Example:
`define DATA_STATE 4h2
if (state == `DATA_STATE)
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Compiler Directives
`include
Used to include the contents of one source file
inside another. The included file is expanded at
compile time.
Example:
`include header.v
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Design Methodology
Top Down
Bottom up
Both partition the design hierarchically.
Each functional block (and sub-block) is
described as a module in Verilog. A module
is the fundamental building block in
Verilog.
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bottom up

top down

Design Methodology

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DUTs and Testbenches


DUT - Device Under Test
Generally coded in an RTL style

Testbench
Generates stimulus
Checks response

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DUTs and Testbenches


Testbench

Stimulus
Generator

DUT

Checker

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Modules
A module is the fundamental building block
in Verilog.
Modules are declared by the keywords
module and endmodule

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Modules
Example:
module <module name> [ ( <port list> ) ];
...
functional description
...
endmodule
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Ports
The port list defines the order of the ports.
The port list does NOT specify the type of
the port (input, output, or inout), nor the
width of the port.
Port properties are specified inside the
module using the keywords input, output,
and inout.
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Ports
module D_FF(clk, reset, d, q);
input clk, reset;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
always @(posedge reset or posedge clk)
if (reset)
q <= 8'h00;
else
q <= d;
endmodule
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Instances
Lower level modules are assembled into
higher level modules by way of
instantiation.
Interconnect is implemented either by order
or by name.

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Instances
module pipe(clk, reset, x, y);
input clk, reset;
input x;
output y;
// connect by order
DFF
DFF
DFF
DFF

i0(clk, reset, x, d[0]);


i1(clk, reset, d[0], d[1]);
i2(clk, reset, d[1], d[2]);
i3(clk, reset, d[2], y);

endmodule

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Instances
module pipe(clk, reset, x, y);
input clk, reset;
input x;
output y;
// connect by name
DFF
DFF
DFF
DFF

i0(.clk(clk), .reset(reset), .d(x), .q(d[0]));


i1(.clk(clk), .reset(reset), .d(d[0]), .q(d[1]));
i2(.clk(clk), .reset(reset), .d(d[1]), .q(d[2]));
i3(.clk(clk), .reset(reset), .d(d[2]), .q(y));

endmodule

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Dataflow Modeling
RTL
Continuous Assignment
Operators

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Arithmetic, Logical
Bitwise, Reduction
Relational, Equality, Conditional
Shift
Concatenation, Replication
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48

Dataflow Modeling

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assign

Specified outside of a procedural block


The most fundamental construct used to describe
combinational logic at the RTL level.

Examples
assign q = (a & b ) | c;
assign q = s ? d1 : d0;

Introduction to Verilog

49

Dataflow Modeling
Arithmetic Operators
Binary

Multiply
Divide
Add
Subtract
Modulus

*
/
+
%

Unary
Positive
Negative
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+
Introduction to Verilog

50

Dataflow Modeling
Arithmetic Operators
Examples
A = 4b0011; B = 4b0010;
Y = A * B;
Y = A / B;
Y = A + B;
Y = A - B;

//
//
//
//

Y -> 4b1100
Y -> 4b0000
Y -> 4b0101
Y -> 4b0010

Note: If any operand contains a bit value of


x, then the expression evaluates to x

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Dataflow Modeling
Arithmetic Operators
Examples
16 % 5
16 % 4
-16 % 5
16 % -5

-> 1
-> 0
-> -1
-> 1

Note: Modulus takes the sign of the first operand


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Dataflow Modeling
Logical Operators
Evaluates to 1-bit value
Operands equal to zero are FALSE, all
others are TRUE
Operators
Logical-and &&
Logical-or ||
Logical-not !
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53

Dataflow Modeling
Relational Operators
Evalutes to TRUE or FALSE
Evaluates to x if any operand bits are x or z
Operators

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greater-than
less-than
greater-than-or-equal-to
less-than-or-equal-to

>
<
>=
<=

Introduction to Verilog

54

Dataflow Modeling
Equality Operators
Evalutes to TRUE or FALSE
Operators

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Logical equality
Logical inequality
Case equality
Case inequality

==
!=
===
!==

Introduction to Verilog

55

Dataflow Modeling
Equality Operators
Expression Description

EvaluationValues

a == b

a equal to b, result
unknown if x or z in a or b

0, 1, x

a != b

a not equal to b, result


unknown if x or z in a or b

0, 1, x

a === b

a equal to b, including x
and z

0, 1

a !== b

a not equal to b, including x


and z

0, 1

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Dataflow Modeling
Bitwise Operators
Performs bit-by-bit operation on two n-bit
operands, yielding an n-bit result
If operands have differing lengths, the shorter one
is zero extended first
Operators

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negation
and
or
xor
xnor

~
&
|
^
~^ , ^~
Introduction to Verilog

57

Bitwise Operators
Examples:
a = 4b0001;
b = 4b1001;
y = a & b;
y = a | b;
y = a ^ b;
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// y -> 4b0001
// y -> 4b1001
// y -> 4b1000
Introduction to Verilog

58

Dataflow Modeling
Reduction Operators
Performs operation on all bits of a single
operand, yielding an 1-bit result
Operators

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negation
and
or
xor
xnor

~
&
|
^
~^ , ^~
Introduction to Verilog

59

Reduction Operators
Examples:
x = 4b0001;
y = &x;
y = |x;
y = ^x;
2/1/02

// y -> 1b0
// y -> 1b1
// y -> 1b1
Introduction to Verilog

60

Dataflow Modeling
Shift Operators
Shifts a vector left or right by a specified
number of bits.
Zero fill
No wrap around
Operators
Right Shift
Left Shift
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>>
<<
Introduction to Verilog

61

Shift Operator
Examples:
// X = 4b1100
Y = X >> 1 // Y -> 4b0110
Y = X << 1 // Y -> 4b1000
Y = X << 2 // Y -> 4b0000

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Dataflow Modeling
Concatenation Operator
Appends multiple operands
Provides mechanism to bundle separate
signals and vectors into a single vector
Operator:
Operands:

{,}

nets, registers, scalars, vectors, bit-select, partselect, or sized constants


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Dataflow Modeling
Concatenation Operator
Example:
// A = 1b1, B = 2b01, C = 4b1100
Y = {A , B}
Y = {A , C[2:1] , 1b11}
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=>
=>

Introduction to Verilog

3b101
5b11011
64

Dataflow Modeling
Replication Operator
Provides a mechanism to perform repetitive
concatenation.
Example:
// A = 1b1 B = 2b01 C = 3b101
Y = 4{A}
=> 4b1111
Y = 2{A , B}
=> 6b101101
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65

Dataflow Modeling
Conditional Operator
Usage:
condition_expr ? true_expr : false_expr
Behaves like a 2-to-1 mux or an if-else
expression.
Example:
assign out = control ? in_1 : in_0
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Dataflow Modeling
Operator Precedence

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Operator

Symbols

Precedence

Unary
Multiply, Divide, Modulus

+ - ! ~
* / %

highest

Add, Subtract
Shift

+ << >>

Relational
Equality

< <= > >=


== != === !===

Reduction

& ~&
^ ^~
| ~|
Introduction to Verilog

67

Dataflow Modeling
Operator Precedence

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Operator

Symbols

Logical

&&
||

Conditional

?:

Precedence

lowest

Introduction to Verilog

68

Dataflow Modeling
Perform Labs

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Behavioral Modeling

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Behavioral Modeling
Structured Procedures
Initial Blocks
Executed exactly one time

Always Blocks
Loop continuously for the duration of the simulation

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71

Behavioral Modeling
Procedural Assignment
Types
Blocking assignment
Non-blocking assignment

LHS must be a register type


RHS may be any valid expression or signal

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Behavioral Modeling
Blocking Assignment
Executed in the order they appear in a
procedural block

Example:
b = a;
a = x;
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73

Blocking Assignments
initial
begin

Event Queues

Execution
Order

a = b;
c = d;
e = f;

a <- b(t)
c <- d(t)
e <- f(t)

end

Evaluate RHS expression


Schedule assignment
Block flow until assignment is
executed

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t+1

t+2

t+3

Time

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Behavioral Modeling
Non-blocking assignment
Implements concurrency in a procedural block.
Schedules the assignment without blocking execution
of subsequent statements in a procedural block
Executes at the end of the time step
Order of execution is indeterminate
Example:
x <= a;
y <= x ;
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Non-blocking Assignments
initial
begin

Event Queues
a <= b;

Evaluate RHS expression


Schedule assignment at bottom of
queue
Continue flow
Make assignment at end of time
step

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Execution
Order

end

a <- b(t)

Introduction to Verilog

t+1

t+2

t+3

Time

76

Timing Controls
Delay-Based Timing Control
Event-Based Timing Control
Level Sensitive Timing Control

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Delay-Based Timing Control


Specifies the wait time between when a
statement is encountered, and when it is
executed
Regular delays
Intra-assignment delays
Zero delays
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Regular Delay Control


Delayed Blocking Assignments
initial
begin

Event Queues
#1 a = b;

a <- b(t+1)

Delay evaluation of RHS as


specified by the timing control
Evaluate RHS expression
Schedule assignment
Block flow until assignment is
executed

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Execution
Order

end

Introduction to Verilog

t+1

t+2

t+3

Time

79

Regular Delay Control


Delayed Blocking Assignments
initial
begin

Equivalent

initial
begin

#1 a = b;
#1 c = d;
#1 e = f;

#1
a = b;
#1
c = d;
#1
e = f;

end

end

Note: LHS delays accumulate


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Regular Delay Control


Delayed Blocking Assignments
initial
begin

Event Queues
a <- b(t+1)

c <- d(t+2)

e <- f(t+3)

t+1

t+2

t+3

Execution
Order

#1 a = b;
#1 c = d;
#1 e = f;
end

Time

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Blocking Intra-procedural
Delayed Assignment
initial
begin

Event Queues
a = #1 b;

a <- b(t)

Evaluate RHS expression


Schedule the assignment at the end
of the queue specified by the
timing control
Block flow until assignment is
executed
Useless construct

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Execution
Order

end

Introduction to Verilog

t+1

t+2

t+3

Time

82

Regular Delay Control


Delayed Non-Blocking
Assignments
initial
begin

Event Queues

#1 a <= b;

Delay evaluation of RHS


expression as specified by the
timing control
Evaluate RHS expression
Continue flow
Make assignment at end of time
step

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Execution
Order

end

a <- b(t+1)

Introduction to Verilog

t+1

t+2

t+3

Time
83

Non-blocking
Intra-procedural
Delayed Assignment
initial
begin

Event Queues
a <= #1 b;

Evaluate RHS expression


Schedule the assignment at the end
of the queue specified by the
timing control
Continue flow
Make the assignment at the end of
the time step

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Execution
Order

end

a <- b(t)

Introduction to Verilog

t+1

t+2

t+3

Time

84

Non-blocking
Intra-procedural
Delayed Assignment
initial
begin

Event Queues

end

Execution
Order

a <= #1 b;
c <= #1 d;
e <= #1 f;
a <- b(t)
c <- d(t)
e <- f(t)

Note: RHS delays dont


accumulate
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t+1

t+2

t+3

Time

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85

Event-Based Timing Control


Regular Event Control
Event OR Control
Named Event Control

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86

Regular Event Control


Specified with @ symbol
Executes statement group when a signal
value changes.
posedge keyword
negedge keyword

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87

Regular Event Control


Examples
@(clk) q <= d;
@(posedge clk) q <= d;
@(negedge clk) q <= d;
@(posedge clk or posedge reset)
begin

end
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Named Event Control


Declare event with keyword event
Trigger event with the -> symbol
Recognize event with @ symbol

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89

Named Event Control


Example
event send_data;
always @(posedge req) begin
if (ready)
->send_data
end
always @(send_data) begin

end
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Level-Sensitive Timing Control


Keyword: wait
Blocks execution of subsequent statement
until wait condition is TRUE

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91

Level-Sensitive Timing Control


Example
initial
begin
clk = 1b0;
wait (clk_enable)
forever #20 clk = ~clk;
end

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Rules of Thumb
1. Use blocking assignments without delays
for combinational always blocks.
2. Use non-blocking assignments exclusively
for sequential always.

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93

QUIZ
always @(posedge clk)
a = b;
always @(posedge clk)
b = a;

always @(posedge clk)


begin
a = b;
b = a;
end

Assume a =1 and b =2.


What are the values of a and b
after the first rising edge of clk?

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Assume a =1 and b =2.


What are the values of a and b
after the first rising edge of clk?

Introduction to Verilog

94

QUIZ
always @(posedge clk)
a <= b;
always @(posedge clk)
b <= a;

always @(posedge clk)


begin
a <= b;
b <= a;
end

Assume a =1 and b =2.


What are the values of a and b
after the first rising edge of clk?

2/1/02

Assume a =1 and b =2.


What are the values of a and b
after the first rising edge of clk?

Introduction to Verilog

95

Programming Statements
Branching
if
if - else
case, casex, casez

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Iteration

Introduction to Verilog

repeat
forever
while
for

96

if
if (cond_expr)
statement or
statement_group

yes

cond_expr
TRUE?

no

Statement

Example:
if (enable)
dout = din;

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or group

Introduction to Verilog

97

if - else
if (cond_expr)
statement or
statement_group
else
statement or
statement_group

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yes

cond_expr
TRUE?

no

Statement

Statement

or group

or group

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98

case
case (<reg or net>)
cond_1: statement or
group
cond_2,
cond_3: statement or
group
default: statement or
group
endcase

cond_1

yes

no

cond_2

yes

no

cond_3

yes

no

default

yes

no

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99

casez
Considers all occurrences of z in the case
expression or case alternatives to be dont
cares.
Compares only non-z positions in thecase
expression and case alternatives

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100

casex
Considers all occurrences x and z in the
case expression or case alternatives to be
dont cares.
Compares only non-x or -z positions in the
case expression and case alternatives

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101

while
while (while_expr)
statement or
statement group
Repetitively executes
the statement group
as long as the
while_expr is TRUE.
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while_expr
TRUE?

Introduction to Verilog

yes

no

102

repeat
Repeat (<number of times>)
statement or
statement_group
Repetitively executes the statement_group a
fixed number of times
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repeat
Example
//Hold reset high for 20 clock periods
initial
begin
reset = 1b1;
repeat (20) @(posedge clk);
reset = 1b0;
end

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104

forever
forever
statement or
statement_group
Repetitively executes the statement group
until the simulation is terminated with the
$finish system task.
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105

forever
Example
//Generate a clock with period of 10
initial
begin
clk = 1b0;
forever #5 clk = ~clk;
end
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106

for
for (initial_assignment;
cont_expr;
step_assignment)
statement or
statement_group

initial
assignment
cont_expr
TRUE?

no

exit

yes
statement
group

step
assignment

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for
Example
//intialize RAM with checkerboard pattern
initial
begin
for(addr = 0; addr < 32;addr = addr + 2)
ram[addr] = 8h55;
for(addr = 1; addr < 32;addr = addr + 2)
ram[addr] = 8hAA;
end
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108

Statement Groups
Sequential Blocks
begin
end

Parallel Block
fork
Join

Name Blocks
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109

Statement Groups
Sequential Blocks
Statements are processed in the order they are
specified
Any delay is relative to the time the previous
staement completed

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110

Sequential Block
Example
initial
begin
x = 1b1;
y = 1b0;
z = 4hf
end
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111

Statement Groups
Parallel Blocks
Statement are executed concurrently
Order does not matter
Any delay is relative to the time the block was
entered
Suseptable to race conditions. Why?

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112

Parallel Block
Example
initial
fork
x = 4h5;
y = 4h5;
z = x + y;
end
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fork

X=4h5 Y=4h5

y=x+y

join

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113

Named Blocks
Allow variables variables
to be declared local to the
clock
Are part of the design
hierarchy.
Local variables can be
accessed with hierarchical
name referencing.
Can be disabled

2/1/02

initial
begin : block1
reg x;
x = 1;
end
initial
fork : block2
reg x, y;
#10 x = 1;
#20 y = 1;
join

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114

Nested Blocks
initial
begin
clk_1 = 0; clk_2 = 0; clk_3 = 0;
fork
forever #10 clk_1 = ~clk_1;
forever #20 clk_2 = ~clk_2;
forever #30 clk_3 = ~clk_3;
join
end
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Tasks and Functions


Tasks
Defined by keywords: task and endtask
Must be used if any of the following
conditions are true for the procedure:
There are delay, timing, or event constructs
in the procedure
The procedure has zero or more than one out
arguments
The procedure has no input arguments
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Tasks and Functions


Tasks (continued)
Can invoke other tasks and functions
Interface is specified using to the keywords
input, output, and inout
Although registers defined within the task have
local scope, the task my directly access any
register defined in the calling module

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Tasks
Syntax:
task <task name>;
[<tf_declarations>]
[<statement group]
end task

tf_declaration

Invocation:
<task name>
<task name>(arg1, arg2, )
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parameter
input, output, inout
reg
integer, real
time
event

118

Tasks and Functions


Functions
Defined by keywords: function and
endfunction
Use if all the following conditions are true for
the procedure
There are no delay, timing, or event control
constructs in the procedure
The procedure returns exactly one value
Requires at least one input argument

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119

Tasks and Functions


Functions (continued)
May call other functions
May not call other tasks

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120

Functions
tf_declaration

Syntax:

function [<type_range>] <func_name>


<tf_declarations>
<statement or group>
endfunction

type_range

Invocation:
<func_name> (arg1, arg2, );

2/1/02

input (one required)


parameter
reg
integer, real
time

Introduction to Verilog

range
integer
real
121

Tasks and Functions


module mod1;
reg clk;
initial
begin
clk = 0;
forever gen_asym_clk;
end
task gen_asym_clk;
begin
#3 clk = ~clk;
#4 clk = ~clk;
#10 clk = ~clk;
end
endtask
endmodule

2/1/02

module mod2;
reg [3:0] x;
reg [7:0] y;
initial
begin
x = 4d10;
y = square(x);
$display(%d squared is %d,x,y);
End
function [7:0] square;
input [3:0] x;
begin
square = x * x;
end
endfunction
endmodule
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122

Finite State Machines


Mealy Model
Outputs a function of current state and inputs

Moore Model
Outputs a function of current state only

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Finite State Machine


Mealy Model
Output
Logic
Next State
Logic

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State
Registers

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124

Finite State Machine


Moore Model

Next State
Logic

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State
Registers

Introduction to Verilog

Output
Logic

125

Finite State Machines


Coding Guidelines
Place sequential and combinational functional
blocks into separate procedural blocks
Latch the outputs to prevent glitches

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