module halfadder(carry,sum,A,B);

input A,B;
output carry, sum;
and g1(carry,A,B);
xor g2(sum,A,B);
endmodule
module testbench_halfadder();
reg A,B;
wire carry,sum;
halfadder ha1(carry,sum,A,B);
initial
begin
A=0; B=0;
#20 A=0; B=1;
#20 A=1; B=0;
#20 A=1; B=1;
end
endmodule
module twotwovedic(Q,A,B);
input [1:0]A;
input [1:0]B;
output [3:0]Q;
wire [3:0]w;
and g1(Q[0],A[0],B[0]);
and g2(w[0],A[1],B[0]);
and g3(w[1],A[0],B[1]);
and g4(w[3],A[1],B[1]);
halfadder ha1(w[2],Q[1],w[0],w[1]);
halfadder ha2(Q[3],Q[2],w[2],w[3]);
endmodule
module testbench_twotwovedic();
reg [1:0]A;
reg [1:0]B;
wire [3:0]Q;
twotwovedic vedic(Q,A,B);
initial
begin
A=2'b10; B=2'b11;
end
endmodule
module fulladder(carry,sum,A,B,C);
input A,B,C;
output carry,sum;
wire w1,w2,w3;
halfadder ha1(w2,w1,A,B);
halfadder ha2(w3,sum,w1,C);
or g5(carry,w2,w3);
endmodule
module fourbit(cout,sum,A,B,cin);
input[3:0]A,B;
input cin;
output [3:0]sum;

output cout;
wire c1,c2,c3;
fulladder fa1(c1,sum[0],A[0],B[0],cin);
fulladder fa2(c2,sum[1],A[1],B[1],c1);
fulladder fa3(c3,sum[2],A[2],B[2],c2);
fulladder fa4(cout,sum[3],A[3],B[3],c3);
endmodule
module testbench_fourbit();
reg [3:0]A,B;
reg cin;
wire [3:0]sum;
wire cout;
fourbit four(cout,sum,A,B,cin);
initial
begin
A=4'b0101; B=4'b1010; cin=0;
end
endmodule