Lab Report: EEE 454

Department of EEE

Lab Report: EEE454

VLSI I

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Group No: 01

Lab Number: 04

LAB TITLE: Layout design with Cadence Virtuoso Layout Suite L

Editor

Prepared By:
Student Name: Anupam Golder
Student ID: 0906004
Name of Group Member: Anik Saha
Student ID of Group Member: 0906001
Date of Experiment: 23/08/2014
Date of Report: 30/08/2014

Lab Report: EEE 454

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ABSTRACT
In this experiment, Cadence Virtuoso Layout Suite L has been used to build the layout view of a
CMOS Inverter with the constraint that it should be of minimum possible size. Then using
Cadence ASSURA the DRC rules have been checked for design errors and using ASSURA LVS
check, layout has been matched with the schematic. The process technology adopted for this
experiment is gpdk090 which is a 90nm technology. The purpose of this experiment was to get
acquainted with the design rules that come into action when minimum size devices are to be
designed.

KEYWORDS

Virtuoso
ASSURA
Inverter
Layout

DRC
LVS

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TABLE OF CONTENTS
Page
Abstract...2
Keywords.2
Table of Contents....3
List of Figures.....4
List of Tables...4
1. Introduction.....5
2. Theory.5
3. Lab Handout Question ...8
4. Tools Used...8
5. Procedure 8
6. Results ....8
6.1 Layout of the inverter......8
6.2 Errors Received...................9
6.3 List of rules....10
6.4 List of some good practices.......10
6.5 Fabrication Sequence of the CMOS Inverter.11
6.6 LVS Check ...13

7.Conclusion13
8.References. 13

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LIST OF FIGURES

VLSI Design Flow

CMOS Inverter Schematic
CMOS Inverter Layout
Basic DRC Rules
Layout of CMOS Inverter
Measurement of the area of the inverter
Error Layer Window (ELW)
DRC Check
Fabrication sequence of CMOS Inverter
LVS Check

Page
5
6
6
7
8
9
9
10
11-13
13

LIST OF TABLES

Explanation and meanings of Errors

9-10

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INTRODUCTION
In this experiment, a layout of a CMOS inverter has been designed in Cadence Virtuoso Layout Suite L.
The design rules have specifications for minimum width, area, separations, enclosure, butting and overlapping.
To ensure the minimum possible area for the inverter layout all the rules have been carefully checked and
followed. The rules were specified for gpdk090 technology.

After the DRC check has been performed, several DRC errors have been found which have been corrected.

Then LVS check has been performed which ensured that the layout and the schematic of the inverter
matched. Several issues have been encountered like mismatched pins and nets which have been corrected.

This experiment can help demonstrate how design rules come into play when minimum sized devices are to
be designed and the reason behind following the rules which is related to the accuracy of the fabrication process
for the specified technology.

THEORY
VLSI Design Process
The VLSI design process goes through the following steps:

Fig No. 1: VLSI Design Flow

Layout Design
Integrated circuit layout is the representation of an integrated circuit in terms of planar geometric shapes which
correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated
circuit [1].
When using a standard process the behavior of the final integrated circuit depends largely on the positions and
interconnections of the geometric shapes. While designing a layout all the components that make up a chip are
placed and connected so that they meet performance and size criterion. The generated layout must pass a series of
checks in a process known as physical verification. The most common checks in this verification process are:

design rule checking (DRC),

layout versus schematic (LVS),
parasitic extraction,
antenna rule checking
Electrical rule checking (ERC) etc.

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CMOS Inverter:
The CMOS inverter consists of a PMOS and an NMOS transistor. They must be properly shaped to account for the
fact that holes have lower mobility than electrons. So the PMOS transistor generally has a larger size and to reduce
the undesirable effects due to larger size, twice the no. of contacts in NMOS are placed in the PMOS.

Fig No. 2: CMOS Inverter Schematic

Fig No. 3: CMOS Inverter Layout

Layout Design Rules

Layout design is performed maintaining some basic rules of dimension and relative positions of various layers
representing oxide, n-well, poly-silicon, and substrate, metal1 and doped regions (Nimp or Pimp). An inverter
consists of a NMOS and a PMOS transistor. According to the gpdk90nm Mixed Signal Process Specifications, the
primary design rules of NMOS and PMOS transistors are as follows:
As seen from the layout diagram the NMOS inverter consists of oxide, Nimp, Cont and poly layers.
NMOS Transistor Design Rules
Contact size: 0.12m x 0.12m (Fixed)
Poly width Minimum: 0.1m (Fixed MOS gate length)
Contact to poly spacing (Minimum): 0.1m
Contact to oxide spacing (Minimum): 0.06m
Poly extending to oxide (Minimum): 0.18m
Nimp overlapping oxide (Minimum): 0.18m
Minimum Metal 1 width: 0.12m
Maximum Metal 1 width: 12.0m
Minimum Metal 1 to Contact enclosure: 0.06m
The PMOS transistor consists of Oxide, Poly, Pimp, Cont and Nwell layer.

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PMOS Transistor Design Rules

Minimum Nwell width: 0.6m
Minimum Nwell spacing to Nwell (same potential): 0.6m
Minimum Nwell spacing to Nwell (different potential): 1.2m
Minimum Nwell spacing to N+ active area: 0.3m
Minimum Nwell spacing to P+ active area: 0.3m
Minimum Nwell enclosure to P+ active area: 0.12m
Minimum Nwell enclosure to N+ active area: 0.12m
Minimum N+ active Area to P+ active Area Spacing: 0.15m
Minimum Contact to Contact spacing

0.14m

Design Rule Check (DRC)

Design Rule Checking (DRC) is the process that determines whether the physical layout of a particular chip satisfies
a series of recommended parameters called Design Rules. Design rule checking also involves LVS (Layout versus
schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks etc [2].
Design Rules are a series of parameters provided by semiconductor manufacturers which are specific to a particular
semiconductor manufacturing process. Design rules specify certain geometric and connectivity restrictions to ensure
that the process can fabricate the device properly. The most basic design rules for one layer are: width, spacing and
enclosure.

Fig No. 4: Basic DRC Rule

Layout versus Schematic (LVS) Check
The Layout Versus Schematic (LVS) is the class of verification that determines whether a particular integrated
circuit layout corresponds to the original schematic or circuit diagram of the design. A successful Design rule
check (DRC) ensures that the layout conforms to the rules designed/required for faultless fabrication. However, it
does not guarantee if it really represents the circuit we desire to fabricate. This is where an LVS check is used.
LVS Checking involves following three steps:
1. Extraction: The software program takes a database file containing all the layers drawn to represent the
circuit during layout. It then runs the database through many area based logic operations to determine the
semiconductor components represented in the drawing by their layers of construction.
2. Reduction: During reduction the software combines the extracted components into series and parallel
combinations if possible and generates a netlist representation of the layout database.
3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic.If
the two netlists match, then the circuit passes the LVS check.
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LAB HANDOUT QUESTIONS

There was no lab handout questions.

TOOLS USED
1. Cadence Virtuoso Layout Suite L
2. Cadence ASSURA DRC
3. Cadence ASSURA LVS

PROCEDURE

Cadence Virtuoso Layout Suite L. has been launched.

Appropriate lengths for device dimensions have been calculated from design rules to meet
the minimum area criterion.
All 6 layers of CMOS nwell process for gpdk090 technology has been drawn in the layout.
The contacts have been drawn first and then the metal1 surrounding them, then the oxide
layer, nimp, pimp, poly,nwell etc. Lengths have been checked by the tool ruler and the
snapping has been fixed as mentioned in the lab sheet.
Then ASSURA DRC has been launched and used to check the design.
From the Error Layout Window, the regions have been detected where design rules have
been violated. Then errors have been corrected.
When there have been no more DRC errors, ASSURA LVS has been launched and the
errors due to mismatched layout and schematic have been found out and corrected.

RESULTS
1. Layout of the CMOS inverter as designed:

Fig. No. 5. Layout of CMOS Inverter

In the above figure,
Poly pink, Metal1- yellow, Nwell green, Cont black, pimp light blue, nimp blue

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Size of the Inverter:

The area of the inverter has been found to be 2.0 um x 2.1 um

Fig. No. 6 Measurement of area of the inverter

This might be the achievable minimum size for the inverter which meets the requirements as specified.
2. Errors Received:
We had to run DRC for several times and some errors have been observed in he layout which have been
corrected before another run. Errors from different runs have been combined in the following figure:

Fig. No. 7 Error Layer Window(ELW)

Meanings of the errors:
The explanations of the errors are given below in the order they appeared in ELW.
Error
No
1
2 and 3
4

Explanations and meanings of Errors

We have created too small a well to connect the nwell (n-sub) to VDD and there were no connection
between the nwell for PMOS and the nwell for connection to VDD which generates this error.
Active n-regions (nimp) and p-regions (pimp) must have an area greater than 0.15 . We have used
a smaller well for the contact of p-sub to GND and nwell to VDD.
Contact must be covered by oxide or poly. Contacts are for connected metal layer to poly layer or for
nimp or pimp to metal layer. In case of nimp or pimp, contact must be covered by oxide.
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This might be due to the error in drawing which led to the p-sub or nwell being not connected to proper
connections (GND or VDD).

6
7

Oxide must be covered by nimp or pimp or nzvt.

Minimum oxide to poly enclosure must be 0.2 m

8
9
10
11
12
13

Poly gates cannot have bends. We have to use path to connect poly gates to input or output pin.
Minimum contact to gate spacing must be 0.1 um. This occurred due to error 8.
Minimum poly to contact enclosure must be 0.04um.
Poly to contact enclosure on at least two opposite sides must be greater than 0.06 um.
Contact on gate is not allowed. It occurred due to error 8.
Metal area smaller than .07
are not allowed.
Table No. 1 Meanings of the errors

After all the errors have been corrected, DRC check yielded the following window:

Fig. No. 8 DRC Check

3. List of rules relevant to the design of CMOS inverter in addition to the rules mentioned in the theory
section:
1. Metal area smaller than .07
are not allowed.
2. Contact on gate is not allowed.
3. Minimum poly to contact enclosure must be 0.04um. Poly to contact enclosure on at least two opposite sides must
be greater than 0.06 um.
4. Poly gates cannot have bends
5. Contact must be covered by oxide or poly.
6. Nimp or Pimp must have an area greater than 0.15 .
7. Oxide area must be greater than 0.06 .
4. List of some good practices for Inverter layout design:
1. It is better to start with the smallest of the layers which is generally the contact layer. It has the smallest
dimension. Then metal1 can be drawn around it. Then it can be copied and used for the second contact in
the nimp region by maintain minimum poly to contact spacing and ploy width (for gate), Then the oxide
layer and so on.
2. The intersection of an active region and poly region defines the channel of a transistor. So width of the poly
should be chosen accordingly.
3. Metal1 layer does not have any specifications other than minimum width or maximum width and contact to
metal1 enclosure, so after the enclosure has been ensured, metal1 can be routed easily.
4. It is better to calculate all the dimensions beforehand which will save design time.
5. Oxide areas define active regions. So oxide must be used for nimp or pimp.
6. Nwell is connected to VDD using nimp and p-substrate is connected to GND using pimp. But these two
connections are net connections. So only the net names should be changed.
7. For inputs and outputs, pins must be used.
8. Poly and metal1 are two different layers. So, to connect them, use of contacts is a must.
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5. Fabrication sequence of the CMOS inverter with masks and cross-section: (From Q & A section)
Start: For an n-well process, the starting point is p-type silicon wafer.
Epitaxial growth: A single p-type single crystal film is grown on the surface of the wafer by oxidation.
D ia m e te r = 7 5 to 2 3 0 m m

p -e p ita xia l la ye r

< 1m m

P + -typ e w a fe r

N-well formation: formation of nwell for PMOS transistor fabrication.

P h ysica l stru ctu re cro ss se ctio n

M ask (to p view )

n-w e ll m a sk

La tera l
diffu sio n

n -w ell
p-typ e ep ita xial la ye r

Active area definition: A thin layer of SiO2 is grown over the active region and covered with silicon nitride.
A c tive m ask

S ilico n N itrid e

S tre ss-re lie f o xid e

n-w e ll
p -typ e

Isolation: i)Channel-stop implant:The silicon nitride (over n-active) and the photoresist (over n-well) act as masks
for the channel-stop implant
c h a n n e l s to p m a s k = ~ ( n - w e ll m a s k )

Im p la n t (B o ro n )
r e s it

n -w e ll
p -ty p e

p + c h a n n e l- s to p im p la n t

ii) Local oxidation of silicon(LOCOS): growing thick oxide field after removing photresists.
p a tte rn e d

a c t iv e

a re a

F ie ld

o x id e

(F O X )

n - w e ll
a c tiv e

a re a

a fte r L O C O S

p -ty p e

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Gate oxide growth: After removing stress-relief oxide and nitride gate oxide (thin) is grown.
n - w e ll
p -ty p e
G a t e o x id e

to x

tox
n - w e ll
p -ty p e

Polysilicon deposition and patterning: A layer of polysilicon is deposited on entire wafer and then photolithography
is used to pattern it.
P o lysilico n m a sk
P o lysilico n g ate

n -w ell
p -typ e

PMOS formation: polysilicon acts as a mask for gate region. P+ is implanted.

p+ implant (boron)
p+ mask

n-well
Photoresist
p-type
NMOS formation: n+ is implanted.
n + im pla n t (arse nic o r p ho sp h orou s)
n + m as k

n -w ell
P h o toresist
p -typ e

Annealing: thermal annealing cycle is executed.

n - w e ll
n+

p+
p -ty p e

12

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Contact cuts: The surface of the IC is covered by a layer of CVD oxide. Contact cuts are defined by etching SiO2
down to the surface to be contacted.
C o n ta ct m a sk

n -w e ll
n+

p+
p -ty pe

Metal1: A first level of metallization is applied to the wafer surface and selectively etched to produce the
interconnects.
m e ta l 1 m a s k

m e ta l 1

n -w e ll
n+

p+
p -ty pe

Fig. No. 9 Fabrication sequence of a CMOS Inverter

6. LVS Check:

The LVS check lead to no error. The output window is shown below:

Fig. No. 10 LVS Check

CONCLUSION
In this experiment three basic steps of CMOS process flow Layout Design, DRC and LVS checking have been
studied in Cadence. The layout of a basic inverter has been drawn in the Cadence Virtuoso Layout Suite L for
gpdk90nm process parameters. The design rules of the layout have been checked by the Cadence ASSURA and all
the errors have been resolved. And finally, the LVS check has been performed. Another objective was to obtain
minimum possible dimension for the inverter, which, as we have calculated, has been obtained as instructed. This
experiment helped understand the layout design process rules.

REFERENCES
1. http://en.wikipedia.org/wiki/Integrated_circuit_layout

2. http://en.wikipedia.org/wiki/Design_rule_checking
3. Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI Design: A Circuits and Systems
Perspective, Third Edition, Chapter 4, Section 6,Pearson Education, 2005
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