CCS Technology

Synopsys Interoperability Forum

November 9, 2005
Bill Mullen
Vice President of Engineering
Synopsys, Inc.

Composite Current Source (CCS)

Timing

Timing

2005 Synopsys, Inc. (2)

Noise

Power

Delay Calculation Requirements

Driver Model: drive arbitrary interconnect, including

high-impedance nets
Receiver model: complex input capacitance
Efficient characterization
Vdd & Temperature scaling for IR drop, multi-Vdd, DVFS,
corners

load1
driver
Driver Model

2005 Synopsys, Inc. (3)

Receiver Model

load2

NLDM Based Driver/Receiver Models

Cinp
+
-

Rd

v(t)

Reduced-Order
Network Model
Input cap
single value

Driver Model

Receiver Model

Ramp voltage source,

fixed drive resistance
Very fast accurate for
most nets
Limited accuracy for
high impedance networks
with large drivers (RC-009)

min/max rise/fall input caps

2005 Synopsys, Inc. (4)

Doesnt model capacitance

variation during transition

Basics of CCS Timing

Driver model

Receiver model

C1, C2 vary with

9 Input slew
9 Output load

i(t,v)

C1

C2

9 Rise vs. fall

9 State of cell

Nonlinear
Current
Source

Load1

Driver
Load2

2005 Synopsys, Inc. (5)

Characterization for NLDM

Pin Capacitance

Cell Delay / Slew Tables

input
slew
0.7
0.5
0.2

Cinp
(single value)

0.1
.023 .047 .065 .078 .091

output cap

Measure current
and voltage at input
pin for receiver
model

2005 Synopsys, Inc. (6)

input
slew
0.7

3.31

3.61

3.98

4.12

5.32

0.5

2.72

3.12

3.43

3.82

4.25

0.2

2.22

2.54

2.72

3.11

3.47

0.1

1.31

1.75

1.99

2.31

2.77

.023 .047 .065 .078 .091

output cap

Measure cell delay

and output slew

Characterization for CCS Timing

Receiver Model
input
slew
0.7

Driver Model
input
slew
0.7

C1,C2

C1,C2 C1,C2 C1,C2 C1,C2

0.5

C1,C2

C1,C2 C1,C2 C1,C2 C1,C2

0.5

0.2

C1,C2

C1,C2 C1,C2 C1,C2 C1,C2

0.2

0.1

C1,C2

C1,C2 C1,C2 C1,C2 C1,C2

0.1

.023 .047 .065 .078 .091

output cap

Measure current
and voltage at input
pin for receiver
model

2005 Synopsys, Inc. (7)

.023 .047 .065 .078 .091

output cap

Measure current
through load cap
for driver model

CCS Receiver Model Advantage

CCS Receiver
Model matches
both delay &
slew

Miller effect
at input pin
of inverter

One Cinp
value is
insufficient

Input cap:
single value

2005 Synopsys, Inc. (8)

C1
Cinp

CCS
C2

Receiver model

Vdd and Temperature

CCS Timing enables high accuracy delay

calculation for wide range of Vdd and Temperature
For power-aware design styles:
Single Vdd
Multiple Vdd
Dynamic Voltage & Frequency Scaling (DVFS)

Advanced analysis including IR Drop effects

What is scaled:
Driver model
Receiver model
Timing constraints: setup, hold, recovery, removal,
MPW

Straightforward characterization

2005 Synopsys, Inc. (9)

lib_1.2v.db
lib_1.0v.db
lib_0.8v.db
Separate CCS
Libraries

Constraint Arcs: Vdd & Temperature

Constraint arc (timing check) values depend on

Vdd and Temperature

CCS Timing supports nonlinear scaling of
constraint arcs
Setup vs. Vdd
110

CK

100

tsetup

95
setup (ps)

105

90
85
80
75

CK

70
65
60

D
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0.8

0.85

0.9

0.95

1
Vdd (V)

1.05

1.1

1.15

1.2

CCS Timing Results

Results: STARC, TSMC

STARC
3500

Major Foundry

Delay (HSPIC E vs PT-liberty,PT-C C S)

900

Delay (HSPIC E vs PT-liberty,PT-C C S)

800

liberty,C C S [ps]

850

3000

750

liberty,CC S[ps]

2500

2000

2% vs.
HSPICE

liberty
-3%
+3%
CC S

700

650

600
600

HSPICE[ps]
650

700

750

800

850

900

liberty
-3%
+3%
CC S

1500

3% vs.
HSPICE

1000

500

HSPICE[ps]

0
0

500

1000

1500

2000

2500

3000

PrimeTime2004.12 with STARC

90nm CCS liberty libraries
Error : < 3% vs. HSpice

2005 Synopsys, Inc. (12)

3500

PrimeTime2005.06 with 90nm

CCS liberty libraries
Error : < 2% vs. HSpice

Customers Demonstrate CCS Accuracy

CCS Accuracy v s. HSPICE

CCS & NLDM vs. HSPICE

+/-2%

+/-3%
6,000

5,000

4,000

CCS
-2%
+2%

H SP IC E

C C S [ns]

3
NLDM

3,000

CCS
+3%
-3%

2,000

1
1,000

0
0

Hspice [ns]

1,000

2,000

3,000

4,000

5,000

Prime Time

90nm Library

65nm Library

Major Electronics Firm in Asia

Leading Global IDM

2005 Synopsys, Inc. (13)

6,000

CCS Timing Summary

High accuracy delay and slew calculation

Advanced driver and receiver modeling
Results within 2% of SPICE
Powerful scaling for Vdd and Temperature

No impact on analysis runtime

Easy and efficient characterization
Industry Support
ARM, TSMC, Virage Logic, STARC, Library
Technologies, Synopsys NanoChar

2005 Synopsys, Inc. (14)

Composite Current Source (CCS)

Noise

Timing

2005 Synopsys, Inc. (15)

Noise

Power

Noise Analysis
Aggressor

Failure Analysis

0
Victim

Calculate
Glitch

2005 Synopsys, Inc. (16)

Propagated
Glitch

Noise Modeling Requirements

Accurate model to support:

Noise bump calculation
Noise propagation
Driver weakening (combination of propagated and
injected bumps)
Vdd and Temperature scaling

Characterization should be fast and cover a broad

set of cell types
Model must enable efficient calculation in
analysis and implementation tools

2005 Synopsys, Inc. (17)

NLDM Noise Modeling in Liberty

Aggressor

Noise
Immunity
Curve

0
Victim

I/V Curve
Noise
Propagation

Table-based noise immunity and propagation

characterization require extensive circuit simulation
2005 Synopsys, Inc. (18)

Introducing CCS Noise

Faster Characterization:
100X faster characterization vs. NLDM Noise
Much less circuit simulation is needed
Typical 90nm library in under 4 hours on 10 cpus

High Accuracy:
Accurately models noise propagation and driver
weakening
Accurate voltage and temperature scaling using
the same scaling mechanism as CCS Timing
Same accurate receiver modeling as CCS Timing

2005 Synopsys, Inc. (19)

CCS Noise: Cell Model

Inverter: 1 stage cell
DFF: multi-stage cell
CCS-N
CCS-N
D CCS-N

AND: 2 stage cell

CK CCS-N
CCS-N
CCS-N
CCS-N

First and last transistor stages are modeled

2005 Synopsys, Inc. (20)

Arc and Pin CCS Noise Models

Input stage: Noise immunity

Output stage: Driving strength
Arc: Immunity + Driving Strength + Noise Propagation
For paths of one or two stages
Pin-Based Model
Arc-based Model
CCS-N

CCS-N
CCS-N
CCS-N

2005 Synopsys, Inc. (21)

D CCS-N
CK CCS-N

Arc-Based Example: AND2

A1

A1
Z

CCS-N

N_7
A2

A2

2005 Synopsys, Inc. (22)

CCS-N
CCS-N

AND2 Liberty Syntax

pin(Z) {
direction : output;

timing() {
related_pin
: "A1";

ccsn_first_stage() { /* A1 to N_7 */

}
ccsn_last_stage() { /* N_7 to Z */

}
}

timing() {
related_pin

: "A2";

ccsn_first_stage() { /* A2 to N_7 */

}
ccsn_last_stage() { /* N_7 to Z, copy of the above */

}
}
}

2005 Synopsys, Inc. (23)

CCS Noise Stage Contents

Each CCS Noise stage has three components:

1. DC Current Table
CCS Noise stage

2. Dynamic Behavior
Information
3. Parameters

2005 Synopsys, Inc. (24)

Characterization: DC Current Table

DC Current table represents output current as a function

of two variables
Vin: Input voltage
Vout: Output voltage
A fast DC sweep simulation is used to capture data

Vin
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+
-

+
-

Vout

Characterization: Dynamic Behavior

Small number of transient simulation runs

Inputs: A few ramps and a few glitches
Output response is used to derive the dynamic
behavior of the stage

2005 Synopsys, Inc. (26)

Noise Propagation Accuracy

CCS Noise accurately models dynamic effects

such as the impact of charging/discharging of
internal nodes
Propagated noise
waveform (HSPICE)

Internal Nodes

Voltage (V)

0.5

Propagated noise
waveform (PTSI)

Input noise waveform

0
(HSPICE)
0

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100

200
Time (ps)

300

400

CCS Noise Bump Height Correlation

aggressor
A

(quiet) victim

aggressor
1.2

1.2

Noise Bump Calculation

(Node A)

PTSI Noise Height (V)

PTSI Noise Height (V)

0.8

0.6

0.4

0.2

Noise Propagation
(Node B)

0.8

0.6

0.4

0.2

0.2

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0.4

0.8
0.6
SPICE Noise Height (V)

1.2

0.2

0.4

0.8
0.6
SPICE Noise Height (V)

1.2

Noise Propagation Correlation

1.2

1.2

10%
1

PTSI Noise Height (V)

PTSI Noise Height (V)

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

0.2

0.4

0.8
0.6
SPICE Noise Height (V)

NLDM Noise

2005 Synopsys, Inc. (29)

1.2

0.2

0.4

0.8
0.6
SPICE Noise Height (V)

CCS Noise

1.2

CCS Noise Fast Characterization

2005 Synopsys, Inc. (30)

Library Technology

Number
of cells

Characterization
time on 10 CPUs

Lib1 90-nm

595

1.5 hrs

Lib2 90-nm

747

2 hrs

Lib3 90-nm

593

4 hrs

Lib4 90-nm

541

1 hr

Lib5 90-nm

1304

4 hrs

Lib6 65-nm

766

3 hrs

CCS Noise Summary

Very good customer beta test results

Fast characterization
Typical library in under 4 hours on 10 cpus
For large blocks, only need to characterize
boundary stages

Fast calculation no measurable overhead

during noise analysis

High Accuracy
Noise propagation and driver weakening
Voltage and temperature scaling

2005 Synopsys, Inc. (31)

Composite Current Source (CCS)

Power

Timing

2005 Synopsys, Inc. (32)

Noise

Power

Power Library Requirements

Address needs of Multi-Voltage designs

Multi-Rail cells (Vdd, Vss)
Non-zero ground rail
MTCMOS (power gating)

Static and dynamic rail analysis

Support accurate voltage (IR) drop calculation

Single library / model for all power related

applications

Fast and easy library characterization

2005 Synopsys, Inc. (33)

Power Gating (MTCMOS)

Reduce Leakage by turning block off
Vdd

Vsleep

Fine Grain:
Sleep transistor within each cell
IN

MTCMOS

Block A

LVt

OUT

VirtualVdd

Sleep

Block B
Sleep-mode
Power switch control

Block C

Coarse Grain:
Sleep transistor for entire block
VDD

VSS
VDD

Challenge: Analyze in-rush

current when block turns on
2005 Synopsys, Inc. (34)

INTERNAL VSS

Introducing CCS Power

Switching current waveform for each power or ground pin

Finer time resolution
Full Multi-Voltage support

Equivalent parasitics as seen from the power network

Allows fast yet accurate rail analysis

Support for macro power modeling for memory and IP

Unified library model for power optimization, power
analysis, rail analysis
Fast and easy to characterize

2005 Synopsys, Inc. (35)

Characterization for NLPM

Liberty Non-Linear Power Model

Internal Energy per

transition

3.31
0.7
input 0.5
slew 0.2
0.1

3.61

3.98

4.12

5.32

2.72

3.12

3.43

3.82

4.25

2.22

2.54

2.72

3.11

3.47

1.31

1.75

1.99

2.31

2.77

.023 .047 .065 .078 .091

Leakage power per state

2005 Synopsys, Inc. (36)

output cap

Characterization for CCS Power

Dynamic Current
Waveform per
transition per Rail
0.7
0.5
i(t)

Leakage current per state

per rail

0.2

0.1
input
.023 .047 .065 .078 .091
slew
output cap

Can characterize CCS Power switching

information concurrently with CCS Timing
2005 Synopsys, Inc. (37)

CCS Power Characterization

HSPICE Simulation: AND gate with rising input

Power pin (Vdd) current
Ground pin (Vss) current

2005 Synopsys, Inc. (38)

Advantages: Time Resolution

Captures complete
power and ground pin
current waveforms

I i + I i 1
I n (t n t n 1 )
(ti ti 1 ) +
0 Idt
2
ln (I n 1 I n )
i =1

2005 Synopsys, Inc. (39)

Charge/energy can
be calculated by
integrating current

Dynamic Rail Analysis

Compute instance-specific voltage drop at
all power/ground pins

Requires cell model for switching and nonswitching cases

VDD1

Cpar

GND

2005 Synopsys, Inc. (40)

Rpar

Equivalent Parasitics for NonSwitching Case

Essential for accurate rail analysis additional decoupling cap
Cpar per input state for each power or ground pin
Rpar per input state for each power or ground pin to each output

Rpar

IN1
OUT
Cload
IN2

Cpar

Cload

Cint

Equivalent Parasitics
2005 Synopsys, Inc. (41)

CCS Power Summary

Single Power Model For All Power Applications:
Power Optimization, Dynamic Rail Analysis, Power
Analysis

Accurately Models:

Transient current during switching

Equivalent parasitics for non-switching case
Leakage current
Multi-Voltage designs
Multi-rail cells
Non-zero ground rail

MTCMOS: fine-grain or coarse-grain

Characterized concurrently with CCS Timing

2005 Synopsys, Inc. (42)

CCS Summary
Continuing With A Tradition Of Innovation

CCS - Next Generation Modeling Technology

Open Source
Unified Model For Timing, Noise and Power
Higher Accuracy as Needed By 90nm and Below

Easy and Efficient Library Characterization

Complete Ecosystem: Models, Format, Characterization

Timing

2005 Synopsys, Inc. (43)

Noise

Power

Technical Collateral Material

Technical collateral material for CCS is available on:
www.synopsys.com/products/solutions/galaxy/ccs/cc_source.html

It includes:
CCS Backgrounder
White Papers
Format Specification
FAQ

2005 Synopsys, Inc. (44)