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DEVICE TECHNOLOGY
s Si transistors rapidly approach their projected scaling limit of ~5-nm gate lengths,
exploration of new channel materials and
device architectures is of utmost interest
(13). This scaling limit arises from short
channel effects (4). Direct source-to-drain tunneling and the loss of gate electrostatic control on the
channel severely degrade the Off state leakage currents, thus limiting the scaling of Si transistors
(5, 6). Certain semiconductor properties dictate
the magnitude of these effects for a given gate
length. Heavier carrier effective mass, larger
band gap, and lower in-plane dielectric constant
yield lower direct source-to-drain tunneling currents (7). Uniform and atomically thin semicon1
SCIENCE sciencemag.org
www.sciencemag.org/content/354/6308/96/suppl/DC1
Materials and Methods
Supplementary Text
Figs. S1 to S11
Table S1
References (3456)
20 February 2016; accepted 6 September 2016
10.1126/science.aaf5134
99
10 -4
10 -8
10 -8
MoS2
Si
10 -10
TOX = 0.5 nm
10
-12
10
-14
VDS = 0.43 V
OX,y = 3.9 0
ISD-LEAK (A/m)
ISD-LEAK (A/m)
10 -6
10
-5
10 -11
10 -14
TCH (nm)
10 -17
LG = 4 nm
10 -20
1
TCH (nm)
LG (nm)
Fig. 1. Direct source-to-drain tunneling leakage current. (A) Normalized direct source-to-drain tunneling leakage current (ISD-LEAK), calculated using the WKB (Wentzel-Kramers-Brillouin) approximation as a
function of channel thickness TCH for Si and MoS2 in the Off state. VDS = VDD = 0.43 V from the International
Technology Roadmap for Semiconductors (ITRS) 2026 technology node. (B) ISD-LEAK as a function of gate
length LG for different thicknesses of Si and MoS2 for the same Off state conditions as Fig. 1A. The dotted
line in Fig. 1, A and B represents the low operating power limit for the 2026 technology node as specified by
the ITRS.
Fig. 2. 1D2D-FET device structure and characterization. (A) Schematic of 1D2D-FET with a MoS2
channel and SWCNT gate. (B) Optical image of a representative device shows the MoS2 flake, gate (G),
source (S), and drain (D) electrodes. (C) False-colored SEM image of the device showing the SWCNT
(blue), ZrO2 gate dielectric (green), MoS2 channel (orange), and the Ni source and drain electrodes
(yellow). (D) Cross-sectional TEM image of a representative sample showing the SWCNT gate, ZrO2 gate
dielectric, and bilayer MoS2 channel. (E) EELS map showing spatial distribution of carbon, zirconium, and
sulfur in the device region, confirming the location of the SWCNT, MoS2 flake, and ZrO2 dielectric.
100
R ES E A RC H | R E PO R TS
RE S EAR CH | R E P O R T S
SCIENCE sciencemag.org
10-4
VGS = -3 V to 0.5 V
VDS = 1 V
25
VDS = 50 mV
20
Step = 0.5 V
VBS = 5 V
10
65 mV/decade
10-10
-3
MoS2
10
-5 V
-3 V
-1 V
1V
5V
10-10
-2 -1
VGS (V)
MoS2
(MV/cm)
5.7
OFF
ZrO2
4 nm
SiO2
-3
-2 -1
VGS (V)
ON
4 nm
SiO2
0.001
OFF
10-12
ZrO2
2.9
MoS2
VBS
10-8
15
IG, IB
10-12
10-6
ON
6.5 x 1012
LEFF ~ 3.9 nm
ZrO2
SWCNT
4 nm
SiO2
SWCNT
ZrO2
2.1 x 109
4 nm
SiO2
1.3 x 105
10
10
10
Fig. 3. Electrical characterization and TCAD simulations of 1D2D-FET. (A) ID-VGS characteristics of a
bilayer MoS2 channel SWCNT gated FET at VBS = 5 V and VDS = 50 mV and 1 V. The positive VBS voltage
electrostatically dopes the extension regions n+. (B) ID-VDS characteristic for the device at VBS = 5 V and
varying VGS. (C) ID-VGS characteristics at VDS = 1 V and varying VBS illustrating the effect of back-gate bias
on the extension region resistance, SS, On current, and device characteristics. Electric field contour plots
for a simulated bilayer MoS2 device using TCAD in the (D) Off and (F) On state. Electron density plots for
the simulated device using TCAD in the (E) Off and (G) On state. The electron density in the depletion
region is used to define the LEFF. LEFF ~ d ~ LG in the On state and LEFF > LG in the Off state because of the
fringing electric fields from the SWCNT gate.
-5
-7
VBS = 5 V
VDS = 1 V
-9
10
-11
10
-13
MoS2 thickness
1.3 nm
12 nm
31 nm
-2
-1
VGS-VT (V)
200
Simulation
Experiment
160
120
80
VDS = 1 V
40
VBS = 5 V
0
0
2
4
6
8
10
MoS2 thickness (nm)
12
Fig. 4. MoS2 thickness dependence. (A) Dependence of MoS2 channel thickness on the performance of
1D2D-FET. SS increases with increasing MoS2 channel thickness. (B) Extracted SS from experimental
curves and TCAD simulations show increasing SS as channel thickness TCH increases.
7 OCTOBER 2016 VOL 354 ISSUE 6308
101
-8
VDS = 1 V
ID (A/m)
10-6
ID (A/m)
30
VBS = 5 V
ID (A/m)
10-4
ID (A/m)
R ES E A RC H | R E PO R TS
RE FE RENCES AND N OT ES
102
www.sciencemag.org/content/354/6308/99/suppl/DC1
Materials and Methods
Supplementary Text
Figs. S1 to S10
Table S1
References (3144)
BIOCATALYSIS
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