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IEEE
Std 421.5-2005
39
IEEE
Std 421.5-2005
IEEE STANDARD
As shown in Figure 12-1, the speed (or equivalent) PSS signal provides continuous control to maintain
steady-state stability under normal operating conditions. For the discontinuous control, a signal proportional
to change in the angle of the synchronous machine is obtained by integrating the speed signal. It is not a
perfect integrator, i.e., the signal is reset with the time constant, TAN.
The speed change is integrated only during the transient period following a severe system fault. The relay
contact, S1, which introduces the signal, is closed if the following conditions are satisfied:
a)
b)
c)
2)
The output of the integrator block then decays exponentially with a time constant, TAN.
The use of a fast-acting terminal voltage limiter is essential for satisfactory application of this discontinuous
excitation control scheme. A dual voltage limiter is used to provide fast response and a high degree of
security, without the risk of exciting shaft torsional oscillations. One of the limiters is fast acting and uses a
discrete or bang-bang type of control with hysteresis to limit the generator terminal voltage. The second
limiter uses a continuous control action and is slower acting, but limits to a lower terminal voltage. It takes
over control of terminal voltage from the first limiter after an initial delay and limits the terminal voltage to
a lower value for sustained overexcitation conditions, such as those that could be caused by malfunction of
PSS or discontinuous excitation controls. By overriding the action of the discrete limiter, the slower limiter
prevents sustained terminal voltage and resulting power oscillations inherent to the action of the bang-bang
limiter should the unit be operating continuously against the limit for any reason.
The outputs of the PSS, VST, the terminal voltage limiter, and the angle signal are combined, and overall
limits are applied to the new signal, VS, which goes to the summing junction of the voltage regulator.
40
IEEE
Std 421.5-2005
41
IEEE
Std 421.5-2005
IEEE STANDARD
Annex A
(normative)
Nomenclature
Maximum and minimum limits of parameters are not shown explicitly in the nomenclature, but are
represented by the appropriate subscript (max or min) on the variable. A score line above a parameter is used
to indicate that it is a phasor.
A18
ADJ_SLEW
EFD
EFD1, EFD2
Exciter voltages at which exciter saturation is defined (dc commutator exciters and Type
AC5A models only)
EFDN
ESC
EXLON
F1, F2
FEX
HV GATE
Model block with two inputs and one output, the output always corresponding to the
higher of the two inputs.
HYST
IFD
IFDLIM
IFDMAX
ILR
IN
IRated
I T ,I T
ITFPU
k1
UEL terminal voltage exponent applied to real power input to UEL limit look-up table
k2
UEL terminal voltage exponent applied to reactive power output from UEL limit look-up
table
KA
KAN
KB
42