Zynq EPP Boot Camp Lab Workbook

Zynq EPP Boot Camp Lab Workbook
Zynq EPP Boot Camp Lab Workbook
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Table of Contents
Lab 1: Basic System Implementation ............................................................... 3
Lab 2: Application Development ..................................................................... 51
Lab 3: Software Interrupts ............................................................................... 81
Lab 4: Debugging ........................................................................................... 101
Lab 5: Writing a Device Driver ....................................................................... 121
Lab 6: Integrating a Custom Peripheral ........................................................ 147
Lab 7: Building Custom AXI IP for an Embedded System .......................... 171
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Basic System Implementation
Lab 1: Basic System Implementation

Cortex-A9 Processor and Zynq EPP ZC702 Board
Introduction
This lab is an introduction to the Xilinx Platform Studio. From the modules, you learned the general
concepts of hardware construction. In this lab, you will learn how to construct the hardware platform used
for all of the labs in this course. You will use the Processor Configuration Wizard (PW) to create the
hardware and example test software application named Peripheral_Test. Subsequently, you will create a
new SDK software workspace and add the sample application to it. The hardware consists of:
Cortex-A9 processor core
GPIO interface to drive eight LEDs located under the LCD display
GPIO interface to drive five LEDs located next to each pushbutton
GPIO interface to input the five pushbutton array
UART as an input/output device
Triple timer counter (TTC)
GPIO interface to drive a two-line LCD
Not all of the hardware will be used by the software application in this lab.
Objectives
After completing this lab, you will be able to:
Implement a processor system via the PlanAhead software and XPS using the Processor
Configuration Wizard (PCW)
Add Xilinx-provided or custom peripherals to a processor design
Generate the hardware implementation bitstream file
Connect the target board for download
Configure the Zynq EPP and run a sample application program
Procedure
This lab is separated into steps that consist of general overview statements that provide information on
the detailed instructions that follow. Follow these detailed instructions to progress through the lab.
This lab is comprised of five primary steps: You will implement a processor design with the Processor
Configuration Wizard (PCW); implement the hardware design; create an SDK workspace and add the test
application software generated by PCW; connect the development board hardware; and, finally, configure
the Zynq EPP and test the application.
Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab
from www.xilinx.com/training/downloads.htm. These are the original lab files and do not contain any work
that you may have previously completed.
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General Flow for this Lab
Implementing a Processor Design Using the Processor Configuration

Wizard
Step 1
The first step of this lab is to specify the hardware part of the system. You will begin by
launching PlanAhead software to create a new project for the target Zynq EPP ZC702
evaluation board hardware.
Once the project is created, the PlanAhead tool software launch Xilinx Platform Studio
(XPS). Within XPS, the Processor Configuration Wizard (PCW) is used to choose and
configure system hardware components from those available on the ZC702 evaluation
board.
You will build a system with the following components.
o Cortex-A9 processor core
o GPIO interface to drive eight LEDs located under the LCD display
o GPIO interface to drive five LEDs located around the pushbuttons
o GPIO interface to input the five pushbutton array
o PS - UART1
o Triple timer counter (TTC)
o GPIO interface to drive a two-line LCD
o Quad SPI (flash memory interfaces)
o DDR3 (memory interfaces)
1-1.
Begin the lab by opening a new PlanAhead software project.
1-1-1. Select Start > All Programs > Xilinx ISE Design Suite > PlanAhead > PlanAhead (32) for 32bit systems or PlanAhead for 64-bit systems to launch the PlanAhead software.
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1-1-2. Click Create New Project and click Next.
Figure 1-1: Creating a Project

The New Project Wizard is launched.
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1-1-3. In the Project name field, enter lab1. In the Project location field, browse to the
C:\training\EmbSysSoft\labs directory.
Figure 1-2: Assigning the Project Name and Location

1-1-4. Click Next until you reach the Add Constraints dialog box. Select UCF and click Next.
1-1-5. In the Default Part dialog box, select the board and project options listed below and click Next.
Property Name
Value
Family
Zynq-7000
Package
CLG484
Speed Grade
-1
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Figure 1-3: Selecting the Evaluation Board

1-1-6. Examine the project summary and then click Finish.
Figure 1-4: Finishing the New Project Wizard
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The PlanAhead GUI will be launched.
1-2.
Add a new source file that is of an embedded type. When specified, it will
automatically launch the XPS tool. Then you will use the Processor
Configuration Wizard (PCW) to create the embedded processor system.
1-2-1. In Flow Navigator, Click on Add Sources (
).
The Add Sources Wizard will be launched.

1-2-2. Select Add or Create Embedded Sources from the list of source types and click Next.
Figure 1-5: Adding a New Processor Project Source

1-2-3. Click Create File.
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1-2-4. In the Module Name field, enter system. Click OK.
Figure 1-6: Creating a New Embedded Processor Project Source

1-2-5. Click Finish.
Xilinx Platform Studio will be launched with a blank project.
1-2-6. Click Yes to add Processing System7 instance to the system.
Figure 1-7: Adding a Processing System Instance

1-2-7. Select the ZYNQ tab from the System Assembly View (SAV).
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Take a moment to view the architecture of the processing system (PS). Click the blocks in green
to view the available settings.
Figure 1-8: Processor System Architecture
1-3.
The Zynq Processing System Configuration tab provides a graphical

means for selecting the desired set of PS peripherals and to route them via
MIO or EMIO, as well as selecting physical I/O standards, configuring the
PS DDR controller, and setting clocking parameter.
Select the following PS peripherals (IOP) and configure the selected
peripherals to MIO:
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UART 1
Timer 0
Quad SPI (flash memory interfaces)
DDR3 (memory interfaces)
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1-3-1. Click the Import Zynq Configurations.
Figure 1-9: Importing Zynq EPP Configurations

1-3-2. Click OK to select configuration template.
Figure 1-10: Selecting a Configuration Template

1-3-3. Click Yes to update the MHS file.
This will configure the peripherals that are supported by the chosen board (ZC702) and create the
required system files and settings.
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The IOPs that are configured are displayed in different colors.
Figure 1-11: IOPs Configured (Supported by the ZC702 Board)
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1-3-4. Click the I/O Peripherals block to open the ZYNQ MIO Configuration dialog box. Select Show
I/O Standard Options. Observe the enabled I/O peripherals (IOP) and the I/O connection.
Figure 1-12: Zynq PS MIO Configurations (Supported by the ZC702 Board)

1-3-5. De-select all peripherals except Quad SPI Flash, UART1, and Timer0.
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Not all peripherals used in this lab will be used in subsequent labs.
Figure 1-13: Selecting the I/O Peripherals

1-3-6. Click Close.
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1-3-7. To view how the tool has configured the DDR3 memory, click the Memory Interfaces block in the
ZYNQ tab.
Figure 1-14: DDR3 Memory Configuration

Note that because you selected Import Zynq Configuration in an earlier step, DDR3 memory
(from the ZC702 board configuration) is selected.
1-3-8. Click OK.
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1-3-9. Select the IP Catalog tab in the left window and expand General Purpose IO to view the
available cores under the corresponding entries.
Figure 1-15: System Assembly View of IP Catalog

1-3-10. Double-click the AXI General Purpose IO core (version 1.01.b) in the IP Catalog and click Yes to
add this IP to the design.
The XPS Core Config dialog box will automatically appear. While you can configure the core now,
you will perform this configuration later. This will demonstrate how you can later change a
peripheral configuration.
1-3-11. In the Instantiate and Connect IP dialog box, select Select processor instance to connect to
and click OK.
Figure 1-16: Instantiate and Connect IP Dialog Box

You made the default selection and the tools will automatically make the AXI connection.
However, you could also have chosen to make the connections and settings manually.
The new core will appear as a component in the System Assembly View tab. There will be
several errors in the console because the core was not allowed to auto-configure.
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1-3-12. Change the instance name of the peripheral to LEDs_8bit by clicking once in the Name column
of the axi_gpio_0 component, typing the new name, and then clicking any other screen object.
At this point, the peripherals should look like those in the figure below, although not necessarily in
the same order.
Figure 1-17: Bus Interfaces Tab after Adding and Renaming the axi_gpio_0 Peripheral
Notice that the wire coming from the LEDs_8bit peripheral is attached to the AXI interconnect.
This indicates that this component is connected to the AXI.
As indicated in the previous step when the interconnect was created for the processing system,
the interconnect for the LEDs_8bit peripheral has been automatically made by the tools when the
GPIO was first added. When performed manually, this connection can be made by one of two
ways:
o
The quick connection method is executed by clicking the hollow shape.
The more flexible method requires expanding the LEDs_8bit component and clicking in the
Bus Name column next to the S_AXI port of the component and selecting the desired AXI
interconnect (in this design, there is only a single AXI interconnect).
Figure 1-18: Selecting axi_interconnect_1

1-3-13. Select the Addresses tab. Expand processing_systems7_0s Address Map to view the
address map for this processor.
You can manually assign the base address and size of your peripherals or have XPS generate
the addresses for you. Notice that the LEDs_8bit peripheral in the tree has been assigned an
address already.
Figure 1-19: Adding the LEDs_8bit to the Address Map

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1-3-14. Verify that the memory size of the peripheral is 64K.
1-4.
In this step, you will create an external port to the processor system that
can later be attached to the eight physical LEDs. The configuration of the
GPIO that was deferred earlier will be performed. All of these items will be
performed in the Ports tab of the SAV.
1-4-1. Select the Ports tab in the System Assembly View and expand the LEDs_8bit instance and the
two sub-ports.
Figure 1-20: Ports of Added Instances

1-4-2. Right-click LEDs_8bit and select View PDF Datasheet.
This document is the hardware description of the AXI_GPIO component. Everything you might
want to know about this component will be contained in this document.
1-4-3. Click in the Net column of the the GPIO_IO_O port of the LEDs_8bit instance and select New
Connection as the net name from the Net column drop-down list.
Figure 1-21: GPIO_out Port Connection Added to Instance

XPS will automatically choose a net name (LEDs_8bit_GPIO_IO_O) based on the port name and
instance name of the peripheral.
1-4-4. For GPIO_IO, select No Connection.
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1-4-5. Right-click the LEDs_8bit instance and select Configure IP.
Figure 1-22: Selecting Configure IP

The same XPS Core Config dialog box that appeared when you originally added the component
will be launched.
Note: You can also access the configuration dialog box for a peripheral instance by doubleclicking anywhere in the instance listing.
Notice that the peripheral can be configured for two channels.
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1-4-6. Because you want to use only one channel, keep the Enable Channel option de-selected.
Figure 1-23: Configurable Parameters of the GPIO Instance
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1-4-7. Select Channel 1 to view Channel 1-related configurable parameters. Enter 8 in the GPIO Data
Channel Width box to match the width of the eight LEDs on the the FMC card.
Figure 1-24: Setting Configurable Parameters

1-4-8. Click OK.
1-4-9. Expand External Ports (at the top of the Ports tab).
Note that the LED ports are not listed there yet.
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1-4-10. Click in the Net column of the GPIO_IO_O port of the LEDs_8bits instance and select Make
External from the Net column drop-down list.
Figure 1-25: Making a Port External

Note: The port will connect externally on the Zynq EPP and now appears in the External Ports
connections field with [7:0] as the range.
1-4-11. In Ports tab, expand the processing_system7_0 instance and select New Connection from the
Net column drop-down list for the following signals:
M_AXI_GP0_ARESETN (net name: processing_system7_0_M_AXI_GP0_ARESETN)
FCLK_CLK0 (net name: processing_system7_0_FCLK_CLK0)
Figure 1-26: Creating Signals for FCLK_CLK0 and M_AXI_GP0_ARESETN
1-5.
In this step, you will make reset and clock connections to the AXI
interconnect and processing system.
1-5-1. In the Ports tab, expand processing_system7_0 instance and again expand the (BUS_IF)
M_AXI_GP0 sub-port.
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1-5-2. For M_AXI_GP0_ACLK, select the clock processing_system7_0_FCLK_CLK0 from the Net
column drop-down list.
Figure 1-27: Selecting the Clock Signal (M_AXI_GP0_ACLK)

1-5-3. Similarly, connect the clock and reset signals for the axi_interconnect_1 and LEDs_8bit
component as shown below.
Figure 1-28: Selecting the Clock and Reset Signals
1-6.
Similarly, you will have to create AXI general-purpose I/O for the following
peripherals:
Character_LCD_2x16 (direction: output; width: 11 bits)
LEDs_5_Buttons (direction: output; width: 5 bits)
Buttons_5Bit (direction: input; width: 8 bits)
However, in the interest of time, the completed MHS file is available for you
and you can use it to create AXI general-purpose I/O for the above
peripherals.
1-6-1. In the Project tab on the left, under Project Files, double-click the system.mhs file.
1-6-2. Using Windows explorer, browse to the C:\training\EmbSysSoft\Support directory and open the
system_snippet.mhs file using a text editor.
1-6-3. Replace the contents of the system.mhs in XPS with the contents of the system_snippet.mhs file
in the Support directory. Save it. Click to Reload.
1-6-4. If you are not using the system_snippet.mhs file from the Support directory and are creating AXI
general-purpose I/O for each of the peripherals, be sure to perform the following changes to the
system.mhs file.
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On line 27, change VEC = [10:0] to VEC = [0:10].
Figure 1-29: Changing to VEC[0:10]

The final system should look like the one below:
Figure 1-30: Final View in the Ports Tab (1)
Figure 1-31: Final View in the Ports Tab (2)
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Question 1
Which of the components did you specifically add as peripherals in the Processor Configuration Wizard?
Implementing the Hardware Design
Step 2
The design is now specified. The result is the system.mhs file, which is a netlist of the
various components of the processor system. The netlist is an ASCII-readable file and
the System Assembly View in XPS is its graphic representation.
The next step in the design process is to engage the Xilinx implementation tools to
generate a processor subsystem netlist, export that hardware description to the SDK
software tool, and finally generate a bitstream in the PlanAhead tool. At that point, the
hardware specification and implementation will be complete for all subsequent labs in
the course. Due to time constraints, the hardware netlist and bit file will not be
generated but the necessary steps will be outlined.
2-1.
The embedded processor system is now a component in the PlanAhead

software design. It is now necessary to create a top-level wrapper and add
the UCF file.
2-1-1. Select File > Exit to exit XPS.

In the PlanAhead software project, observe that system.xmp has been added.
2-1-2. In Sources tab, observe Libraries to view Embedded Design Sources.
Figure 1-32: Embedded Design Sources in the Libraries Tab

The added processor system in the project has UCF, XDC and MHS files included.
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2-2.
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The embedded processor system is now a component in the PlanAhead

software design. In this step, you will create a top-level wrapper.
2-2-1. In the Hierarchy window, right-click the system component and select Create Top HDL.
Figure 1-33: Creating the Top-Level Wrapper

2-2-2. Expand the newly created system_stub component.
You can double-click system_stub to examine the HDL code. This is where you could add
additional components to the Zynq EPP design.
2-2-3. Close system_stub after you are finished examining it.
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2-3.
The user constraint file contains Zynq EPP pin placement information and
timing constraints. Add the UCF to the project.
2-3-1. In PlanAhead software, select File > Open File. Browse to

C:\training\EmbSysSoft\labs\lab1\lab1.srcs\sources_1\edk\system\data. Select the system.ucf
file and click OK.
2-3-2. Using Windows Explorer, browse to C:\training\EmbSysSoft\Support. Open the file
system_lab1.ucf using any text editor. Select all the pin information and copy and paste it to the
system.ucf file (C:\training\EmbSysSoft\labs\lab1\lab1.srcs\sources_1\edk\system\data) already
opened in the PlanAhead software.
2-3-3. Select File > Save File.
2-4.
Normally, the hardware design would be implemented and bitstream would

be generated at this time. However, due to the limitations in the software at
this time, you will skip this step. A working bitstream file has been
provided for you. The step is included only for completeness and will result
in errors if attempted using the P7.xd software.
Use the implementation tools in the PlanAhead software to:
Synthesize
Translate
Map
Place and route
Generate the bitstream
This action will implement the hardware design that can be directly
downloaded to the Zynq EPP via a download cable. You can then start
using the software development tools in SDK to implement the software
application on this hardware.
2-4-1. In the Flow Navigator, click Synthesis Settings under Synthesis. Set the strategy to PlanAhead
Defaults.
2-4-2. In the Flow Navigator, click Implementation Settings under Implementation. Set the strategy to
ISE Defaults.
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2-4-3. In the Flow Navigator, click Generate Bitstream.
Figure 1-34: Generating the Bitstream

You are asked to launch synthesis and implementation. Normally, you would click Yes.
However, do not perform this step but note what should done.
Generation takes approximately 30 minutes. When generation is completed, the message
Process "Generate Programming File" completed successfully appears in the Console window.
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Creating the Test Application Software
Step 3
The hardware portion of the project is done. In this step, you will create an SDK
workspace, create a software platform, and add the Peripheral Tests software
application that was created by BSB. Upon automatic launch when exporting embedded
hardware, SDK creates a hardware platform project in the new workspace that you
specified in the last step. On this platform you will build a First Stage Bootloader (FSBL)
project, Board Support Package (BSP), and a software application. All of these projects
will be members of the SDK workspace.
In this step, you will create a software project by using one of the available projects that
SDK supports. When creating a simple software application project, SDK can autocreate the BSP project.
Of the projects in the workspace (hardware platform, BSP, and software application),
two of them will be automatically created, leaving little work for you.
SDK will automatically build the software application project and produce an Executable
and Load Format (ELF) file.
3-1.
Export the processor and launch the Software Development Kit (SDK).
3-1-1. In the Hierarchy window, select and double-click the system_i - system (system.xmp)
component.
3-1-2. In XPS, select Project > Export Hardware Design to SDK. Uncheck Include bitstream and
BMM file.
Figure 1-35: Exporting the Processor Hardware and Launching SDK

The actual exporting of the embedded processor hardware is transparent to the user. The SDK
tool will launch.
SDK creates a workspace environment consisting of project files, tool settings, and your software
application. Once set, you cannot change the location of this workspace. If it is necessary to
move a software application to another location or computer, use the Import and Export features
built into SDK. A good location for the software workspace is the root directory of your
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PlanAhead/XPS software project. While not a requirement, it is a good idea to keep the SDKrelated files together.
3-1-3. Click Export & Launch SDK.
3-1-4. Browse to and select the
C:\training\EmbSysSoft\labs\lab1\lab1.srcs\sources_1\edk\system\SDK directory for
software development and click OK.
Figure 1-36: Setting up the Workspace Environment Path

This directory was created when the Export Hardware Design to SDK command was
performed.
SDK must associate with a hardware system that has been previously exported. It needs
hardware configuration information so that an appropriate software platform or board support
package can be built.
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3-1-5. Verify that the SDK tool launches. Close the welcome screen.
Figure 1-37: SDK Main Window
3-2.
Build a standalone board support package project for a future application

that uses the new created system_hw_platform hardware platform. This
step can also be part of the creating a new software application process.
The intention here is to illustrate that there are three separate projects in
the SDK workspace, hardware platform, BSP, and software application.
Each can be separately built, or the hardware platform can be auto-created
by the export function and the BSP can be created at create software
application time.
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3-2-1. In SDK, select File > New > Xilinx Board Support Package.
Figure 1-38: Creating a Board Support Package

A board support package needs a name and association with a hardware platform. It also needs
a platform type. Xilinx provides a minimal Standalone environment or xilkernel (standalone
environment with a scheduler).
3-2-2. In the New Board Support Package Project dialog box, enter the following settings and click
Finish.
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Project name: lab1-bsp
Hardware Platform: system_hw_platform
CPU: ps7_cortexa9_0
Platform Type: standalone
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Figure 1-39: Creating a New Board Support Package Project

It will take a minute or two for the board support package project to build.
While the board support package is building, the Board Support Package Settings dialog box
opens. This dialog box allows you to select libraries to include in the software project builds that
use the board support package. It also allows you to select standard input and output peripherals,
software driver selection, and other related settings.
3-2-3. Take some time to browse the available board support package settings.
No changes are necessary at this time. The Board Support Package Settings dialog box can be
accessed by right-clicking a board support package project name in the Project Explorer tab and
selecting Board Support Package Settings.
3-2-4. In the Board Support Package Settings dialog box, click OK.
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3-3.
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You are now ready to add a Zynq FSBL application project.
3-3-1. In SDK, select File > New > Xilinx C Project.
Figure 1-40: Creating a C Application Project
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3-3-2. Select Zynq FSBL from the Select Project Template area.
Figure 1-41: Selecting the Zynq FSBL Application

The FSBL configures the programmable logic with a hardware bitstream (if it exists) and loads the
Operating System (OS) Image or Standalone (SA) image or second stage bootloader image from
the non-volatile memory (NAND/NOR/QSPI) to RAM (DDR) and starts executing it.
3-4.
In this step, you will add a new C software application project by using the
BSB-created Peripheral Tests sample application project template and the
newly created lab1-bsp.
3-4-1. Select File > New > Xilinx C Project.
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SDK supports multiple software projects in a single SDK project. There are several different types
of software application projects, with the simplest being a C application project. In this type of
project, the software designer writes code from the standpoint of beginning in the main{} C
function.
The New Xilinx C Project dialog box appears. Note that every software application is attached to
a software platform (BSP) that is already attached to a hardware design.
3-4-2. Select the Peripheral Tests project template. Keep the default project name peripheral_tests_0
and click Next.
Figure 1-42: Creating a Peripheral Test Application

The next step is to associate a board support package to the project. The board support package
contains all the software drivers for system components.
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3-4-3. Select Target an existing Board Support Package, select lab1-bsp, and click Finish.
Figure 1-43: Associating a Board Support Package

3-4-5. In the Project Explorer tab, right-click the peripheral_tests_0 project name and select Generate
Linker Script.
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3-4-6. Select ps7_ddr_0_S_AXI_BASEADDR as the memory area used from the Code Sections, Data
Sections, and Heap and Stack drop-down lists.
Figure 1-44: Configuring the Linker Script

3-4-7. Click Generate. Click Yes to overwrite the existing linker script file if prompted.
IMPORTANT: When you click Generate, the application is automatically compiled and linked. If
there is an error, repeat the step to generate the linker script.
3-4-8. Make sure that the application is built without errors.
Figure 1-45: Successful Software Application Build
3-5.
From SDK, open the file testperiph.c and examine the test code. Then test
your understanding by answering the questions that follow.
3-5-1. In the Project Explorer tab, expand the src folder under the peripheral_tests_0 application.
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3-5-2. Double-click the testperiph.c program to open it.
Figure 1-46: Opening the Source File

3-5-3. Find the beginning of the main program near line 48.
The line and column number of the cursor in the file is displayed along the bottom edge of the
SDK window a little right of center in the format line:column. Line numbers can be turned on for
the editor by right-clicking in the left margin and selecting Show Line Numbers.
Question 2
What does the testperiph.c program do?
Question 3
What is the program unable to do? Hint: See the comment at about line 204.
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3-5-4. Close the testperiph.c file and examine the xgpio_tapp_example.c test program and note:
o
The testperiph.c program calls functions in xgpio_tapp_example.c.
The XGpio_DiscreteWrite function near line 209, in xgpio_tapp_example.c, is used to output

data to the LEDs on the board.
There is a conditional compile directive (a few lines below) to insert a software-based timing
delay loop when the code is not targeted for simulation.
3-5-5. Examine this simulation-only timing loop.
Question 4
What is the constant name defining the number of times a wait loop will be executed to make the LED
visible? Hint: Look a few lines below line 209.
Question 5
How many times will the wait loop be executed? (Hint: Look for a #define statement near the beginning of
the program.)
Connecting the Development Board Hardware
Step 4
In this step, you will become familiar with the Zynq EPP ZC702 development board and
learn how to connect to it.
You will verify that the board configuration switches and jumpers are properly set and
then connect the power supply, download, and serial cables to the evaluation board.
Ask the instructor for help if you encounter problems.
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4-1.
Connect the ZC702 board to your machine. Open a terminal in SDK to view
the output of the software application.
4-1-1. Connect the ZC702 board to your machine as shown below.
Figure 1-47: ZC702 Development Board

4-1-2. Make sure that the USB cable is used to connect the USB UART port (J17) in the board to the
machine and the Platform Cable USB connects the platform cable pins (J2) in the board to the
machine.
4-1-3. Ensure that the jumper settings on the board (J20 J22, J25 J28) are as shown in the figure
above.
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4-1-4. Power up the ZC702 board.

4-1-5. Determine if a Terminal window is already open.
A terminal tab would appear next to the Problems, Tasks, Console, and Properties tabs under the
Edit window.
Figure 1-48: Terminal Tab and Connect Icon

4-1-6. If you do not see a Terminal tab, select Window > Show View > Terminal.
Figure 1-49: Opening a Terminal Window

4-1-7. Click the Connect icon to open the Terminal Settings dialog box.
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4-1-8. Configure the settings as shown in the following figure.
Figure 1-50: Terminal Settings

Note: The COM port setting is specific to the computer being used and may need to be different
than shown.
4-1-9. Click OK.
Configuring the Zynq EPP and Testing the Application
Step 5
In this last step, you will configure the Zynq EPP, download the application, and test the
program for proper operation.
You will then perform a simple modification to the application to make a row of LEDs
continuously chase each other.
This lab assumes that the ZC702 hardware board and download cabling are in place.
5-1.
The Zynq EPP will now be configured with a bitstream that has been
provided for you.
5-1-1. Make sure that the hardware board is set up and turned on.
5-1-2. In SDK, select Xilinx Tools > Program FPGA.
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5-1-3. In the Bitstream field, browse to the C:\training\EmbSysSoft\Support directory and select the
system.bit file.
Figure 1-51: Programming the Zynq EPP

5-1-4. Click Program.
The Zynq EPP should be configured in less than 30 seconds. Look for a message window to read
"FPGA configuration complete" to flash briefly on the display.
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5-2.
Create a new Run configuration named peripheral_tests_0 and test the

application.
5-2-1. In the Project Explorer tab, right-click the peripheral_tests_0 software application and select
Run As > Run Configurations.
Figure 1-52: Creating a Run Configuration

5-2-2. In the Run Configurations dialog box, double-click Xilinx C/C++ ELF in the left pane.
A default Run configuration named peripheral_tests_0.elf will automatically be created.
5-2-3. Select the Device Initialization tab and check the settings.
Notice that there is a configuration path to an initialization Tcl file. The path of ps7_init.tcl is
mentioned. This file was exported when you exported your design to SDK and it contains the
initialization information for the processing system.
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5-2-4. Click Run. Click OK on the Reset Status dialog box.

5-2-5. View the results in the Terminal window.
Figure 1-53: Viewing in Terminal after Downloading the Software Application

You may have noticed that, after the download finished and the program started, the five LEDs
next to each pushbutton on the FMC expansion card and the row of eight LEDs, located under
the LCD display, each flashed once in order.
Figure 1-54: Location of LEDs

If you missed this event, you can rerun the test program.
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5-3.
Change the C code in testperiph.c to make the LEDs blink continuously.
5-3-1. In the Project Explorer tab, double-click the testperiph.c file under the src folder to open it.
5-3-2. At line 104, add the C statement while (1) {
5-3-3. At line 135, add a }.
5-3-4. Save the testperiph.c file.

The file will automatically build. Make sure that it compiles error-free.
5-4.
Re-Run the application peripheral_tests_0.
5-4-1. In the Project Explorer tab, right-click the peripheral_tests_0 software application and select
Run As > Run Configurations. Click Run.
5-4-2. Verify that the LEDs turn on and off sequentially for a "light-chasing" effect.
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5-4-3. To terminate the program, click the Terminate icon in the Console tab.
Figure 1-55: Terminating the Program
Question 6
Where does the print() routine output to? How would the output device be configured?
Question 7
Was it necessary to re-implement (Translate, Map, Place & Route) the hardware when the software was
updated? Describe the relationship between hardware and software updates.
Conclusion
In this lab, you built a hardware system and learned how to include an embedded processor design as
part of a PlanAhead software project.
The processor component of the design was added as a new source, launching XPS and using the
Processor Configuration Wizard. When you completed the hardware design, you exported it (the Export
Hardware Design to SDK command), launched the SDK tools, created a peripheral test software
application project, and produced the ELF software object for it.
You returned to the PlanAhead software to generate the hardware bitstream file and complete the
hardware design process. You then connected the ZC702 development board to your computer and
tested the sample software application that was created.
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Answers
1. What does the testperiph.c program do?
The program first enables the processor cache via calls to the appropriate system services.
Subsequently, there are BSB-generated calls to test routines for each of the selected peripherals.
Each of these calls is enclosed in braces {}.
The other source files in the project support the various tests for each of the peripherals.
2. What is the program unable to do? Hint: See the comment at about line 204.
The ps7_uart_1 will not be run because it has been selected as the STDOUT device. However, the
UART will be used as an output device.
3. What is the constant name defining the number of times a wait loop will be executed to make the LED
visible? Hint: Look a few lines below line 209.
LED_DELAY
4. How many times will the wait loop be executed? (Hint: Look for a #define statement near the
beginning of the program.)
#define LED_DELAY 1000000
// 1,000,000 times
5. Where does the print() routine output to? How would the output device be configured?
The print() function prints to STDOUT, although this information is not obvious from looking at these
files.
This information would be found in the OS and Libraries Document Collection reference document
under the software section (select Start > All Programs > Xilinx ISE Design Suite 14.1 > EDK >
Documentation > Reference User Guides). Most of the Xilinx software services follow normal C
language practices.
The output device that STDOUT talks to was configured when BSB selected and configured the
sample software application during the Application step of the Processor Configuration Wizard.
6. Was it necessary to re-implement (Translate, Map, Place & Route) the hardware when the software
was updated? Describe the relationship between hardware and software updates.
No, the hardware does not have to be re-implemented when the software changes, only if the
hardware changes.
Typically, during software development, the hardware platform is static and having to re-implement
would take unnecessary time. Instead, Xilinx keeps the existing bitstream (BIT file) and updates it
with the new software object.
A BMM file indicates where in block RAM the object code (ELF file) should be placed. This is all done
as part of the Program FPGA command.
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Application Development
Lab 2: Application Development

Introduction
In this lab you will use the Xilinx Software Development Kit (SDK) to create a simple software application
project. The source files for a software loop-based stopwatch are provided. The application is mostly
written, lacking only the code to initialize the data direction of two general-purpose I/O peripherals,
axi_gpio, as either inputs or outputs. One of the five peripherals is for the directional pushbuttons on the
evaluation board, which you will configure as inputs. The other drives the LEDs, which you will configure
as outputs.
It is your task to find and use the correct Level 0 driver calls that set I/O direction, requiring you to search
the hardware and device driver documentation. In the example used for the lab, these calls are #define
macros that have low overhead and execute quickly. The axi_gpio is one of the most popular processor
peripherals, so much of what you learn here will be useful in future projects.
Objectives
Create an SDK software application project
Navigate Xilinx processor peripheral hardware documentation
Navigate device driver API documentation
Implement a Level 0 device driver
Download and run an application on development hardware
Procedure
This lab comprises four primary steps: You will open a pre-built basic hardware system and create an
SDK software application project; add Level 0 axi_gpio device drivers to the software application;
configure the Zynq EPP; and finally, download and run the application.
Creating an SDK Software Workspace
Step 1
The first step in this lab is to create an SDK software workspace.

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The working directory of the SDK workspace for this lab and all subsequent labs is
C:\training\EmbSysSoft\labs. You will create the SDK workspace and software platform
for the hardware that was developed in the "Basic System Implementation" lab in this
directory. This workspace directory and software platform will be used in subsequent
labs.
A working version of the hardware that you built in the the "Basic System
Implementation" lab has been placed in the C:\training\EmbSysSoft\Support\hw
directory so that this and subsequent labs do not require the completion of the "Basic
System Implementation" lab.
Once SDK is launched and a workspace is set up in this directory, you will not be able
to move these directories.
1-1.
Launch SDK. Select C:\training\EmbSysSoft\labs as the workspace

directory and system.xml in the C:\training\EmbSysSoft\Support\hw
directory as the hardware specification file.
1-1-1. Select Start > All Programs > Xilinx ISE Design Suite > EDK> Xilinx Software Development
Kit to launch SDK.
The Workspace Launcher opens.
SDK creates a workspace environment consisting of project files, tool settings, and your software
application. Once set, you cannot change the location of this workspace. If it is necessary to
move a software application to another location or computer, use the Import and Export facilities
built into SDK. A good location for the software workspace is the root directory of your ISE tool
project.
1-1-2. In the Workspace Launcher, browse to and select C:\training\EmbSysSoft\labs as the
workspace directory and click OK.

This directory was created in the "Basic System Implementation" lab when the Export Hardware
Design to SDK command was performed. While not a requirement, it is a good idea to keep the
SDK-related files together.
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SDK must associate with a hardware system that has been previously exported. It needs
hardware configuration information so that an appropriate software platform or board support
package can be built.
1-1-3. Close the Welcome screen if it appears in SDK.
1-1-4. Select File > New > Xilinx Hardware Platform Specification.
1-1-5. Enter EmbSysSoftHWP in the Project name field. Browse to C:\training\EmbSysSoft\Support\
hw, select the system.xml hardware project, and click Open.
Figure 2-2: Creating a New Hardware Project

system.xml was also created when you exported the hardware design to SDK. Essentially this is
an XML version of the XPS project (system.xmp) and netlist (system.mhs) files.
1-1-6. Click Finish to create the hardware project.
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The Hardware Platform Specification (system.xml file) is displayed.
Figure 2-3: Newly Created Hardware Project

SDK supports multiple hardware platform projects in the same workspace.
Note: When you scroll lower in the system.xml file, you can display information about the IP by
clicking the link to the datasheet for the IP.
Adding a Software Application
Step 2
In this step, you will generate the software platform for the hardware and an empty
software project. Then you will import C source files into the project and SDK will
automatically build and produce an Executable and Load Format (ELF) file.
You will examine, but not change, the board support package (BSP) platform options.
Provided are the nearly completed C source code and associated LCD display drivers,
which you will add to the project. Then you will generate a linker script and configure the
compiler options.
As a first step in a new software environment, a software platform must be built to
contain a library of system and processor services, as well as device drivers for the
hardware peripherals that make up the system. Once a software platform has been
built, then a software application can be written. Xilinx provides the Software Platform
wizard to accomplish this task.
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2-1.
Build a standalone board support package project named lab2-bsp that

uses the EmbSysSoftHWP hardware platform.
Figure 2-4: Creating a Board Support Package

A board support package needs a name and association with a hardware platform. It also needs
a platform type. Xilinx provides a minimal Standalone environment or xilkernel (standalone
environment with a scheduler).
2-1-2. In the New Board Support Package Project dialog box, enter these settings and click Finish.
o
Hardware Platform: EmbSysSoftHWP
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It will take a minute or two for the board support package project to build.
opens. This dialog box allows you to select libraries to include in the software project builds that
use the board support package. It also allows you to select standard input and output peripherals,
software driver selection, and other related settings.
2-1-3. Take some time to browse the available settings.
2-1-4. No changes are necessary at this time, so click OK.
The Board Support Package Settings dialog box can be accessed by right-clicking a board
support package project name in the Project Explorer tab and selecting Board Support Package
Settings.
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2-2.
Create a blank software application (Empty Application) named stopwatchlab2 as a C project.

SDK supports multiple software projects in a single SDK workspace. There are several different
types of software application projects, with the simplest being a managed make C application
project. In this type of project, the software designer writes code from the standpoint of beginning
in the main{} C function.
The New Xilinx C Project dialog box appears. Note that every software application is attached to
a software platform (BSP) that is already attached to a hardware design.
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2-2-2. Select the Empty Application project template. Enter stopwatch-lab2 in the Project name field
and click Next.
Figure 2-7: Naming the C Project and Selecting a Project Template

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2-3.
Import the source code files lab2.c, lcd.c, and lcd.h from the
C:\training\EmbSysSoft\Support directory into the project. Verify that it
builds correctly.
2-3-1. In the Project Explorer tab, expand the stopwatch-lab2 project, right-click the src directory, and
select Import.
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2-3-2. In the Select dialog box, expand General, select File System, and click Next.
Figure 2-9: Importing Files into the Project

2-3-3. In the From directory field, browse to the C:\training\EmbSysSoft\Support directory and click OK.
2-3-4. Select lab2.c, lcd.c, and lcd.h for import.
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Use the default Into folder directory path, which copies the files into the src folder of the current
project.
Figure 2-10: Importing Existing Source Files into the Application

The application is automatically built. The Console window shows the results of the build.
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2-3-6. Make sure that the application is built without errors.
Figure 2-11: Successful Software Application Build
2-4.
Review the board support package platform options and note how to
change them from SDK. No changes need to be made.
2-4-1. In the Project Explorer tab, right-click lab2-bsp and select Board Support Package Settings.
In the Overview view of the Board Support Package Settings dialog box, note that standard Xilinx
libraries for TCP/IP, flash, memory file system, and others can be selected to be included in the
board support package.
Figure 2-12: Overview View of the Board Support Package Settings Dialog Box
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You will come back to this in the "File Systems" lab to include the Xilinx Memory File System. At
this time nothing needs to be done.
2-4-2. In the left navigation pane, select standalone to view the OS configuration settings.
Figure 2-13: OS Configuration Settings

Here, the peripherals used for stdin and stdout can be set. This is also where profiling and
MicroBlaze processor exceptions are configured. You will return here in the "SDK Profiling" lab
to enable profiling.
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2-4-3. In the left navigation pane, select drivers to view driver settings.
Figure 2-14: Software Driver Settings

Here, software drivers and driver versions can be selected for each peripheral. You will return
here in the "Writing a Device Driver" lab to configure the LCD to use a custom driver.
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2-4-4. In the left navigation pane, select cpu to view CPU-related configuration settings.
Figure 2-15: Compiler Settings

Here, the compiler to be used can be set along with extra compiler flags. Normally, these settings
do not need to be changed.
2-4-5. Click OK to close the Board Support Package Settings dialog box.
When changes are made to the BSP settings, the BSP is rebuilt when you click OK.
2-5.
Generate a linker script, locating the Code, Data, Stack, and Heap sections
in on-chip block RAM. The off-chip DDR3 RAM will not be used in this lab.
2-5-1. In the Project Explorer tab, right-click the stopwatch-lab2 project and select Generate Linker
Script.
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2-6.
Verify the C/C++ Build properties. Make sure that compiler optimization is
off and that debugging symbols are enabled for the Debug configuration.
Verify that the proper linker script has been selected.
2-6-1. In the Project Explorer tab, right-click the stopwatch-lab2 project and select C/C++ Build
Settings.
2-6-2. In the Properties dialog box, expand C/C++ Build in the left navigation pane and select Settings.
2-6-3. In the Configuration area, select Debug [ Active ] from the drop-down list.
2-6-4. In the Tool Settings tab, expand ARM gcc compiler, select Optimization, and set the
Optimization Level to None (-O0).
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2-6-5. Select Debugging in the properties list just below Optimization and set the Debug Level to
Default (-g).
Figure 2-17: C/C++ Build Properties for stopwatch-lab2

2-6-6. In the Settings window, select Linker Script under ARM gcc linker and verify that the linker script
file is ../src/lscript.ld.
Figure 2-18: Linker Script Setting
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2-6-7. Click OK and the application will be rebuilt.
Question 1
When might you change a setting in the Board Support Package Settings dialog box and regenerate the
BSP?
Question 2
What would you do differently in this step to generate faster, more compact C code?
Finishing and Building the Software Application
Step 3
The stopwatch application is almost complete. To complete the application, the registers
controlling the data direction of the axi_gpio peripherals used for the pushbutton inputs
and LED outputs need to be initialized.
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3-1.
Review the axi_gpio datasheet to determine how to program I/O data

direction.
3-1-1. In the Project Explorer tab, expand the EmbSysSoftHWP hardware platform project and doubleclick system.xml to open the hardware platform specification in the edit window.
Figure 2-19: Accessing the axi_gpio Datasheet

To the right of LEDs_8Bit (or any peripheral that uses the gpio peripheral) is a Datasheet link that
will show information about the selected IP.
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3-1-2. Click the Datasheet link to open the gpio datasheet in a browser window.
Figure 2-20: axi_gpio Datasheet

3-1-3. View the operation of the AXI GPIO 3-State Register on page 9 of the datasheet.
Figure 2-21: 3-State Register Information for the AXI GPIO
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It states that bits in the register cleared to 0 configure the associated I/O pin as an output and
bits set to 1 configure the associated I/O pin as an input.
Now you need a way to set up the registers in the lab2.c program. For the sake of simplicity, you
will use a low-level macro.
3-2.
Open the system.mss file to access peripheral drivers documentation. Find

the macro call in the xps_gpio_l.h driver file to write to a register. Open and
read the information for the macro function call in xgpio_l.h. Determine the
parameters required by the macro function call.
3-2-1. In the Project Explorer tab, expand the lab2-bsp board support package project and double-click
system.mss to open the board support package information in the edit window.
3-2-2. In the list of peripheral drivers, click the Documentation link next to a gpio peripheral.
Figure 2-22: system.mss File Board Support Package Information

The gpio drivers documentation opens in a browser window.
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3-2-3. Click Files to display the list of documented elements.
Figure 2-23: gpio Software Drivers Documentation
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3-2-4. Find the low-level generic write register macro for xps_gpio and click the link to xgpio_l.h next to
it.
Figure 2-24: gpio Software Drivers File List
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The xgpio_l.h file reference document opens in the browser window, displaying information about
the low-level write register macro.
Figure 2-25: Low-Level Write Register Macro Description

Note that all the level 0 macros are contained in xgpio_l.h. Take a moment to scroll through the
xgpio_l.h file reference information. Note the register offset #define statements that are useful
when using the low-level macros.
3-2-5. Study the macro and the #define symbols that need to be used to set gpio data direction.
3-3.
Find the program location in the lab2.c source (with the comment "Student
to add code here") to set the axi_gpio data direction for the pushbuttons
and LEDs. Using the macro driver functions, initialize the data direction for
the two axi_gpio peripherals. Compile and link the code.
To perform this step, you will need the base address of the 8-bit LEDs and
5-bit pushbutton peripherals. The base address #defines are found in the
xparameters.h file that is automatically created when the BSP is built.
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3-3-1. In the Project Explorer tab, expand the stopwatch-lab2 project, expand the src folder and
double-click lab2.c to open it in the edit window.
Figure 2-26: Conditionally Compiled Blocks of Code

Note that conditionally compiled blocks of code that were not compiled are shown with a gray
background so that you can easily tell what code was compiled.
3-3-2. Right-click in the left margin of the lab2.c file and select Show Line Numbers.
3-3-3. Scroll down in the lab2.c file to find the comment blocks that begin with "Student to add code
here". Add the macro calls necessary to initialize the data direction registers of the pushbutton
and LED gpio peripherals.
You can also copy and paste the necessary code from the lab2_xps_gpio_macro_calls.c file in
the C:\training\EmbSysSoft\Support directory.
Figure 2-27: Macro Calls to Initialize the Data Direction Registers
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3-3-4. Save the lab2.c file when you finish.

The tools will automatically re-build the project.
A successful build is indicated when the program size is returned.
Figure 2-28: Returning the Program Size Indicates a Successful Build

Note that your code size may vary.
Question 3
In what file are the low-level macro-based gpio functions found? How many gpio macro functions exist?
Question 4
Is changing, editing, or adding to the xparameters.h file a good idea? Why or why not?
Step 4
In this last step, you will configure the programmable logic, download the application,
and test the program for proper stopwatch operation. The hardware portion of the
design has already been implemented for you. This is the same configuration that was
created in the "Basic System Implementation" lab. This lab assumes that the ZC702
hardware board and download cabling are in place.
4-1.
Configure the Zynq EPP with the bitstream. The BIT file is located in the
C:\training\EmbSysSoft\Support directory
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system.bit file.
These are the hardware files that were created in the "Basic System Implementation" lab.

The Zynq EPP should be configured in less than 30 seconds. Look for the message, "FPGA
configuration complete" to flash briefly on the display.
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4-2.
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Create a new Run configuration named stopwatch-lab2 and test the

application.
4-2-1. In the Project Explorer tab, right-click the stopwatch-lab2 software application and select Run
As > Run Configurations.

A default Run configuration named stopwatch-lab2.elf will automatically be created.
4-2-3. Click Run to download and run this configuration.
The message "Lab2" should appear on line 2 (bottom) of the LCD. The stopwatch time appears
on line 1 (top). The eight LEDs along the bottom of the LCD should strobe left to right when the
stopwatch is running.
4-2-4. Verify proper stopwatch operation.
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The button functions are:

o
START BTN3
STOP
RESET BTN1
BTN2
4-2-5. To terminate the program, click Terminate button on the Console tab. If not visible, select Xilinx
Tools > XMD Console and enter stop in the XMD command box.
Figure 2-31: Terminating the Program
Question 5
Why is the bootloop program specified for FPGA configuration?
Question 6
The Run configuration is set for the Debug project configuration. What is the purpose for all of these
configurations?
Conclusion
In this lab, you created a basic SDK software application that operates a software loop-based stopwatch.
The application utilized Level 0 axi_gpio device drivers. You used the documentation available from SDK
to investigate how to identify and install these drivers in the C source. You learned how to configure the
FPGA, then load and run the software application.
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Answers
1. When might you change a setting in the Board Support Package Settings dialog box and regenerate
the BSP?
The settings can be changed for various reasons, including:
Changing hardware
Changing the configuration options of the standalone BSP services
Changing or adding a new device driver to the BSP
2. What would you do differently in this step to generate faster, more compact C code?
In the C/C++ Build section properties, the compiler optimization was turned off to enhance debugging.
Setting the optimization level higher will cause the compiler to generate more efficient and compact
code.
3. In what file are the low-level macro-based gpio functions found? How many gpio macro functions
exist?
Low-level, macro-based functions for the gpio peripheral are all found in the xgpio_l.h file.
There are only two gpio macro functions: XGpio_WriteReg( ) and XGpio_ReadReg( ). These macros
are useful for doing simple tasks in small programs. In larger, more complex programs, the gpio
functions found in the xgpio.c file may be a better choice.
4. Is changing, editing, or adding to the xparameters.h file a good idea? Why or why not?
No, the xparameters.h file is regenerated every time the BSP is built by LibGen. This is a read-only
file.
5. Why is the bootloop program specified for FPGA configuration?
The bootloop program is a default program that is essentially a branch to *. Its purpose is to keep the
processor safely occupied after configuration until the actual application is downloaded. In normal
operation, the tested and debugged software application would be in this place.
6. The Run configuration is set for the Debug project configuration. What is the purpose for all of these
configurations?
SDK accommodates multiple setups for quickly choosing an object ELF application to download to
the simulator or hardware; this is a RUN configuration. Project configurations, such as Release,
Debug, and Profile, each allow the compiler/linker to generate a different ELF file based on tool
settings for each configuration. The Debug configuration is created by default during project creation.
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Lab 3: Software Interrupts

Introduction
This lab will convert the stopwatch application of the "Application Development" lab from a softwarebased timing loop to an interrupt-driven, timer-based peripheral. The application program has been
mostly written for you and includes usage of the interrupt controller (GIC) and timer (TTC0) peripherals.
The application program performs the following regarding the interrupt:
Initializes the processor interrupts
Initializes the interrupt controller
Registers the interrupt controller interrupt service routine (ISR) with the processor interrupt data
structure
Registers the timer ISR with the interrupt controller interrupt data structure
You will be required to search BSP processor services documentation to find and use the correct
processor service calls that initialize the processor interrupt data structure and enable interrupts. The API
documentation for the interrupt controller (GIC) and timer (TTC0) device driver services will be examined.
The axi_timer is one of the most commonly used processor peripherals, so much of what you will learn
here will be useful for future projects.
Objectives
Create an SDK software application project
Navigate Xilinx processor device services documentation
Use the BSP processor interrupt services
Navigate device driver API documentation
Investigate interrupt controller (GIC) and timer (TTC0) device driver services
Download an application to hardware
Procedure
This lab comprises three primary steps: You will create an SDK software application; add processor
services device drivers to the software application; and, finally, configure the Zynq EPP and test the
application.
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Creating an SDK Software Application
Step 1
In this step, you will create a software application in SDK by using the provided C
source code. You must complete the code, then add it and the LCD display drivers to
the project. A linker script will be generated and the compiler options set.
Keep working with the SDK workspace that you started using in the "Application
Development" lab. Even if you are not able to complete or get subsequent labs working,
the workspace is valid for use.
This lab adds another software application project to the existing SDK project,
illustrating that multiple applications can be created in one SDK workspace. Every
subsequent lab in this course will add a new software application to the SDK
workspace.
1-1.
Launch SDK and open the workspace in the C:\training\EmbSysSoft\labs

directory.
1-1-1. If the SDK project is still open, skip to step 1-2.

1-1-2. Restart SDK.
1-1-3. Browse to the workspace directory C:\training\EmbSysSoft\labs and click OK.
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1-1-4. Verify that your workspace appears similar to the following figure.
Figure 3-2: SDK Project Workspace
1-2.
Create a new application project named interrupt-lab3. Import the source

code files lab3.c, lcd.c, and lcd.h from the C:\training\EmbSysSoft\Support
directory into the project.
Notice a bug in the application that will result in a compile error.
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1-2-2. Select the Empty Application project template. Enter interrupt-lab3 in the Project name field
and click Next.

contains all the software drivers for system components. The hardware has not been changed
from the previous lab.
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1-2-4. In the Project Explorer pane, expand the interrupt-lab3 project, right-click the src directory, and
select Import.
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project.
Figure 3-7: Importing Existing Source Files to the Application

The application files are automatically built but errors are declared. Ignore the errors for now.
They will be fixed in the course of this lab.
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1-2-9. In the Project Explorer tab, note that folder icon for interrupt-lab3 has a red X. Expand the folder
and note that the src folder and its lab3.c file also have a red X.
Figure 3-8: Finding Files with Errors

The red X indicates a location (file or folder) where an error exists.
1-3.
in on-chip block RAM. The off-chip DDR3 RAM will not be used in this lab.
1-3-1. In the Project Explorer tab, right-click the interrupt-lab3 project and select Generate Linker
Script.
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IMPORTANT: When you click Generate, the application is automatically compiled and linked.
Although the linker script generates correctly, the previous build error remains.
1-4.
set to None and that debugging symbols are enabled for this new
configuration. Verify that the proper linker script is selected.
Fix the program bug in the application.
1-4-1. In the Project Explorer tab, right-click the interrupt-lab3 project and select C/C++ Build
Settings.
1-4-2. In the Configuration area, select Release from the drop-down list.
Optimization Level to None.
1-4-4. Select Debugging in the properties list just below Optimization and set the Debug Level to None.
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1-4-5. In the Tool Settings tab, select Linker Script under ARM gcc linker and verify that the linker
script file is ../src/lscript.ld.
Figure 3-10: Linker Script Setting

1-4-6. Click OK.
1-4-7. In the Project Explorer tab, expand the src folder under the interrupt-lab3 folder and double-click
the lab3.c file to open it in the editor window.
Note the small red symbols that indicate an error (circles in the following figure).
Figure 3-11: Error Symbols

Placing the cursor over the red symbol next to the vertical scroll bar (the arrow in the figure
above) displays a description of the error.
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1-4-8. Click the red symbol next to the vertical scroll bar to display the line in the file that is causing the
error.
The error is the undefined label INTC_DEVICE_ID0. The problem is just a typo where the ID0
should be a ID.
Figure 3-12: Fixing the Error

1-4-9. Fix the problem and save the lab3.c file.
The application is automatically rebuilt and the error is gone.
Finishing and Building the Software Application
Step 2
The stopwatch application is mostly finished. What remains is enabling the interrupt for
the device and enable the timer interrupt.
You will use driver documentation sources.
2-1.
Open lab3.c and find the commented location for enabling the interrupt for
the device and enabling the timer interrupt.
Add the appropriate code, save the file, and verify error-free compilation.
2-1-1. View the system.mss file in the edit window.
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If the file is not already open, expand the lab2-bsp project in the Project Explorer tab, then
double-click the system.mss file to open it.
2-1-2. Click the Documentation link next to scugic.
Figure 3-13: Opening the Documentation (scugic and scutimer)
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2-1-3. Click the Files, then Globals, and then Functions links.
Figure 3-14: Viewing the XScuGic Functions
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2-1-4. Click the xscugic.h link and view the function details.
Figure 3-15: Viewing the XScuGic_Enable Function

2-1-5. In lab3.c, scroll to and study line 379.
2-1-6. Test your skills and write the code to enable the interrupt for the device and enable the timer
interrupt where indicated by the comment.
Below is the required code snippet to enter. You can also copy-and-paste it from the
lab3_interrupt_enable.c file in the C:\training\EmbSysSoft\Support directory.
XScuGic_Enable(IntcInstancePtr, TimerIntrId);
XScuTimer_EnableInterrupt(TimerInstancePtr);
2-1-7. Save the lab3.c file.
Question 1
Where is the BaseAddress parameter found for ps7_scutimer_0?
Question 2
What level of driver service is this? How can you tell? What file would be referenced to understand its
operation?
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Step 3
In this last step, you will configure the Zynq EPP, download the application, and test the
program for proper stopwatch operation. The hardware portion of the design has
already been implemented for you. This is the same configuration that was used in the
"Basic System Implementation" lab. This lab assumes that the ZC702 hardware board
and download cabling are in place.
3-1.
Configure the Zynq EPP with the bitstream that has been provided for you.
system.bit file.

3-2.
Create a new Run configuration named interrupt-lab3 Debug and test the
application.
3-2-1. In the Project Explorer tab, right-click the interrupt-lab3 software application and select Run As
> Run Configurations.
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3-2-2. Double-click Xilinx C/C++ ELF to create a new configuration.

3-2-3. Select the Main tab and set the following parameters.
o
Name: interrupt-lab3 Debug
Project: interrupt-lab3
Build Configuration: Debug
C/C++ Application: Debug\interrupt-lab3.elf

3-2-4. Click Run. Click OK in the Reset Status dialog box.
3-2-5. Verify proper stopwatch operation.
o
START BTN3
STOP BTN2
RESET BTN1
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3-2-6. To terminate the run, click the red Terminate icon in the Console window. If not visible, select
Xilinx Tools > XMD Console and enter stop in the XMD command box.
Figure 3-18: Terminating a Run

Runs must be terminated before another run can be started.
Question 3
Is the stopwatch program more accurate with a timer than the software loop from the "Application
Development" lab?
Conclusion
In this lab, you converted a software loop-based stopwatch to an interrupt-driven, timer-based stopwatch.
You researched scu_gic and scu_timer in the documentation to enable the interrupt.
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Answers
1. Where is the BaseAddress parameter found for ps7_scutimer_0?
In the xparameters_ps.h file, the symbol is defined as XPAR_SCUTIMER_BASEADDR.
2. What level of driver service is this? How can you tell? What file would be referenced to understand its
operation?
[ANSWER]
3. Is the stopwatch program more accurate with a timer than the software loop from the "Application
Development" lab?
Yes, while the software timing loop may be predictable, it is difficult to determine how much time the
rest of the main{} program loop takes to execute. With a hardware timer, the main{} loop starts every
10 ms. As long as main{} takes less than 10 ms, the timer will be accurate to the clock frequency.
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Debugging
Lab 4: Debugging
Introduction
This lab will introduce you to the SDK software debugger. The stopwatch application created in the
previous lab will be set up for debugging and observations will be made by using the debuggers features.
You are encouraged to experiment with the various debug options.
Objectives
Set up an SDK software application project for debugging
Use the many features of the SDK debugger
Procedure
This lab comprises three primary steps: You will open a pre-built basic hardware system and create an
SDK software application project; configure the Zynq EPP, create a Debug Run configuration, and
download the application; and, finally, use the features of the debugger.
Creating and Building an SDK Software Application
Step 1
The first step of this lab is to create an SDK software application as you did in previous
labs. The C code source from the previous lab will be used as the target for debugging.
The software application will compile and link without errors.
Keep working with the SDK workspace that you started using in the "Application
Development" lab. Even if you are not able to complete or get subsequent labs working,
the workspace is valid for use.
This lab adds another software application project to the existing SDK project,
illustrating that multiple applications can be created in one SDK workspace. Every
subsequent lab in this course will add a new software application to the SDK
workspace.
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1-1.
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Launch SDK and open the workspace in the C:\training\EmbSysSoft\labs

directory.
1-1-1. If the SDK project is still open, skip to step 1-2.

1-1-2. Restart SDK.
1-1-3. Browse to the workspace directory C:\training\EmbSysSoft\labs and click OK.
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1-1-4. Verify that your workspace appears similar to the following figure.
Figure 4-2: SDK Project Workspace
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1-2.
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Create a new application project named debug-lab4. Import the source

code files lab4.c, lcd.c, and lcd.h from the C:\training\EmbSysSoft\Support
directory into the project.
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1-2-2. Select the Empty Application project template. Enter debug-lab4 in the Project name field and
click Next.

contains all the software drivers for system components. The hardware has not been changed
from the previous lab.
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1-2-4. In the Project Explorer tab, expand the debug-lab4 project, right-click the src directory, and
select Import.
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1-2-8. Use the default Into folder directory path, which copies the files into the src folder of the current
project.
Figure 4-7: Importing Existing Source Code into a Project

The application is automatically built. The Console tab shows the results of the build.
1-3.
in on-chip block RAM. The off-chip DDR RAM will not be used in this lab.
1-3-1. In the Project Explorer tab, right-click the debug-lab4 project and select Generate Linker Script.
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1-4.
off and that the Debug Level is Maximum for the Debug configuration.
Verify that the proper linker script has been selected.
1-4-1. In the Project Explorer tab, right-click the debug-lab4 project and select C/C++ Build Settings.
1-4-2. In the Configuration area, select Debug [ Active ] from the drop-down list.
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Optimization Level to None (-O0).
Figure 4-9: C/C++ Build Properties for debug-lab4

1-4-4. Select Debugging in the properties list just below Optimization and set the Debug Level to
Maximum (-g3).
1-4-5. In the Tool Settings tab, select Linker Script under ARM gcc linker and verify that the linker
script file is ../src/lscript.ld.
1-4-6. Click OK.
The application is rebuilt. A successful build is indicated when the program size is returned.
Figure 4-10: Returning the Program Size Indicates a Successful Build
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Setting Up the Test Application for Debugging
Step 2
In this step, you will configure the Zynq EPP, set up the project for debugging, download
the application, and open the SDK Debug perspective. The hardware portion of the
design has already been implemented for you. This is the same configuration that was
used in the previous labs. This lab assumes that the ZC702 hardware board and
download cabling are in place.
2-1.
system.bit file.

2-2.
Create a new Debug configuration named lab4-debug and test the

application.
2-2-1. In the Project Explorer tab, right-click the debug-lab4 project and select Debug As > Debug
Configurations.
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2-2-2. Double-click Xilinx C/C++ ELF to create a new configuration.

2-2-3. Select the Main tab and set the following parameters.
o
Name: debug-lab4 Debug
Project: debug-lab4
Build Configuration: Debug
C/C++ Application: Debug\debug-lab4.elf
Figure 4-12: Creating a Debug Configuration

2-2-4. Click Debug. Click OK in the Reset Status dialog box.
2-2-5. Click Yes in the Confirm Perspective Switch dialog box if it appears.
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A Debug perspective is opened.
Figure 4-13: Debug Perspective Window

Program operation is suspended at the first executable statement in main{} (not running).
Note that local variables for the current function are shown in the Variables tab.
Using the Features of the SDK Debugger
Step 3
In this step, you will use the debugger to research interrupt latency time by using
breakpoints, examine the contents of the memory-mapped timer peripheral via the
Memory tab, determine the time spent updating the LCD display by using breakpoints,
and identify how to free run and halt a program thread.
3-1.
Set up the project for debugging, setting a breakpoint in the timer interrupt
handler.
3-1-1. Select the Breakpoints tab.

Tip: If you click the X on the tab, the tab will close. To reopen the view, select Window > Show
View and select the view that you want to open.
The lab4.c source file should be visible in the Sources window.
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Note: Click in the window to make it active.

3-1-2. In the Outline tab, in the list of functions, click TimerIntrHandler() to open it.
Note: There are actually two occurrences of TimerIntrHandler in the Outline tab list. Make sure to
click the one next to the widely known international symbol for a function
click the other one (should be at the bottom of the list).
. If this does not work,
The line in lab4.c where the function starts is highlighted.

3-1-3. Scroll down in the TimerIntrHandler() function to line 409 and double-click the line number 423 to
set a breakpoint there (a check mark becomes visible
).
This line is the next statement following an assignment to variable zx. Note that the breakpoint
that you just set appears in the Breakpoints view (upper right pane, Breakpoints tab).
3-1-4. Click the Play/Resume button (green triangle
) to run the program.
The program runs to the breakpoint.

3-1-5. Select the Variables tab located next to the Breakpoints tab.
The Variables view now shows the local variables of the TimerIntrHandler() function. The local
variable zx contains the value read from the timer register immediately after entering the interrupt.
3-1-6. Click the C/C++ perspective (
) button just below the main toolbar in the upper right of the
SDK window to view the lab4.c source file.
The lab4.c source file should be displayed in the main editor window. You can also perform this
step in the Debug perspective, but the view pane in the C/C++ perspective is generally larger and
more convenient to use.
3-1-7. Scroll up to line 222 where the auto-reload value is set.
3-1-8. Move the cursor over the constant TIMER_LOAD_VALUE and note the displayed value.
3-1-9. Click the Debug (
) button just below the main toolbar in the upper right of the SDK window
to return to the Debug perspective.
3-2.
Calculate the latency for entering the timer interrupt service routine.
3-2-1. Subtract the value of the local variable zx from the auto-reload value.
The timer interrupt occurred when the timer value reached zero. The timer continues to count
even after interrupting. The value of the local temporary variable zx is set to the current timer
value after entering the timer interrupt service routine (line 423).
Because the timer counts down from the auto-reload value, the result is the number of timer
ticksat ~2.5 ns per tickthat it took to get into the ISR. (ScuTimer runs at 400 MHz).
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Question 1
Approximately how many clock ticks were required for the system to enter the timer interrupt? What does
this number represent in actual time?
Question 2
What does this time signify from a system view?
3-3.
View a specific memory location of the memory-mapped timer count

register.
3-3-1. In the bottom window, select the Memory tab (located in the same window as the Console tab).
If it not available, select Window > Show View and select Memory.
3-3-2. Click the green + sign in the Memory tab toolbar to add a memory monitor.
The Memory Monitor dialog box appears, requesting the address to be monitored.
Figure 4-14: Monitor Memory Dialog Box

You will use this debug feature to view the contents of the timer count register, a memorymapped peripheral.
You are looking for the value of the ScuTimer count register. Where should you look to find the
address?
3-3-3. Click Cancel.
You will come back to this dialog box after determining the address to enter.
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3-3-4. In the Outline tab (middle right side), scroll to the top of the list and double-click the
xparameters.h include file to open it.
3-3-5. Again, in the Outline tab, double-click the xparameters_ps.h file to open it.
3-3-6. Again, in the Outline tab, scroll down the list to find the base address of ScuTImer (the #define
name is XPAR_SCUTIMER_BASEADDR).
3-3-7. Click XPAR_SCUTIMER_BASEADDR in the Outline tab list and the line where it is defined is
highlighted in the window to the left.
#define XPAR_SCUTIMER_BASEADDR (XPS_SCU_PERIPH_BASE + 0x600) where
XPS_SCU_PERIPH_BASE is 0xF8F00000
3-3-8. Note the base address of XPAR_SCUTIMER_BASEADDR.
3-3-9. Return to the C/C++ Perspective (upper right of the SDK window
file which may already be open as a tab in the edit window.
). View the system.xml
If the system.xml file is not already open, expand the EmbSysSoftHWP project in the Project
Explorer tab (left side) and double-click the system.xml file to open it.
3-3-10. In the IP blocks present in the design list, click the ps7_scutimer_0 datasheet link to open its
datasheet.
Note: The datasheet is not available for the beta version.
The count vale register address is 0xF8F00604 (base address + 4).
3-3-11. Return to the SDK Debug perspective.
3-3-12. Click the green + sign in the Memory tab toolbar to add a memory monitor.
3-3-13. In the Memory Monitor dialog box, enter the base address of the ps7_scutimer_0 peripheral as
the memory address to monitor.
Remember to type the address as a hex value by using the 0x prefix.
3-3-14. Click OK.
Question 3
What is the base address of ScuTimer and the offset to the count register? How many bytes of memory
does this count register consume?
Question 4
What bsp source file might contain a #define for the base address of ScuTimer?
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Debugging
3-3-15. In the Variables window, right-click zx and select Format > Hexadecimal.
It is necessary to compare the count register value with the value of the local variable zx.
Unfortunately, the Count value register value is by default shown as hex and there is no way to
easily change its radix. However, the radix display format of the zx variable in the Variables
window can be easily changed.
The value of zx will be displayed in hex.
Question 5
Are the values of the variable zx and the Count value register the same? Should they be close? Why or
why not?
3-4.
Remove the existing breakpoint and set a new breakpoint. Calculate the
time spent servicing the LCD.
3-4-1. Open the lab4.c file again and scroll to line 423. Double-click the breakpoint marker in the left
margin, or the line number, to remove the breakpoint.
You could also have removed the breakpoint by right-clicking the breakpoint in the Breakpoints
window and selecting Remove.
3-4-2. Scroll up to line 304 and double-click the line number to set a new breakpoint.
This breakpoint is set at the next statement after the assignment to zx upon LCD update
completion.
3-4-3. Click the Play/Resume button to run to the breakpoint.
This operation may take a few seconds for the system to update.
On line 304, the general-purpose variable zx is used to calculate how much time is spent
servicing the LCD. This is the difference between the value of the timer before the LCD is
serviced (line 295) and the timer value read at line 304. At line 307, the calculation is complete
and zx can be observed.
Question 6
At ~2.5 ns per count, approximately how much time is spent servicing the LCD?
3-5.
Skip the breakpoints. Run and suspend the program.
3-5-1. Select the Breakpoints tab.
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3-5-2. In the Breakpoints window toolbar, click the Skip All Breakpoints icon ( ).
Figure 4-15: Skip All Breakpoints Icon

3-5-3. Click the Play/Resume button again.
3-5-4. In the Debug window, click the Suspend icon ( ) to pause program execution.
3-5-5. To terminate the run, click the red Terminate icon ( ) in the Debug window.
3-5-6. To restart the program, right-click the terminated Debug session in the Debug window and select
Relaunch to restart the debug session.
Figure 4-16: Relaunching After Termination

3-5-7. Explore the debugger on your own.
Conclusion
In this lab, you used the debugger in SDK to debug a basic software application. You learned how to set
up a software project for debugging and how to use the features of the debugger.
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Debugging
Answers
Answers listed represent sample solutions only. Your results may differ depending on the version of the
software, service pack, or operating system that you are using.
1. Approximately how many clock ticks were required for the system to enter the timer interrupt? What
does this number represent in actual time?
About 202 clock ticks at ~2.5 ns per tick. Approximately 5 s.
2. What does this time signify from a system view?
This is the interrupt latency time.
3. What is the base address of ScuTimer and the offset to the count register? How many bytes of
memory does this count register consume?
0xF8F00600 is the ScuTimer base address. The count register offset if (0xF8F00600 + 0x4). Four
bytes, 0xF8F00604 0xF8F00607.
4. What bsp source file might contain a #define for the base address of ScuTimer?
The xscutimer_hw.h file found by expanding lab2-bsp > ps7_cortexa9_0 > libsrc > scutimer_v1_00a >
src. The parameter name can be found in the Outline list (XSCUTIMER_COUNTER_OFFSET).
5. Are the values of the variable zx and the Count value register the same? Should they be close? Why
or why not?
The value of zx and Count register are not the same or even close. They would only be the same or
close by coincidence. The timer is a peripheral on the SCU unit and does not stop when the
processor is halted. The debugger reads the timer value some amount of time after the breakpoint is
reached.
6. At ~2.5 ns per count, approximately how much time is spent servicing the LCD?
Typically, about 1 msec.
zx (number of counts) * 2.5 ns = ~1 ms.
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Writing a Device Driver
Lab 5: Writing a Device Driver

Introduction
A device driver is a lower-level service that typically interfaces the software application with a specific
piece of hardware. Device drivers can either be part of your software application project or part of the
board support package (BSP). When it is part of your application project, the source code for the drivers
must always be present and compiled/linked with your application. If the driver is used often and well
debugged, a better alternative is to make it a service of the BSP. This makes it easier to distribute and the
programmer does not have to be concerned with keeping track of it in the application project.
All Xilinx-provided peripherals have device drivers that are included in the BSP when they are used.
When a custom peripheral is created via the Create and Import Peripheral Wizard, a skeleton software
driver for BSP inclusion is provided, along with a hardware skeleton.
Because this lab is a software exercise and there is limited time, you will not be able to build a custom
piece of hardware and a software driver for it. Instead, you will create a custom driver for the axi_gpio bus
peripheral. The process will illustrate the ability of the SDK to support multiple software drivers for any
given hardware peripheral.
The hardware platform in this class uses an axi_gpio peripheral as a controller for the LCD display on the
Zynq EPP ZC702 evaluation board. The timer software application project in the "Application
Development" lab included a low-level driver for the LCD display. In this lab, you will move the LCD
device driver from the software application into the BSP as an included service.
The structure of the device driver environment is sensitive to directory/file names and locations.
Generating *.mdd and *.tcl definition files will be necessary. To make the task easier, you will use the
Create and Import Peripheral Wizard in XPS to generate dummy hardware peripheral and device driver
skeletons. You will ignore the hardware portion and build on the software structure that the wizard
generates.
Objectives
Create a device driver skeleton by using the Create and Import Peripheral Wizard
Edit the *.mdd file to attach to a peripheral
Write code to replace the driver for the axi_gpio peripheral
Successfully include the device driver in the BSP
Call the BSP services from a software application
Procedure
This lab comprises four primary steps: You will create a skeleton device driver; add the LCD device driver
from the "Application Development" lab and create the BSP; create a project in SDK with the application
program from the "Application Development" lab; and, finally, verify proper device driver operation by
downloading to the hardware and testing.
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Creating a Skeleton Device Driver
Step 1
The first step of this lab will be to create an LCD dummy peripheral using the Create
and Import Peripheral Wizard in XPS to generate the skeleton structure of the device
driver.
1-1.
Launch XPS. Create an XPS project named system.xmp in the

C:\training\EmbSysSoft\labs\lab6 directory.
Create a new peripheral software driver skeleton named lcd by using the
Create and Import Peripheral Wizard within XPS.
1-1-1. Select Start > All Programs > Xilinx ISE Design Suite > EDK > Xilinx Platform Studio to
launch XPS.
1-1-2. In the Xilinx Platform Studio dialog box, click Create New Blank project.
Figure 5-1: Creating a Blank XPS Project
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1-1-3. In the Create New XPS Project dialog box, browse to the C:\training\EmbSysSoft\labs directory to
specify a project file and append the lab6 directory. Accept the default system.xmp project file.
Figure 5-2: Create New XPS Project Dialog Box

Because you are just using this project to create a software driver skeleton, any target device can
be used. In a sense, this is just a dummy project.
1-1-4. De-select AXI Clock Generator and AXI Reset Module.
1-1-5. Accept the other default settings and click OK.
If you are asked to create the new directory, click Yes.
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1-1-6. Click OK to close the How to Add IPs to Design dialog box.
Figure 5-3: How to Add IPs to Design Dialog Box

A processing_system7 instance in the XPS project opens.
Figure 5-4: PS7 Instance the XPS Project

1-1-7. In XPS, select Hardware > Create or Import Peripheral to start the wizard.
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The Welcome window for the Create and Import Peripheral Wizard appears.
Figure 5-5: Viewing the Welcome Dialog Box

This wizard is used to create and import a custom hardware peripheral. At completion, it
generates a skeleton software driver. Because this lab is not concerned with the hardware
content that consumes most of the wizard choices, you will select the default settings for the
hardware choices. The second-to-last dialog box of the wizard presents the option to generate a
skeleton device driver structure.
1-1-8. Click Next.
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1-1-9. In the Peripheral Flow dialog box, select Create templates for a new peripheral and click Next.
Figure 5-6: Selecting to Create New Peripheral Templates

The Repository or Project dialog box allows you to specify where the peripheral files will be kept.
If the peripheral will be reused in other projects, an EDK user repository would be the best choice.
If the peripheral will not be used again, then the files would best be kept in the project. For this
lab, you will keep the files within the project.
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1-1-10. In the Repository or Project dialog box, select To an XPS project and click Next.
Figure 5-7: Selecting Where to Store the New Peripheral

1-1-11. In the Name and Version dialog box, enter lcd in the Name field, accept the default settings for
the various versions, and click Next.
Figure 5-8: Naming the Peripheral

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1-1-12. In the Bus Interfaces dialog box, select AXI4-Lite: Simpler, non-burst control register style
interface and click Next.
Figure 5-9: Selecting the Bus Interface
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1-1-13. In the IPIF (IP Interface) Services dialog box, deselect all options and click Next.
Figure 5-10: Selecting the IP Interface

No IPIF services, such as software reset, are required for the lcd peripheral. And because you
are not using the hardware that will be created, deselecting these options will reduce disk space
usage.
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1-1-14. In the IP Interconnect (IPIC) dialog box, review the settings and click Next.
Figure 5-11: Reviewing the Default IPIC Signal

This dialog box displays the default IPIC signals that are available for the user logic based on the
previous selection.
In this lab, you do not require any of the optional unchecked signals.
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1-1-15. In the Peripheral Simulation Support dialog box, deselect Generate BFM simulation platform if
necessary and click Next.
Figure 5-12: Deselecting the Option to Generate a BFM Simulation Platform

Peripheral simulation support is not necessary.
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1-1-16. In the Peripheral Implementation Support dialog box, select Generate template driver files to
help you implement software interface and click Next.
Figure 5-13: Peripheral Implementation Support

This dialog box is the only one that concerns the lcd peripheral. Although minimum custom
hardware is actually being made, it will not be used in this lab. The objective is to add a custom
driver to an existing peripheral. To create a custom driver, the template driver files are necessary.
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1-1-17. Review the summary of the peripheral that will be created and click Finish.
Figure 5-14: Reviewing the Summary
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1-1-18. Using Windows Explorer, verify that the new drivers directory has been added to the XPS project
structure.
Figure 5-15: Project Directory with the New drivers Directory

The lab6 directory should be in the C:\training\EmbSysSoft\labs directory.
Question 1
Browse to the C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\src directory. This directory is where
the source files for the device driver reside. What files have been placed there by the wizard?
Question 2
What is in the lcd.c file?
No hardware was changed or created so the design does not have to be re-implemented. The
goal of the process is to associate a custom driver to existing peripheral hardware. The new
peripheral is named lcd but the hardware is actually an unmodified gpio peripheral.
1-1-19. Close XPS.
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Adding the Device Driver to the BSP
Step 2
The skeleton driver that was added in the last step needs to be customized as an
axi_gpio peripheral driver. You will accomplish this by modifying the lcd.mdd device
driver description file.
The lcd.c device driver file from the "Application Development" lab will replace the
skeleton version of the same name that was generated by the wizard. The generated
lcd.h file will not be needed because the drivers in lcd_ml605.c will actually be calling
the axi_gpio drivers that are already in the BSP.
This is a valuable feature in that device drivers in the BSP (or software platform) can
call other device driver services in the same BSP.
In this step, you will:
o Modify lcd.mdd to point to the axi_gpio peripheral by using SDK.
o Replace the lcd.c file located in the C:\training\EmbSysSoft\labs\lab6\drivers\
lcd_v1_00_a\src directory with custom driver files from the C:\training\EmbSysSoft\
Support\MB_ML605 directory.
o Add the path for the custom lcd driver files to the User-Defined Software
Repositories.
o Create a new BSP and modify its settings to use the lcd driver for the LCD display.
o Regenerate the BSP.
2-1.
Modify the configuration files that integrate the driver source into the BSP
are in the C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\data
directory.
The lcd_v2_1_0.mdd file needs to be modified so that this software driver is
associated with the axi_gpio peripheral. The lcd_v2_1_0.tcl file does not
need modification because it generates symbols that will not be used in the
xparameters.h file.
2-1-1. Launch SDK and select the C:\training\EmbSysSoft\labs workspace.

2-1-2. Select File > Open File and open the lcd_v2_1_0.mdd file in the
C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\data directory.
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2-1-3. On line 11, change lcd to axi_gpio.
Figure 5-16: Associating the lcd Driver with the axi_gpio Peripheral
Changing this symbol directs the association on the device driver to the name of the supported
hardware. In this step, you are indicating that this driver is for the axi_gpio peripheral, as opposed
to the non-existent LCD hardware that was specified, but not used, when the skeleton was
created with the Create and Import Peripheral Wizard.
2-1-4. Save and close the lcd_v2_1_0.mdd file.
2-1-5.
Using Windows Explorer, delete the lcd.c file located in the

C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\src directory.
2-1-6. Using Windows Explorer, copy the lcd_zc702.c and lcd_driver.h files from the
C:\training\EmbSysSoft\Support directory to the
C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\src directory.
This replaces the skeleton custom driver source file generated by the Create and Import
Peripheral Wizard with the new custom lcd driver source files. Note that the file name is not
important as the make utility will compile all the *.c files in the src directory.
Note: Open the lcd_selftest.c from the directory
C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\src directory. Comment the line no. 13
(#include "xio.h").
2-2.
The User-Defined Software Repositories indicate search directories for

LibGen to reference when building the BSP. The location of the new driver
must be included in the search path.
Note that the added path is two directories above
C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a, where the custom
lcd driver files are located. This is simply how the tools search for custom
drivers.
If the wrong path is specified, the custom driver files will not be found and
errors will result in the building of all software platforms and software
applications that require the driver files.
2-2-1. Select Xilinx Tools > Repositories.

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2-2-2. To the right of the Local Repositories area, click New, then browse to and select the
C:\training\EmbSysSoft\labs\lab6 directory and click OK.
The path should appear in the Local Repositories list.
Figure 5-17: Software Repositories Dialog Box

Note: The added path is two directories above where the custom lcd driver files are located.
2-2-3. Click OK.
Everything in the SDK project is rebuilt because the software repository applies to the entire SDK
project, not just a single BSP or software application.
Note: If a build error occurs, clean the project and build all.
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2-3.
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The newly created device driver must be associated with the instance of
the LCD display. Currently, the GPIO driver is selected.
In this step, you will create a new BSP named lab6-bsp and set the driver
for its LCD peripheral to be the new lcd driver.
2-3-2. In the Xilinx Board Support Package Project dialog box, enter these settings and click Finish.
o
Hardware Platform: EmbSysSoftHWP

opens.
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2-3-3. In the left navigation pane, expand Overview and select drivers. For the Character_LCD_2x16
instance, select lcd from the Driver column drop-down list.
Figure 5-19: Associating the lcd Driver with the Character_LCD_2x16 Instance
This assigns the custom lcd driver that was just created to the Character_LCD_2x16 instance in
the design.
2-3-4. Click OK to close the Board Support Package Settings dialog box and start BSP regeneration.
2-3-5. In the Console window, verify that the BSP is built without errors.
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2-3-6. In the Project Explorer tab, expand the lab6-bsp project and verify that the lcd_v1_00_a directory
was added to the microblaze_0\libsrc directory.
Figure 5-20: Added lcd Driver Source Files
Question 3
Which of the preceding steps resulted in lcd as an option for the axi_gpio driver in the Software Platform
Settings dialog box?
Question 4
In the Project Explorer pane, double-click the lcd_driver.h file to open it. Note that functions are divided
into External and Internal. External functions are those called by other functions outside of the driver.
What parameter is passed into all external functions? Why would this parameter be needed?
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Question 5
If errors occurred in the BSP build after you added the new driver, what might the problem be?
Creating an SDK Application
Step 3
The newly added driver is ready to be tested. You will use the application from the
"Application Development" lab to test the driver. Note that the LCD display driver, which
was part of the "Application Development" lab application project, will not be present.
The same lcd driver is now part of the BSP. Here you will create an SDK software
application project and import the lab6 source file into it.
3-1.
In this step, you will create another software application project that uses
the LCD by relying on the presence of the LCD drivers in the BSP.

3-1-2. Select the Empty Application project template. Enter lcd_driver-lab6 in the Project name field
and click Next.
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3-1-4. In the Project Explorer tab, expand the lcd_driver-lab6 project, right-click the src directory, and
select Import.
3-1-7. Select lab6.c for import.
project.
The application is automatically built.
3-1-9. Check the linker script settings for the lcd_driver-lab6 C project.
Hint: Right-click the project name.
3-2.
in on-chip block RAM.
3-2-1. In the Project Explorer tab, right-click the lcd_driver-lab6 project and select Generate Linker
Script.
Question 6
How do you know that the LCD drivers are part of the BSP?
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Verifying Device Driver Operation
Step 4
You are now ready for the big test. Configure the Zynq EPP, download the program,
and make sure that the stopwatch application is still working.
This lab assumes that the ZC702 hardware board and download cabling are in place.
4-1.
system.bit file.

configuration complete" to flash briefly on the display. The program will already be running.
4-1-5. In the Project Explorer tab, right-click the lab6_driver-lab6 software application and select Run
As > Run Configurations.
A default Run configuration named lab6_driver-lab6.elf will automatically be created.
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4-1-7. Click Run. Click OK on Reset Status dialog box.

4-1-8. Verify operation of the stopwatch.
o
START BTN3
STOP
RESET BTN1
BTN2
4-1-9. Terminate the program.
Question 7
Do you expect any difference in performance, whether the LCD drivers are part of the BSP or
application project, as in the "Application Development" lab?
Conclusion
In this lab, you created a new software driver for the axi_gpio peripheral. You used the Create and Import
Peripheral Wizard to create the skeleton framework and used the lcd driver from the "Application
Development" lab with minor modifications as the main source for this driver.
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Answers
1. Browse to the C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\src directory. This directory is
where the source files for the device driver reside. What files have been placed there by the wizard?
lcd.c
lcd.h
lcd_selftest.c
Makefile
2. What is in the lcd.c file?

Nothing. It is a shell.
3. Which of the preceding steps resulted in lcd as an option for the axi_gpio driver in the Software
Platform Settings dialog box?
Changing the supported peripherals option in the lcd_v2_1_0.mdd file from lcd to axi_gpio.
4. In the Project Explorer pane, double-click the lcd_driver.h file to open it. Note that functions are
divided into External and Internal. External functions are those called by other functions outside of the
driver. What parameter is passed into all external functions? Why would this parameter be needed?
The LCD base address is passed into all external functions. It is needed because the LCD base
address will vary with hardware configuration. Passing the base address as a parameter is one way
to get this necessary information into the driver functions.
5. If errors occurred in the BSP build after you added the new driver, what might the problem be?
An error in one of the C source files located in the
C:\training\EmbSysSoft\labs\lab6\drivers\lcd_v1_00_a\src directory or the driver source files were not
found due to an incorrect or missing path in the User-Defined Software Repositories.
6. How do you know that the LCD drivers are part of the BSP?
The easiest way to tell is that the LCD driver files are not found in the application source file folder but
they are found in the lab6-bsp > ps7_cortexa9_0 > libsrc > lcd_v1_00_a > src folder, which is a BSP
project.
7. Do you expect any difference in performance, whether the LCD drivers are part of the BSP or
application project, as in the "Application Development" lab?
No, basically the same driver, lcd_zc702.c (which is a modified version of the lcd.c file used in the
previous labs), is the source used in the BSP.
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Integrating a Custom Peripheral
Lab 6: Integrating a Custom Peripheral

Zynq EPP ZC702 Board
Introduction
This lab guides you through the process of adding the custom IP created in the "Building Custom AXI IP
for an Embedded System" lab to an existing processor system using XPS and then integrating the
processor system with other logic in an ISE software design. At the end of the lab, you will download the
software and design to hardware using the XMD tool.
Objectives
Use a processor interrupt
Create a new SDK workspace and import a previously archived project
Place the processor system in the hierarchy of a Project Navigator software project
Add other logic to an Project Navigator tool project that contains a processor system
Download and test the design in hardware
Procedure
In this lab, you will extend the hardware design from the "Adding IP to a Hardware Design" lab by adding
to the existing processor system the AXI-based LCD controller that you built and tested in the two
previous labs, AXI_GPIO. This controller interfaces with logic to control the rotary switch that is on the
evaluation board.
In this lab, the processor system will be an XPS-based project that is a sub-project of a greater Project
Navigator project. In the current design, it is the sole component of the ISE software project. In Project
Navigator, you will expand the design by:
Adding a new top-level design component to the hierarchy
Instantiating the processor system into the new top level
Instantiating other logic that performs a rotary switch decode function
The software for this project is provided as an exported, archived SDK project. You will create a new SDK
workspace and import the archived project.
Working in Project Navigator, you will build out the design to include a new top-level component and other
logic. These files are provided for you. The top-level file lacks an instantiation of the processor system
component. Your task will be to have the tools generate an instantiation template for the processor
system. You will then copy and complete the processor system instantiation in the top-level design
component.
The other logic provided is a rotary switch decoder. The rotary switch outputs two signals that produce a
quadrature square wave. The direction of the rotary switch is determined by which signal is leading or
lagging by its edges:
ROTARY_A: quadrature signal
ROTARY_B: quadrature signal
ROTARY_PRESS: pushbutton output of switch; a third output of the switch
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Switch closures, by nature, are noisy. The logic that is provided debounces all of the input signals,
detects the quadrature motion, and decodes it into two new signals:
ROTARY_EVENT_OUT: a single clock-width pulse that indicates that there was movement on the
switch
ROTARY_LEFT_OUT: at a high level when the last rotation was to the left
ROTARY_PRESS_OUT: debounced pushbutton
The three outputs of the rotary switch logic will be connected to the input pins of the AXI_GPIO
component so that the software can read the states. The ROTARY_EVENT_OUT out signal is a very
short pulse indicating that there has been activity on the switch in the left or right direction based on the
state of ROTARY_LEFT_OUT. Because it is difficult to capture ROTARY_EVENT_OUT in software, it will
also be attached to the interrupt input pin of the processor so that the event can be captured in an
interrupt service routine. And because this signal is a pulse, its nature is such that it is a self-clearing,
edge-triggered, interrupt.
The completed design is illustrated in the following figure.
This lab comprises five primary steps: You will open the project; add the IP to the processor system;
create the software project, integrate into the ISE software project; and, finally, download and test the
design in hardware.
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Opening the Project
Step 1
The working directory for this lab (C:\training\embedded\labs\lab6) has already been
created for you. You will launch this project in the ISE software and complete the
design.
1-1.
Launch Project Navigator and open the project file. Then launch XPS for
the system component.
1-1-1. Select Start > All Programs > Xilinx ISE Design Suite > ISE Design Tools > Project
Navigator to launch Project Navigator.
1-1-2. Click Open Project. Browse to the C:\training\embedded\labs\lab6 directory, select
PS_ZC702.xise, and click Open.
1-1-3. In the Sources window, double-click system to launch XPS.
Adding IP to the Processor System
Step 2
To complete the processor system design, you will add a simple GPIO component and
the custom LCD controller IP that you created and verified in the previous labs. The
GPIO component will attach the rotary switch interface logic that you will add later to the
design.
2-1.
A GPIO peripheral is often an easy way to communicate with simple

external components and sensors. The rotary switch is a good candidate.
In this step, you will add a GPIO component from the IP catalog.
2-1-1. Select the IP Catalog tab in the left window and expand General Purpose IO to view the
available cores under the corresponding entries.

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2-1-2. Double-click the AXI General Purpose IO core (version 1.01.b) in the IP Catalog tab and click
Yes to add this IP to the design.
The XPS Core Config dialog box will automatically appear. You will configure the core in the next
few steps.
2-1-3. To properly document the embedded system, change the name of the newly added GPIO to
Rotary_Switch_3Bit in the Component Instance Name Field.
2-1-4. Because you want to use only one channel, leave the Enable Channel 2 option de-selected.
2-1-5. Expand Channel 1 to view Channel 1-related configurable parameters.
2-1-6. Enter 3 in the GPIO Data Channel Width box.
You need only three inputs from the rotary switch logic in the ISE software.
2-1-7. Enter 1 for TRUE in the Channel 1 is Input Only box.
Figure 6-2: Setting Configurable Parameters

Using the input-only option reduces the logic required to implement the component by leaving out
the output and 3-state enable registers.
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2-1-8. Click OK.

The Instantiate and Connect IP dialog box appears. The default selection is to automatically
connect the GPIO to the AXI interconnect. Because there is only one AXI interconnect in the
system, you can leave this selection unchanged.
Figure 6-3: Auto-Connect GPIO to AXI Interconnect

2-1-9. Click OK.
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2-2.
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The LCD_IP peripheral that was created in the "Building Custom AXI IP for
an Embedded System" lab will be added to the embedded system in this
step.
2-2-1. Select the IP Catalog tab in the left window and expand Project Local pcores > USER to view
the available custom, user-generated cores.

2-2-2. Double-click the LCD_IP core in the IP Catalog tab and click Yes to add this IP to the design.
The XPS Core Config dialog box will automatically appear. You will configure the core in the next
few steps.
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2-2-3. Scroll to the bottom of the All tab and verify that the value of the C_BOARD_TYPE parameter is
ZC702 and the C_LCD_WIDTH parameter is 11.
Figure 6-5: Configuring the User-Defined Parameters of the LCD_IP Peripheral

Note: It is here that you can override the default setting for the target evaluation board and
interface width.
2-2-4. Click OK.
The Instantiate and Connect IP dialog box appears. The default selection is to automatically
connect the GPIO to the AXI interconnect. Because there is only one AXI interconnect in the
system, you can leave this selection unchanged.
2-2-5. Click OK.
2-3.
To properly document the embedded system, change the name of the

newly added custom IP to LCD_2x16.
2-3-1. Change the instance name of the peripheral to LCD_2x16 by clicking once in the Name column,
typing the new name, and then clicking any other screen object.
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The two newly added components have been configured and attached to
the AXI interconnect. In the next steps, the port signals specific to the
peripheral will be connected.
You will start with the rotary switch GPIO and create a three-bit bus net as
an input to the GPIO and make it external to the system.
2-4-1. Select the Ports tab and expand the Rotary_Switch_3Bit instance.
2-4-2. Right-click in the Net column of the GPIO_IO port of the Rotary_Switch_3Bit instance and make
sure that No Connection is selected.
If this is not the case, click No Connection in the Net column to delete the net. It has been
reported that the configuration wizard may automatically create an external net on the I/O pins of
the GPIO. This is not desired because you will be using the GPIO in input mode only.
Note: If the Net column is not visible, right-click any of the column names and select Net.
2-4-3. Click in the Net column of the GPIO_IO_I port of the Rotary_Switch_3Bit instance to enter edit
mode and then enter Rotary_IN for the net name and then click any other screen object.
2-4-4. After the net name has been selected, click again in the Net column and select Make External
from the Net column drop-down list.
Figure 6-6: GPIO Input Port Connection Added to Instance

You have just brought the data lines from the Rotary_Switch_3Bit GPIO component up the
processor hierarchy to the top level, where they will later (in Project Navigator) be attached to the
rotary switch logic.
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2-4-5. Click in the Net column of the S_AXI_ACLK port of the Rotary_Switch_3Bit instance and verify
that clk_75mhz is selected. If not, select clk_75mhz as the net name from the Net column dropdown list.
Figure 6-7: Connecting the Clock Net to the IP Peripheral
2-5.
In the same manner, bring the output pins of the LCD controller external to
the embedded processor system.
2-5-1. In the Ports tab, expand the LCD_2x16 instance.

2-5-2. Click in the Net column of the LCD_2x16 instance and select Make External from the Net column
drop-down list next to the lcd port signal.
The net named LCD_2x16_lcd is generated and appears external in the External Ports list.
Figure 6-8: LCD_2x16_lcd External Port Connection Added to Instance

A new port, LCD_2x16_lcd _pin, external to the processor system, is generated.
You have just brought the LCD interface lines from the LCD_2x16 component up the processor
hierarchy to the top level, where they will later (in Project Navigator) be attached to the external
programmable logic pins to the LCD display.
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2-5-3. Click in the Net column of the S_AXI_ACLK port of the LCD_2x16 instance and verify that
clk_75mhz is selected. If not, select clk_75mhz as the net name from the Net column drop-down
list.
Figure 6-9: Connecting the Clock Net to the IP Peripheral
2-6.
The Add IP Configuration wizard has automatically assigned addresses to

the two peripherals that have been added. It is a good idea to verify this.
2-6-1. Select the Addresses tab and expand processing_system7_0s Address Map. Verify that all
peripherals have assigned addresses.
Figure 6-10: Address Map
2-7.
One of the inputs from the rotary switch signal conditioning module is
producing a pulse, a single clock cycle wide, every time the knob is
rotated. This signal is a great candidate to be an interrupt to the processor.
In this step, you will attach this signal directly to the processor interrupt
input pin.
2-7-1. Select the Ports tab and expand the processing_system7_0 component.
2-7-2. Locate the IRQ_F2P signal in the list.
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2-7-3. Right-click in the Name column of the IRQ_F2P port of the processing_system7_0 instance
and select New Connection.
Figure 6-11: Creating the Processor Interrupt Pin
2-8.
System clocking is a system-level architecture strategy. Programmable

logic system clocking with a processor system usually involves a clockcrossing domain.
Clock generation can be generated in the programmable logic system OR
generated in the processor system and sent to the programmable logic. In
this lab, the latter method will be used because the design has included a
clock generation module.
The AXI peripheral interface clock will be used as the fabric system clock
and will be made an output of the embedded system.
2-8-1. Select the Ports tab and expand the clock_generator_0 component.
2-8-2. Locate the CLKOUT1 port that is connected to the clk_75mhz signal in the list.
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2-8-3. Click in the Net column and select Make External from the Net column drop-down list.
Figure 6-12: Making the CLKOUT1 Port External

2-8-4. At the top of the Ports tab, expand External Ports and for the external
clock_generator_0_CLKOUT1_pin signal, set the class to CLK.
2-8-5. In the External Ports list, change the formal port name of the signal to CLK_FPGA.
Figure 6-13: Making the Clock External for Fabric Use

2-8-6. In the Project tab from the left pane of the window, double-click the system.mhs file available
under Project Files.
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2-8-7. At line no. 36, connect the Rotary_IN[2] signal to the interrupt port of the processor.
Figure 6-14: Connecting the Interrupt Signal to the Processor

2-8-8. Save the system.mhs file.
Question 1
Ports are initially No Connection. What happens in the MHS file when you select New Connection? What
happens if you type in a net name instead?
Question 2
What does making a net name external do in the MHS file?
Question 3
Where are the default values for peripheral parameters found?
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Creating the Software Project
Step 3
An SDK software project has been created and archived for you. In this step, you will
learn how to import an archived software project into a new workspace. The imported
project will be compiled and an ELF file will be generated.
3-1.
The SDK project can be created in either Project Navigator or in XPS. In

this lab, you will be launching SDK from XPS. With either method, the SDK
software development flow is the same.
3-1-1. Select Project > Export Hardware Design to SDK.

This export function will create a targeted subdirectory with a hardware description file in it. SDK
uses this hardware description file to build a software platform. In this way, the SDK software
project can be associated with a XPS project at arms length.
3-1-2. Accept the default directory location and click Export & Launch SDK.
Figure 6-15: Exporting the Processor Hardware and Launching SDK

The directory location for the launch is fixed as ..\SDK\SDK_Export located in the XPS project
directory. This directory contains the hardware description in XML format.
3-1-3. Choose the same location to place the software project
C:\training\embedded\labs\lab6\system\SDK.
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Once selected, this workspace directory should not move because the SDK project file pointers
are referenced by absolute directory location.
Figure 6-16: Choosing the SDK Workspace Location
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Your software team has been busy writing the software for this project.
They have taken advantage of the feature to develop software
independently from the hardware in SDK. The finished software project was
archived. In this step, you will import the SDK project that the software
team exported to a zip file.
3-2-1. In SDK, select File > Import. Expand the General folder, select Existing Projects into
Workspace, and click Next.
Figure 6-17: Importing an SDK Project

3-2-2. Select the Select Archive file option and click Browse. Browse to the
C:\training\embedded\support directory, select lab6_software.zip, and click Open.
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3-2-3. Make sure that the lab6-bsp software platform, lab6-app application project, and zynq_fsbl_0
application are all selected. Click Finish.
Figure 6-18: Selecting an Archive File to Import

It will take a minute or two for the software platform to build. The workspace will be built in the
default location of the C:\training\embedded\labs\lab6\system\SDK directory.
The project should automatically build without errors. A successful build is indicated in the
Console tab when the sizes of all of the program segments are displayed before the build
complete message.
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3-2-4. In the C/C++ Projects tab, expand lab6-app > src and double-click the RotarySwitchLCD.c
application to open it.
Figure 6-19: Opening the RotarySwitchLCD.c Application

3-2-5. Examine the RotarySwitchLCD.c source code.
3-2-6. Exit XPS.
Integrating into the ISE Software Project
Step 4
The ISE software project currently has only the processor system component at the top
level. In this step, you will add a new top-level entity to the design and instantiate the
processor system component into it. You will also add logic to decode the movement of
the rotary switch, add and update the user constraints file, and add the software ELF
file.
4-1.
A top-level VHDL file has been provided. It is missing the processor system
component instantiation. Another component file that conditions the rotary
switch sensor is provided in its entirety. In this step, you will add both files
to the ISE software project.
4-1-1. Select Project > Add Copy of Source. Browse to the C:\training\embedded\support directory,
select Rotary_LCD_TOP.vhd, and click Open.
4-1-2. Click OK to accept the adding of the file to the project with Association to All flows.
4-1-3. In the same way, add the rotary_switch.vhd design file, located in the same directory.
This module is for debouncing the switch contacts and decoding the movement of the rotary
switch.
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4-1-4. In the Hierarchy window, verify that Rotary_LCD_TOP.vhd appears at the top level of the design,
as indicated by the three-square icon next to the file name.
Figure 6-20: Top Level of Design

Notice that system (the processor) is not part of the top-level design. This is because it has not
been instantiated into the design. You will perform this in the next step.
4-1-5. If Rotary_LCD_TOP.vhd is not set as the top level, right-click Rotary_LCD_TOP.vhd and select
Set as Top Module.
4-2.
In this step, you will create an instantiation template for the system
embedded processor component and copy-and-paste the VHDL component
declaration and port map statement into the top-level Rotary_LCD_TOPMB.vhd module at the specified, commented locations.
In the Hierarchy window, you may have noticed that the system component
is outside of the designs hierarchical tree. This is because it needs to be
instantiated in the top level of the design. Once properly instantiated, the
ISE tool will re-generate the hierarchical view.
4-2-1. In the Hierarchy window, select system. In the Processes window, expand Design Utilities and
double-click View HDL Instantiation Template. Click OK in the To Instantiate the Embedded
Processor System dialog box.
4-2-2. Copy the system component and attribute statements.
4-2-3. In the Hierarchy window, double-click the Rotary_LCD_TOP.vhd file to open it.
4-2-4. After the comment at line 65, paste the system component and attribute statements.
4-2-5. In the same way, copy-and-paste the system instantiation statement after the comment at line
121.
Note that this statement is incomplete because local signals have not been included in the port
map. A completed Rotary_LCD_TOP.vhd is printed at the end of this lab.
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4-3.
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The port map instantiation template for the processor system does not
contain the names of the actual port parameters needed to hook the
signals in the system component to the rest of the design.
Connect the port map of the Inst_system component instance of system to
the following port assignments.
Inst_system: system PORT MAP(
CLK_N => CLK_N,
CLK_P => CLK_P,
reset_pin => reset_pin,
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
LEDs_8bit_GPIO_IO_O_pin => LEDs_8bit_GPIO_IO_O_pin,
Rotary_Switch_3Bit_GPIO_IO_I_pin => Rotary_db,
LCD_2x16_lcd_pin => LCD_2x16_lcd_pin,
CLK_FPGA => clk
);
4-3-1. Enter the port assignments as described above.

In many cases, the actual signal name is the same as the formal, so you can copy-and-paste it.
4-3-2. Save and close the Rotary_LCD_TOP.vhd file.
4-4.
The user constraint file contains pin placement information and timing
constraints for the programmable logic.
Because the rotary switch and LCD peripherals have been added, a second
UCF file, which constrains the programmable logic pin numbers, has been
provided. In this step, you will add this file to the project and then
implement the complete design.
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4-4-1. Select Project > Add Copy of Source. Browse to the C:\training\embedded\support directory,
select system_rotary.ucf, and click Open.
4-4-2. Click OK to accept the adding of the file to the project with Association to the implementation
flow.
4-4-3. In the Hierarchy window, select Rotary_LCD_TOP.vhd. In the Processes window, double-click
Generate Programming File.
The tool chain will be started with XST synthesis followed by implementation (translate, map,
place and route), finishing with BitGen.
This will take about seven to nine minutes. There will be some warnings that can be safely
ignored. At the end of this process, a bitstream file (.bit file extension) will be created.
You are now ready to download the design onto the board.
Note: There is a bug in the tool, which fails due to the bmm file creation. But it does generate the
BIT file.
Question 4
What is the value of Project Navigator being able to create an instantiation template for the processor
design?
Downloading and Testing the Design
Step 5
In this final step, you will use the ELF files, download the design into hardware, and
operate the system.
5-1.
Connect the ZC702 board to your machine. Open a terminal in SDK to view
the output of the software application. (Follow the instructions in the
"Adding and Downloading Software" lab to set up the board and SDK
terminal).
5-1-1. Select Xilinx Tools > XMD Console to start the XMD debugger to download and run the
program. In the shell, type the following commands in sequence:
connect arm hw
dow system/SDK/zynq_fsbl_0/Debug/zynq_fsbl_0.elf
download the bootloader file
con
continue or start execution
stop
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fpga -f rotary_lcd_top.bit -debugdevice devicenr 2

download the bit file
dow system/SDK/lab6-app/Debug/lab6-app.elf
download the application file
con
Run the lab6-app program
stop
5-1-2. Rotate the rotary switch and observe the behavior of the LEDs and also displayed in the SDK
Terminal window.
Various messages are sent to the LCD via the custom AXI peripheral that you created. When the
rotary switch is pressed and the LED pattern is 0x80 (right-most LED on), the program exits.
The locations of the rotary switch and LEDs are shown in the following figure.
Figure 6-21: Location of Rotary Switch and LEDs

5-1-3. Exit the ISE software.
Conclusion
In this lab, you integrated a processor system with other non-processor-related logic. The processor
system was treated as another component in a greater design.
Xilinx recommends using Project Navigator (or PlanAhead software) as the basis for your design. Add
a processor module and design the processor system in XPS and the software application in SDK.
Project Navigator will generate a processor instantiation template for the processor module that can be
incorporated with other logic in your design.
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Answers
1. Ports are initially No Connection. What happens in the MHS file when you select New Connection?
What happens if you type in a net name instead?
When New Connection is selected, XPS creates a new net base on the name of the peripheral
instance concatenated with the formal port name. You can override this by typing in a net name
yourself.
2. What does making a net name external do in the MHS file?
Making a net name external puts a global Port instance at the beginning of the MHS file. A new
component port signal of the original net name concatenated with _pin is created. This new port will
be visible as a connection to the processor system.
The port name will be the formal name on the processor instance in Project Navigator. This name can
be changed in the External Ports list.
3. Where are the default values for peripheral parameters found?
In the MPD file of the IP.
4. What is the value of Project Navigator being able to create an instantiation template for the processor
design?
This saves time via the generation of component and port map statements that can be copied and
pasted (Verilog is also supported). The template shows the formal port names of the signals that
make up the processor component. You would otherwise have to locate them manually in the MHS
file.
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Building Custom AXI IP for an Embedded System
Lab 7: Building Custom AXI IP for an

Embedded System
Introduction
This lab guides you through the process of adding a custom AXI peripheral to a processor system using
the Create and Import Peripheral (CIP) wizard.
Objectives
Create an XPS project for the purpose of designing a custom bus peripheral
Create a custom IPIC using the Create and Import Peripheral (CIP) wizard
Modify the MPD and PAO skeleton files created by the CIP wizard
Create and implement user-defined peripheral port signals
Create and implement user-defined peripheral parameters
Use the Project Navigator project created by the CIP wizard to author the peripheral design
Check the design HDL syntax
Procedure
The purpose of this lab is for you to design and build a custom AXI peripheral that can control the onboard LCD display that is used on many of the Xilinx evaluation boards. The challenge will be to
implement a design that is largely insensitive to the different board hardware requirements.
The lab will illustrate a design flow targeted for building AXI interface peripherals. A dummy project will be
created in XPS that will hold only the created peripheral. The Create and Import Peripheral (CIP) wizard
will be used to generate the peripheral pcores directory structure, skeleton design files, an ISE software
development project, and a Bus Functional Model (BFM) design/project (subject of subsequent lab). The
actual peripheral design development work will take place via the ISE software flow that will be created by
the CIP wizard. The purpose of this CIP wizard-created ISE software project is to provide a design
authoring environment and the ability to check HDL syntax. Synthesis and implementation should not be
performed in this lab.
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You will use the Create and Import Peripheral (CIP) wizard of XPS to create a user peripheral IP Interface
(IPIC) and then modify the generated skeleton VHDL user design code to add the necessary code to
implement the LCD interface.
Figure 7-1: Parameterizable LCD Controller for AXI Interconnect

Evaluation boards: KC705 (Kintex-7 FPGA), ZC702 (Zynq 7020 EPP), or custom (user defined).
In order to make the design more flexible, you will define user parameters that will parameterize the
design to the evaluation hardware board being used and the data width of the LCD module. Two different
Xilinx evaluation boards are addressed, the KC705 and ZC702. All of these boards use the same LCD
display. Additionally, you will include a provision to support custom boards that can be specified by the
user.
The LCD display, two lines of 16 characters, is available from many vendors using an industry-accepted
(not a formal standard) interface. The LCD supports an 11-wire interface; E, RS, RW, and byte or nibble
data selectable, which means that some interface lines may not be used.
The KC705 and ZC702 boards connect all eleven interface lines to the programmable logic. Assume the
same for the custom board as well.
The software application writes to the LCD in nibble mode. The three control lines on the interface
(Enable, RS, and RW) are bit banged by the software. This makes the interface to the LCD very simple to
implement, in the form of a parallel output. Because the software only requires seven of the eleven bits, it
is necessary to tie the other four high on the KC705, ZC702, or custom boards.
In order to implement one peripheral that will accommodate all boards, you will define two user
parameters C_BOARD_TYPE and C_LCD_WIDTH. The first parameter will define which board is being
used and the second will dictate the width of the LCD interface. These parameters will be mapped to in a
later lab when this peripheral is instantiated into a design.
This lab comprises four primary steps: You will open the project, create a custom AXI peripheral using the
Create portion of the Create and Import Peripheral Wizard, modify the created MPD and PAO files, and,
finally, add the custom peripheral.
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Opening the Project

1-1.
Step 1
In this step you will create a dummy XPS project for the purpose of
designing an AXI-based peripheral. You will start from XPS because this is
the design stage of the peripheral and you will not be implementing the
design. This lab flow will guide you from design inception through
verification of HDL synthesis.
In this step, you will launch Xilinx Platform Studio and create a blank
project named system.xmp in the
C:\training\embedded\labs\lab4\All_Boards directory.
Because you are creating a generic AXI4-Lite peripheral, selecting the
target programmable logic component for this XPS project is not important.
Later, when the component is instantiated into the actual XPS embedded
design, PlatGen will customize the component for the programmable logic
selected in that targeted XPS project.
1-1-1. Select Start > All Programs > Xilinx ISE Design Suite > EDK > Xilinx Platform Studio to
launch XPS.
1-1-2. Click Create New Blank Project.
Figure 7-2: Creating a New Blank Project

1-1-3. In the Create New XPS Project dialog window, browse to the
C:\training\embedded\labs\lab4\All_Boards directory, and accept the default system.xmp project
file. Click Save.
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Because you are just using this project to create an AXI peripheral, any target device can be
used. In a sense, this is just a dummy project. The Create or Import Peripheral wizard will
generate source VHDL for the peripheral dummy. One of the parameters, later passed when the
peripheral is actually instantiated in the design, is the Xilinx programmable logic family part that is
being targeted.
1-1-4. If the target architecture is the Zynq architecture, de-select AXI Clock Generator and AXI Reset
Module. Accept the other entry default settings and click OK.
Figure 7-3: Creating a Blank Project with the Target Device NOT Important
XPS opens to a blank design. If an informational dialog box referring to the IP Catalog appears,
close it.
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Creating a Custom AXI Peripheral

2-1.
Step 2
This step involves invoking the Create and Import Peripheral Wizard to
build the skeleton IPIC, an ISE software development project, and a Bus
Functional Model (BFM) (subject of a subsequent lab).
In the blank XPS design, you will start the Create and Import Peripheral
wizard and create an AXI peripheral named lcd_ip.
2-1-1. In XPS, select Hardware > Create or Import Peripheral to start the wizard.
The Welcome window for the Create and Import Peripheral Wizard appears.
Figure 7-4: Viewing the Welcome Dialog Box

2-1-2. Click Next.
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2-1-3. In the Peripheral Flow dialog box, select Create templates for a new peripheral and click Next.
Figure 7-5: Selecting to Create New Peripheral Templates
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2-1-4. In the Repository or Project dialog box, select To an XPS project, as the tools will have already
made the proper project association, and click Next.
Figure 7-6: Selecting Where to Store the New Peripheral
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2-1-5. In the Name and Version dialog box, enter lcd_ip in the Name field, accept the default settings
for the various versions, and click Next.
Figure 7-7: Naming the Peripheral
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2-1-6. In the Bus Interfaces dialog box, select AXI4-Lite and click Next.
Figure 7-8: Selecting the Bus Interface

Note the hyperlink (www.xilinx.com/ipcenter/axi4.htm) to the various AXI-related specifications.
2-2.
So far, the Create and Import Peripheral (CIP) wizard has specified a new
peripheral to be placed in the current XPS project. You will continue with
the wizard and select the features to be generated.
The CIP wizard can also generate a BFM simulation platform for later
peripheral simulation (performed in the "BFM Simulation" lab) and an ISE
software project as a peripheral development environment. Both of these
options will be enabled.
When finished, the Create and Import Peripheral Wizard will generate the
VHDL source code and MPD/PAO skeleton files. You will verify the success
of the CIP wizard by ensuring that the new IP appears in the USER section
of the IP Catalog.
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2-2-1. In the IPIF (IP Interface) Services dialog box, select Software Reset and User logic software
register. De-select Include data phase timer and click Next.
Figure 7-9: Selecting the IP Interface
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2-2-2. In the User S/W Register dialog box, accept one software accessible register because you need
only one register to control the LCD. Click Next.
Figure 7-10: Configuring the Number of Software-Accessible Registers in the Peripheral
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2-2-3. In the IP Interconnect (IPIC) dialog box, review the settings.
Figure 7-11: Reviewing the Default IPIC Signal

This dialog box displays the default IPIC signals that are available for the user logic based on the
previous selection.
In this lab, you do not require any of the optional unchecked signals,
2-2-4. Click Next.
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2-2-5. In the Peripheral Simulation Support dialog box, select Generate BFM simulation platform and
click Next.
Figure 7-12: Selecting the Option to Generate a BFM Simulation Platform

This option generates the simulation platform for the next lab.
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2-2-6. In the Peripheral Implementation Support dialog box, select Generate ISE and XST project files
to help you implement the peripheral using XST flow and click Next.
Figure 7-13: Selecting Optional Implementation File Generation

This option creates an ISE software project to help you to write HDL files to implement this
peripheral.
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2-2-7. Review the summary of the peripheral that will be created and click Finish.
Figure 7-14: Reviewing the Summary

2-2-8. Select the IP Catalog tab in XPS and expand Project Local pcores.
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2-2-9. Observe that the new lcd_ip peripheral appears under the USER section of the IP Catalog.
Figure 7-15: Updated Entry in the IP Catalog
Question 1
What IPIC interfaces are you expecting to be generated?
Question 2
What are the names of the HDL files generated? Where are they located?
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Modifying the MPD and PAO Files

3-1.
Step 3
In this step, you will modify the skeleton MPD file that was created in Step
2. Normally, you would also modify the PAO file. However, this design does
not need any other design files.
Every embedded processor system component requires an MPD file that
specifies component port signals, user implementation parameters, and
build options.
The CIP wizard created a skeleton MPD file. As a result, most of the work
has been performed by the CIP wizard. All that is needed is for you to add
any user IP-specific ports and parameters to the file.
3-1-1. Select File > Open and browse to the

C:\training\embedded\labs\lab4\All_Boards\pcores\lcd_ip_v1_00_a\data directory.
3-1-2. Select lcd_ip_v2_1_0.mpd and click Open.
You may have to select All Xilinx Files from the Files of type drop-down list.
3-1-3. Add the following lines anywhere under the ## Generics for VHDL or Parameters for Verilog
section (see the figure below):
PARAMETER C_BOARD_TYPE = KC705, DT = STRING
PARAMETER C_LCD_WIDTH = 7, DT = INTEGER, RANGE = (1:15)
You can also copy-and-paste these lines from the lcd_ip_v2_1_0-mpd-file-snippet.txt file in the
C:\training\embedded\support directory.
These lines inform the system of user parameters. The first parameter passes as a VHDL generic
string the type of board that will be used. This will later be used as a conditional generate to
differentiate between evaluation board hardware. The second parameter indicates the width of
the LCD signal interface.
3-1-4. Add the following line anywhere under the ## Ports section (see the figure below):
PORT lcd = "", DIR = O, VEC = [0: (C_LCD_WIDTH -1)]
This line informs the system that an uncommitted output bus exists and should be displayed in
the Ports tab of the System Assembly View tab.
Question 3
What do the "" in the user port statement indicate?
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3-1-5. Verify the changes that you made.
Figure 7-16: Modified MPD File

3-1-6. Save and close the lcd_ip_v2_1_0.mpd file.
3-2.
The PAO file dictates the order of synthesis for the files that make up the
peripheral. They must be in a hierarchical order with the top-level module
at the bottom of the file. Because the lab design is simple, it will be part of
the user_logic.vhd file that was created by the CIP wizard and is already
specified in the PAO file. No changes to this file will be necessary.
3-2-1. Open the lcd_ip_v2_1_0.pao file in the

C:\training\embedded\labs\lab4\All_Boards\pcores\lcd_ip_v1_00_a\data directory.
3-2-2. View its contents.
Figure 7-17: PAO File (No Need to Modify)

Because you are completing your design in the user_logic.vhd file and do not have any other
HDL files to add, the skeleton PAO that was generated is complete.
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3-2-3. Exit XPS.
Question 4
If other HDL resource files needed to be added, between which lines in the file would they be located?
Adding the Custom IP to the HDL Files
Step 4
In this last step, you will launch the ISE software project that was created by the Create
and Import Peripheral Wizard. This project contains all of the files that make up the
peripheral.
You will modify the user_logic.vhd file to place the necessary logic to interface with the
LCD. Normally, you would instantiate the top level of the controlling logic that forms an
interface to the IPIC in this file. With lab time being short, you will just implement this
logic in the user_logic.vhd file.
The ISE software gives the designer an environment to add files, edit, check syntax,
and simulate submodules. You should not attempt to implement the design because it is
only an AXI peripheral, a fragment of the entire design.
4-1.
User custom ports and parameters must be added to the top level of the
embedded component and then instantiated in the lower levels of the
design to the user_logic.vhd module.
In this step you will add the user-defined parameters, the LCD port signal,
and its port and generic mapping to the lcd_ip-IMP component (the
lcd_ip.vhd file).
4-1-1. Launch the ISE Project Navigator software, browse to the

C:\training\embedded\labs\lab4\All_Boards\pcores\lcd_ip_v1_00_a\devl\projnav directory, and
open the lcd_ip.xise project.
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4-1-2. In the Hierarchy window, expand the various components and familiarize yourself with the design.
Figure 7-18: Custom AXI4-Lite Peripheral in the ISE Software
Question 5
Examine the Hierarchy window. What do all of these components represent?
4-1-3. Double-click lcp_ip - IMP to open it.

4-1-4. Add the two user-defined parameters C_BOARD_TYPE and C_LCD_WIDTH to the entity generic
statement under the --USER generics added here comment.
You can copy and paste the code from the lcd_ip_v2_1_0-vhdl-code-file-snippet.txt file located in
the C:\training\embedded\support directory.
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4-1-5. Add the user-defined port lcd of width (0 to C_LCD_WIDTH -1) to the entity port statement under
the --USER ports added here comment.
Figure 7-19: Adding Parameters and the User Port LCD

4-1-6. Add a generic mapping statement for the user-defined parameters under the --USER generics
mapped here comment.
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4-1-7. Add a port mapping statement to actually make the connection to the LCD under the --USER
ports mapped here comment.
Figure 7-20: Adding the Port Mapping Statement

4-1-8. Save and close the lcd_ip.vhd file.
4-2.
In this step, the custom ports and parameters will be added to the
user_logic.vhd module.
In a typical design you would also instantiate your top-level design in this
module. Due to time constraints, you will place simple code in this file that
will demonstrate a design of a single write only register. The length and
format for this register uses the custom parameters to set the register
length and configuration.
4-2-1. In the Hierarchy window, double-click USER_LOGIC_I user_logic - IMP (user_logic.vhd) to

open it.
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4-2-2. Add the two user-defined parameters C_BOARD_TYPE and C_LCD_WIDTH to the entity generic
statement under the --USER generics added here comment.
You can copy-and-paste the code from the lcd_ip_v2_1_1-vhdl-code-file-snippet.txt file located in
the C:\training\embedded\support directory.
4-2-3. Add the user-defined port lcd of width (0 to C_LCD_WIDTH -1) to the entity port statement under
the --USER ports added here comment.
Figure 7-21: Adding the User-Defined Parameters and LCD Port Definition
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4-2-4. Add the user logic under the --USER logic implementation added here comment.
Figure 7-22: Adding the User Logic

Because this design is simple, there is not much user logic. Normally, you would place a
component instantiation in this file to your logic.
4-2-5. Save and close the user_logic.vhd file.
4-3.
The XST synthesis tool can be used to check the syntax of the modified
user_logic.vhd. Actual synthesis and implementation is not performed
because these operations are performed by PlatGen and Project Navigator
when the new peripheral is instantiated in an actual design.
4-3-1. In the Hierarchy window, select the lower-level USER_LOGIC_I component.

4-3-2. In the Processes window, double-click Check Syntax.
4-3-3. Fix any errors until the syntax properly verifies.
4-3-4. Open the user_logic.vhd file, examine the code, and answer the questions below.
Question 6
Examine the entity port statement. List the IPIC signals that are used.
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Question 7
Of the IPIC signals listed in the previous question, which ones are tied to a constant level and why?
Question 8
In Step 4-2, two VHDL generate statement were added to the user_logic.vhd file. What are the criteria for
generated logic implementation?
Question 9
What is the name of the register that is actually holding the value placed on the LCD output lines?
4-3-5. Exit the ISE software.
Conclusion
Use the Create and Import Peripheral (CIP) wizard to build an IPIC interface to your user logic. The
wizard creates the necessary folder structure, skeleton HDL files, and adds the PlatGen files (MPD, PAO)
to the project directory.
After creating a peripheral, use the Project Navigator project that the CIP wizard generated to add
additional code to the peripheral design under the user_logic.vhd file. Bring up any user-defined
parameters and I/O to the top-level peripheral file. The XST synthesis tool can also be used to check the
design HDL code syntax.
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Answers
1. What IPIC interfaces are you expecting to be generated?
Reset/MIR Write to reset peripheral, read Machine Identification Register. One address decode for
a 32-bit register.
2. What are the names of the HDL files generated? Where are they located?
The files generated are lcd_ip.vhd and user_logic.vhd. They are located in the
C:\training\embedded\labs\lab4\All_Boards\pcores\lcd_ip_v1_00_a\hdl\vhdl directory.
3. What do the "" in the user port statement indicate?
The left side of the port assignment is the net name to assign the signal to. A "" indicates a null
assignment. This will default as a No Connection in the Ports tab of the System Assembly View tab
for the lcd signal.
4. If other HDL resource files needed to be added, between which lines in the file would they be
located?
Between lines 8 and 9. They would be hierarchal below user_logic.vhd and above all of the libraries.
5. Examine the Hierarchy window. What do all of these components represent?
The top-level file, lcd_ip.vhd, and the lower-level file, user_logic.vhd, were generated for you based
on the selections that you made in the Create and Import Peripheral Wizard.
The other files are instantiations of the IPIC components that make up this interface. At this point, you
add your logic components to user_logic.vhd.
6. Examine the entity port statement. List the IPIC signals that are used.
Bus2IP_Clk
Bus2IP_Reset
Bus2IP_Data
Bus2IP_BE
Bus2IP_RdCE
Bus2IP_WrCE
IP2Bus_Data
IP2Bus_RdAck
IP2Bus_WrAck
IP2Bus_Error
7. Of the IPIC signals listed in the previous question, which ones are tied to a constant level and why?
IP2Bus_Error is tied to 0. There will never be a peripheral error for this design.
8. In Step 4-2, two VHDL generate statement were added to the user_logic.vhd file. What are the criteria
for generated logic implementation?
The generate statements are based on the C_BOARD_TYPE parameter, which will be passed down
from the top level. This parameter makes the logic implementation based on the evaluation board that
is used. The KC705, ZC702 and Custom evaluation boards are currently supported. More could be
supported with additional generate statements.
The C_LCD_WIDTH parameter specifies the width of the lcd interface, which will vary based on the
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evaluation board selected. The width options are three LCD control lines plus either a four-bit or
eight-bit LCD data bus.
9. What is the name of the register that is actually holding the value placed on the LCD output lines?
slv_reg0
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Basic System Implementation

Lab 1: Basic System Implementation

Cortex-A9 processor core

GPIO interface to drive five LEDs located next to each pushbutton

GPIO interface to input the five pushbutton array

UART as an input/output device

Triple timer counter (TTC)

GPIO interface to drive a two-line LCD

Add Xilinx-provided or custom peripherals to a processor design

Generate the hardware implementation bitstream file

Connect the target board for download

Configure the Zynq EPP and run a sample application program

Basic System Implementation

General Flow for this Lab

Implementing a Processor Design Using the Processor Configuration

Begin the lab by opening a new PlanAhead software project.

Basic System Implementation

1-1-2. Click Create New Project and click Next.

Figure 1-1: Creating a Project

Basic System Implementation

Figure 1-2: Assigning the Project Name and Location

Basic System Implementation

Figure 1-3: Selecting the Evaluation Board

Figure 1-4: Finishing the New Project Wizard

Basic System Implementation

The PlanAhead GUI will be launched.

1-2-1. In Flow Navigator, Click on Add Sources (

The Add Sources Wizard will be launched.

Figure 1-5: Adding a New Processor Project Source

Basic System Implementation

1-2-4. In the Module Name field, enter system. Click OK.

Figure 1-6: Creating a New Embedded Processor Project Source

Figure 1-7: Adding a Processing System Instance

Basic System Implementation

Figure 1-8: Processor System Architecture

The Zynq Processing System Configuration tab provides a graphical

Quad SPI (flash memory interfaces)

DDR3 (memory interfaces)

Basic System Implementation

1-3-1. Click the Import Zynq Configurations.

Figure 1-9: Importing Zynq EPP Configurations

Figure 1-10: Selecting a Configuration Template

Basic System Implementation

The IOPs that are configured are displayed in different colors.

Figure 1-11: IOPs Configured (Supported by the ZC702 Board)

Basic System Implementation

Figure 1-12: Zynq PS MIO Configurations (Supported by the ZC702 Board)

Basic System Implementation

Figure 1-13: Selecting the I/O Peripherals

Basic System Implementation

Figure 1-14: DDR3 Memory Configuration

Basic System Implementation

Figure 1-15: System Assembly View of IP Catalog

Figure 1-16: Instantiate and Connect IP Dialog Box

Basic System Implementation

The quick connection method is executed by clicking the hollow shape.

Figure 1-18: Selecting axi_interconnect_1

Figure 1-19: Adding the LEDs_8bit to the Address Map

Basic System Implementation

1-3-14. Verify that the memory size of the peripheral is 64K.

Figure 1-20: Ports of Added Instances

Figure 1-21: GPIO_out Port Connection Added to Instance