LABORATORY EXERCISE 4

CMOS Inverter Layout

Objectives
To construct the layout (device-level implementation) of the CMOS inverter
To be acquainted with the capabilities of Electric as a layout editor tool
To simulate the dynamic behavior of the CMOS inverter using the layout-extracted
netlist
Introduction
The layout, which is the final design for fabrication, is the lowest abstraction level in the
design hierarchy for digital systems. It is the accurate physical representation of the device
conforming to constraints imposed by the manufacturing process, the design flow, and the
specifications as verified through simulations. A layout-extracted netlist includes parasitic
resistances and capacitances for more accurate simulations.
In this exercise, the layout of the CMOS inverter that was designed in Exercises 1 and 2 will
be implemented. The trainees are strongly encouraged to compare the simulation results
obtained in Exercise 2 with the data that will be gathered in this exercise.
Procedure
Layout
1. Load Electric.
2. Open the library Exercise.
3. Setup Electric for layout entry. Follow instructions in the Layout section of the Training
Manual: Setting the Layout Technology and Changing the Lambda Size.
4. Create new facet inverter_lay in library Exercise with layout as the facet view. Make
sure that the current technology is mocmossub.
5. Layout the CMOS inverter according to the design rules given in the Training Manual.
Figure 4 is a sample layout of a CMOS inverter. Before proceeding with the layout
implementation, the trainees are strongly encouraged to read the transistor layout tips
given in the Tips section of the Training Manual.
Note: Lp, Ln = 0.35m; Wp = 3.2m; Wn = 0.8m

6. Add the export pins. Label each pin properly. Follow instructions in the Layout section
of the Training Manual.
7. After doing the layout, check for any design rule violation. Click on Tools DRC
Hierarchical Check.
8. If no violations are reported save the inverter layout and close its design window.
Simulation
9. Create new facet inverter_lay_tst with schematic as the facet view. Make sure that
the current technology is schematic, analog.
10. Click on Edit New Facet Instance. Choose library
inverter_lay{lay} from this library. Click on the design window.

Exercise.

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11. Click on Export Re-Export Everything. Add other necessary components for
simulation. Please refer to Laboratory Exercise 2 for these components.
12. Save the schematic. Create a SPICE netlist and simulate the circuit using WinSpice.
Follow instructions in the Simulation section of the Training Manual.
13. Complete the table below by varying the width of the PMOS transistor. Round off your
answers to two decimal places.
Note: To view and edit the inverter layout while in the inverter_lay_tst schematic, select the inverter icon
instance in the design window and press Ctrl-D. To go back to the inverter_lay_tst schematic window,
simply press Ctrl-U.

WN
0.80m
0.80m
0.80m

WP
3.20m
1.60m
0.80m

PHL

PLH

fall

rise

Note: Refer to Exercise 2 for the determination of the delay-time parameters.

Figure 4. Layout of a CMOS inverter.

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