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Design Project
By: Brendan Bartels & Adam Cha
Project
Project 12 Self-Defined: Reverse Polish Calculator
16 Button Inputs
Handles 10-bit unsigned numbers
Only Addition and Subtraction
Result displays on four 4-digit seven-segment displays
Example usage
If you want: 2 + 40 = 42
Type: <2> <enter> <4> <0> <+>
Verilog Design
Verilog Simulation
RTL Synthesis
Placement and Route
Post-Layout Simulation
First Attempt...
LVS Passed
Post-layout Simulation wouldnt work
Virtuoso would only import the cell as a functional block instead of a schematic (which
cant be simulated)
Reason: Virtuoso wont import schematics when assign statements are present
New Strategy
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Design
Digit Shifter
ALU
Controller
Master Mux
Design
Digit Shifter
ALU
Controller
Master Mux
Master Mux
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Master Max
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Master Mux
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Design
Digit Shifter
ALU
Controller
Master Mux
Design
Digit Shifter
ALU
Controller
Master Mux
Design
Digit Shifter
ALU
Controller
Master Mux
Design
Digit Shifter
ALU
Controller
Master Mux
Release
Button
Append
Number
Load
R2 -> R3
Decide
Add
Sub
Load
R1 -> R2
Load
R2 -> R1
Load
R0 -> R1
Load
R3 -> R2
Clear
R0
Design
Digit Shifter
ALU
Controller
Master Mux
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Design
Digit Shifter
ALU
Controller
Master Mux
Driver
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Calculator
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Dimensions:
485u x 441u
DRC and LVS
passed
Driver
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Dimensions:
571u x 562u
DRC and LVS
passed
Calculator
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Driver
1.
2.
3.
4.
5.
6.
Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation
Final Integration
Total Components
Calculator circuit
Driver Circuit
4-digit 7-segment Display
Button Input (User Interface)
Final Integration
Total Components
Calculator circuit
Driver Circuit
4-digit 7-segment Display
Button Input (User Interface)
China Young Sun LED Technology Co., LTD Data Sheet Cont.
Final Integration
Total Components
Calculator circuit
Driver Circuit
4-digit 7-segment Display
Button Input (User Interface)
Final Integration
Questions?