Introduction to VLSI Design (EECE 6080C)

Mini Project

Task Allocation Report

Design
of
Serial by Parallel Multiplier

Srikar Datta Canchi

Sudheer Ram Thulasi Raman

Project Coordinator
Electrical Engineering & Computing Systems
College of Engineering & Applied Science
University of Cincinnati
canchisd@mail.uc.edu
513-432-8215

Electrical Engineering & Computing Systems

College of Engineering & Applied Science
University of Cincinnati
thulassm@mail.uc.edu
513-602-3286

Name of the chip: UCBMUL 3240

Date: 10/11/2016

Project Description:
The mini project that is assigned to our group is Serial by Parallel Multiplier. We
met on Monday and discussed the problem and the following tasks and subtasks were
assigned to each of us.
Tasks:
1: Design the logic using VHDL, enhance its Timing and functionality and perform
analyses on delays.
Sub-Tasks:
a) Design the black box model. -Will be done by both. -Will complete by 7pm,
10/13.
b) Design white box model, which includes all the components like, full adders,
flip-flops and shift registers. -Will be done by Srikar and submitted to
Sudheer. -Will complete by 7pm, 10/14.
c) Write a VHDL code for these blocks behaviorally and make a bit-sliced unit
structurally. -Will be done by Sudheer and submitted to Srikar. -Will
complete by 7pm, 10/16.
d) Write testbench and compute delays. -Will be done by Srikar and submitted to
Sudheer. -Will complete by 7pm, 10/17.
e) Adjust these models to functionally give the output. -Will be done by Sudheer
and submitted to Srikar. -Will complete by 7pm, 10/18.
2: Implementation of Slices to realize the function with n-bits inputs in VHDL its
Timing and functional analysis.
Sub-Task:
a) Initial code is done for 4-bit. So would realize the logic for 8-bit -Will be done
by Srikar and submitted to Sudheer. -Will complete by 7pm, 10/20.
b) Try for higher value of n. -Will be done by Sudheer and submitted to Srikar.
-Will complete by 7pm, 10/24.
3: Design the circuit in HSPICE and simulate to get it functionally work.
Sub-Task:
a) Implement the obtained n-bit and get it done in HSPICE. -Will be done by
Srikar and submitted to Sudheer. -Will complete by 7pm, 10/26.
b) Timing analysis and optimizing. -Will be done by Sudheer and submitted to
Srikar. -Will complete by 7pm, 10/28.

4: Layout for the design and optimizing using Eulers paths.

Sub-Task:
a) Basic layouts for these designs. -Will be done by Srikar and submitted to
Sudheer. -Will complete by 7pm, 10/31.
b) Optimize the layouts for the design, by applying stacking and cascading
concepts. -Will be done by Sudheer and submitted to Srikar. -Will complete
by 7pm, 11/04.
5: Routing and Packaging the design.
Sub-Task:
a) Routing the IO pads to layout. -Will be done by Srikar and submitted to
Sudheer. -Will complete by 7pm, 11/06.
b) Packaging and final placements. -Will be done by Sudheer and submitted to
Srikar. -Will complete by 7pm, 11/09.
6: Testing and configuring.
Sub-Task:
a) Unit testing of all the sub parts. -Will be done by Srikar and submitted to
Sudheer. -Will complete by 7pm, 11/11.
b) System testing and optimizing. -Will be done by Sudheer and submitted to
Srikar. -Will complete by 7pm, 11/12.
7: Report and documentation.
Sub-Task:
a) Report till step 3. Will be done by Srikar and submitted to Sudheer. -Will
complete by 7pm, 11/13.
b) Report till step 6. Will be done by Sudheer and submitted to Srikar. -Will
complete by 7pm, 11/13.
8: Report submission: 11/14.
9: Demo and Tape-Out: 11/16.

Milestones:
1)
2)
3)
4)
5)
6)
7)
8)

8-bit VHDL simulation by 10/18

n-bit VHDL simulation by 10/24
HSPICE Circuit design by 10/28
Layout design by 11/04
Placement and Routing by 11/09
Testing by 11/12
Documentation by 11/13
Tape-out by 11/16