Design Preparation for Scan Test

Tessent Scan

Silicon Test and Yield Analysis

D A T A S H E E T
FEATURES:
Provides intelligent scan insertion
and connection.
Supports Mux-DFF, Clocked-Scan,
LSSD, and mixed design styles.
Performs extensive design rules
checking to identify testability
trouble spots early in the design
cycle.
Automatically corrects many
common testability problems.
Supports layout-based scan
ordering for optimal chain layout.

Tessent Scan inserts scan test structures into the netlist. The output is a design ready for ATPG
and pattern compression.

Inserts IEEE 1500 compliant test

structures to enable block-based
testing strategies for SoC designs.

Ready for Scan Testing

BENEFITS:

Mentor Graphics Tessent Scan turns your gate-level netlist into a design that
is completely ready for scan testing and pattern compression. Although scan test
is the most thorough method of manufacturing test, the effectiveness of the
automatic test pattern generation (ATPG) tool can be limited by the
implementation of the scan structures. Tessent Scan generates and adds the most
effective scan architecture for your design. Not only does Tessent Scan perform
scan flop replacement and stitching, but it also analyzes your circuit for possible
test limitations, performs test-related design rule checks (DRCs), and
automatically corrects errors. Additionally, Tessent Scan facilitates ATPG with
TestKompress and FastScan by generating the required input dofile for these
tools.

Maximizing Test Coverage

Tessent Scan identifies flops in your design that can be changed to scannable
flops. It then replaces those flops and stitches them together into balanced
chains for optimal scan testing. The tool runs a comprehensive set of DRCs to
ensure that safe operation is maintained when the design is operated in scan
test mode. Multiple clock domains are properly grouped to like chains and
contention is avoided. Tessent Scan can analyze your design and identify the
clocks for you.

Universal Operation
Tessent Scan supports a large variety of scan architectures, including full-scan,
clock sequential, sequential transparent, and structure-based.

w w w. m e nto r. co m /si li co n -y i e l d

Works within any tool

environment to improve test
quality.
Adds the most effective scan
structures to maximize test
coverage.
Availability of Mentor Graphics
award-winning customer support
to ensure success.

Unlike other tools that require a specific set of

homogenous EDA tools for operation, Tessent Scan is
designed to work in all design environments using any
combination of synthesis, place-and-route, and
verification tools. This means that TestKompress and
FastScan will generate consistent high-quality test across
all your design groups. For consistency, Tessent Scan,
TestKompress, and FastScan all use the same DRC set.
If your functional design has shift registers, the tool will
recognize that structure automatically and use it for scan
operation, saving valuable chip area and routing.

Hierarchical DFT Support

Tessent Scans wrapper chain insertion capability provides
the foundation for a core-based, hierarchical DFT
methodology. It supports both dedicated and shared
wrapper cells. Shared wrapper cell analysis handles many
corner cases, which results in fewer dedicated wrapper
cells and lower area overhead.

High Performance
Tessent Scan is designed to handle todays large designs. If
your design is in hierarchical blocks, Tessent Scan can
stitch the subchains into the overall design while
maintaining balanced chains and segregating clock and
power domains.

Testability Analysis and Debug

The DFTVisualizer viewing environment is integrated
within Tessent Scan for viewing and correcting testability
problems. DFTVisualizer shows the design in various views
such as schematic, design structure, waveform, library,
data, hierarchy, and additional views to facilitate viewing
and troubleshooting.

Scannability DRC debugging in the DFTVisualizer viewing

environment.

DFTVisualizers ATPG statistics reporting provides detailed

analysis of untestable faults and classifies them into easyto-recognize categories that simplify the debugging of
low test coverage issues.

Tessent Silicon Test and Yield Analysis

Solutions
Tessent Scan is part of the Mentor Graphics industry- and
technology-leading tool suite for silicon test and yield
analysis. The Tessent suite includes integrated solutions
for test insertion; automatic test pattern generation
(ATPG); on-chip compression; memory, logic, and mixedsignal built-in self-test (BIST); silicon bring-up, and
diagnosis-driven yield analysis. All Tessent tools are
available on UNIX and Linux.

The intuitive interface built into DFTVisualizer also allows

viewing of the session transcript, which includes active
links for design rule violations, logic displays, file editing,
documentation, and gate callouts.
For the latest product information, call us or visit: w w w . m e n t o r . c o m /
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