Texas A&M University

Department of Electrical and Computer Engineering

ECEN 607 Advanced Analog Circuit Design

Techniques, Spring 2016:
Homework #1
Section 600
Due on January 21, 2016

Dr. Edgar Sanchez Sinencio

Adriana C. Sanabria Borbon

424001629

Adriana C. Sanabria Borbon

ECEN 607: Homework #1

Problem 1
Use any size technology and generate the equivalent plot (see around page 21 Lect. #1) of various parameters
versus the inversion level. i.e. fT vs if , power consumption, (W/L) vs if . Also add a trace for Vdsat vs if
in the same plot.
The equations that describe the ACM model are mainly:
p
t gm n(1 + 1 + if )
I=
(1)
2
p
t
2( 1 + if 1)
2 L2

(2)

W
gm
1
p
=
L
Cox t 1 + if 1)

(3)

ft =

Vdsat = t ((

1 + if 1) + 4)

(4)

where I is the transistor drain current, n is the slope factor, gm is the transconductance, t is the thermal
voltage and if is the inversion level.
These parameters can be normalized by the same parameter for an inversion level of 1, and doing a sweep
of the inversion level, we can plot the relations in the figure 1.

Figure 1: Inversion level

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ECEN 607: Homework #1

Problem 2
Extract the parameters of transistors PMOS and NMOS for the ACM model, that is one equation all regions.
See Ref. 6 on Lect. #1. Consider the 65 nm and 180 nm CMOS technology and if = 7. Discuss how the
parameters are extracted. Provide a table summarizing results of the extracted parameters. Discuss the
results.
Normalization current Is :
This parameter can be extracted by biasing the transistor in the saturation or strong inversion and
using the setup of the Fig. 2a and 2b for NMOS and PMOS, respectively.

Is I

I/I
2Vs /t

2
(5)

Assuming I = 40A and I = 4A and the transistor sizes: W/L=2.52u/360n for the 180nm technology and W/l=780n/130n for the 65nm technology. (Keeping the same W/L ratio used in the
characterization performed by [1])

(a)

(b)

Figure 2: Is extraction for 2a NMOS and 2b PMOS transistors

Technology
180nm
65nm

NMOS
621.7nA
992.9nA

PMOS
140.9nA
141.3nA

Threshold voltage Vt0 :

According with the one equation all regions model:
p

p
V p V s = t
1 + if 2 + ln( 1 + if 1)
where

(6)

VG Vt0
(7)
n
when the condition that for if = 3 or I = 3 Is VG = Vt0 satisfies. So, the setup of the Fig. 3a and
3b is used in simulation.
Vp

Problem 2 continued on next page. . .

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ECEN 607: Homework #1

(a)

(b)

Figure 3: Vt0 measurement setup for 3a NMOS and 3b PMOS transistors.

Technology
180nm
65nm

NMOS
420.59mV
355.2mV

(a)

PMOS
-413.3mV
-333.6mV

(b)

Figure 4: Vp simulation 2a NMOS and 2b PMOS

Pinch-off voltage Vp and the slope factor n:
In order to find this two parameters the setup of the Fig and 4a and 4b are used:

Problem 2 continued on next page. . .

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ECEN 607: Homework #1

After sweep Vp the values of Vg and n are plotted:

180nm:

(a)

(b)

Figure 5: Vg and n 5a NMOS 5b PMOS using 180nm technology

65nm:

(a)

(b)

Figure 6: Vg and n 6a NMOS 6b PMOS using 65nm technology

Body effect coefficient : From the model, the body effect coefficient is expressed as:
p
= (n 1) 2 2 f + Vp

(8)

when 2f is approximately 0.7V. Using the values from the Vp and n characterization:
180nm NMOS: for VG B = 1, Vp = 478.49mV and n=1.19, then:

= (1.19 1) 2 0.7 + 0.478 = 0.41V 1/2

(9)

180nm PMOS: for VG B = 1, Vp = 304.31mV and n=1.25, then:

= (1.25 1) 2 0.7 + 0.304 = 0.50V 1/2

(10)

Problem 2 continued on next page. . .

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ECEN 607: Homework #1

65nm NMOS: for VG B = 1, Vp = 525.47mV and n=1.19, then:

= (1.19 1) 2 0.7 + 0.525 = 0.42V 1/2

(11)

65nm PMOS: for VG B = 1, Vp = 393.39mV and n=1.17, then:

= (1.17 1) 2 0.7 + 0.393 = 0.35V 1/2

(12)

Mobility 0 and :
The mobility can be extracted by simulating the setup on the Fig. 7a and 7b, where the transistor is
biased to operate in the linear region, so Vds = 100mV and The voltage source at the gate is swept
between 2 Vt0 and Vdd .
=

0
1 + (VG Vt0 )

(13)

So when VG = Vt0 then = 0 .

(a)

(b)

Figure 7: extraction for 7a NMOS and 7b PMOS transistors

Then, the curve is linearised it means, the slope A and the intersection with the vertical axis B are
extracted.
180nm:
NMOS:
Line equation: y=287.8*x+333.39, A=287.8, B=333.39.
0 =

1
1
=
= 1240cm2 /V s
Cox (W/L) B
345.3nF/cm2 (7) 333.39

= 0 Cox

W
A = (1240cm2 /V s)(345.3nF/cm2 )(7)(278.8) = 0.86V 1
L

(14)

(15)

PMOS:
Line equation: y=839.08*x+2359.6, A=839.08.8, B=2359.6.
0 =

1
1
=
= 175cm2 /V s
2
Cox (W/L) B
345.3nF/cm (7) 2359.6

Problem 2 continued on next page. . .

(16)

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ECEN 607: Homework #1

(a)

(b)

Figure 8: extraction 8a NMOS and 8b PMOS for 180nm.

= 0 Cox

W
A = (175cm2 /V s)(345.3nF/cm2 )(7)(839.08) = 0.35V 1
L

(17)

65nm:

Cox =

ox
3.9 8.854 1012
= 1.86F/cm2
=
tox
1.85 109

(18)

NMOS:

(a)

(b)

Figure 9: extraction 9a NMOS and 9b PMOS for 65nm.

Line equation: y=689.94*x+156.25, A=689.94, B=156.25

0 =

1
1
=
= 573.47cm2 /V s
Cox (W/L) B
1.86F/cm2 (6) 156.25

= 0 Cox

W
A = (573.47cm2 /V s)(1.86F/cm2 )(6)(689.94) = 0.79V 1
L

Problem 2 continued on next page. . .

(19)

(20)

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ECEN 607: Homework #1

PMOS:
Line equation: y=3598.69*x+4368.25, A=3598.69, B=4368.25.
0 =

1
1
=
= 20cm2 /V s
Cox (W/L) B
1.86F/cm2 (6) 4368.25

= 0 Cox

W
A = (20cm2 /V s)(1.86F/cm2 )(6)(3598.69) = 0.8V 1
L

(21)

(22)

Sigma
This parameter is associated with the DIBL (Drain Induced Barrier Lowering) that is an effect more
noticeable in the weak inversion operation.
SIGM A = (Lef f )2

(23)

being the variation of the threshold voltage with Vs and Vd.

In order to measure this parameter, the transistor size is set to the minimum, I=0.1*Is and VD is
swept from 200mV to 500mV.

(a)

(b)

Figure 10: Sigma extraction a for NMOS and b for PMOS.

Figure 11: NMOS and shows PMOS for 180nm.

Problem 2 continued on next page. . .

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ECEN 607: Homework #1

Figure 12: a NMOS and b shows PMOS for 65nm.

Summary:
Technology
Is[nA]
Vt0[mV]
n
(
[V 1/2)]
0 [cm2 /V s]
[V 1 ]
Sigma[a]

NMOS-180n
621.7
420.59
1.19
0.41
1240
0.86
400.85

PMOS-180n
140.9
-413.3
1.25
0.5
175
0.35
498.41

NMOS-65n
992.9
355.2
1.19
0.42
573
0.79
222.25

PMOS-65n
141.3
-333.6
1.17
0.35
20
0.8
278.96

Table 1: Parameters
As expected, the mobility, the normalization current and the Vto are larger for the NMOS than the PMOS
transistors. However, the threshold voltage and the mobility are in general smaller for the 65 nm technology
compared with the 180nm technology. Other parameters as , and n are similar for both technologies.
This characterization is dependent on the aspect ratio of the transistors, what makes difficult to provide an
exact value but in general gives a good approximate of the magnitudes.

Problem 3
a) Design, using conventional quadratic saturation transistor equation, a simple two stage transconductance
amplifier for the following specs and using 0.18um technology
AV0 > 60dB
CM RR > 70dB
GBW 4M Hz
P M > 45 deg
OutputSwing > 1.5V
CL = 20pF
P D < 500W
Feel free to use your design obtained in ECEN 704
From previous characterization of the NMOS and PMOS for a L = 360nm: V tp = 0.412, V tn = 0.476,
KN = 130.16A/V 2 and Kp = 36.5A/V 2 .
Problem 3 continued on next page. . .

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ECEN 607: Homework #1

Since we have the load capacitor and in order to have a phase margin greater than 60, the second pole
has to be located at least at 1.73 times the GBW. Assuming a GBW of 5MHz to have a safe margin.
p2 = 1.73(2 5 106 ) = 54.34 106

(24)

For the OTA miller the second pole is determined by:

p2 =

gm8
CL

(25)

So we can find the transconductance of the transistor M8 as:

gm8 = p2 CL = 1.73(2 5 106 ) 20 1012 = 1.08 103

(26)

The compensation capacitor can have the same size of the load capacitor, but for the layout purposes
having 20pF consumes a big area. For that reason, the CC is chosen to be 5pF. Since the GBW is
determined by the ratio between the transconductance of the differential pair and the compensation
capacitor, then:
gm1, 2 = 2 5 106 5 1012 = 157.07 106

(27)

The compensation capacitor also determine the position of the RHP zero:
z=

gm8
1.08 103
=
= 216 106 rad/s
CC
5 1012

(28)

In order to met the power specification considering the supply voltages Vdd=1.8V and GND=0; since
the total power is given by:
P = VDD IDD

(29)

The maximum available current is:

IDD =
Problem 3 continued on next page. . .

500W
= 277.77A
1.8V
10

(30)

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ECEN 607: Homework #1

That current does not consider the biasing current and corresponds to the sum of the Itail or I(M6) and
the current flowing through the second stage.
The size of the input pair transistors can be derived from the transconductance and the current (half of
Itail). In order to have a realizable size, Itail is assumed 40A


W
L


=
1,2

gm2
(157.07 106 )2
=
= 4.74 5
2Cox ID
2 (130 106 )(20 106 )

rds1, 2 =

1
1
= 294K
=
ID
0.17 20 106

(31)

(32)

Due to the output swing specification the Veff of M7 and M8 has to keep small below 200mV each.
 
gm
(1.08 103 )
W
=
=
= 197
(33)
L 8
V ef f Cox
0.15 (36.5 106 )
1
1
=
= 117K
ID
0.17 50 106

(34)

2ID7
2 50 106
=
= 667 106
V ef f
0.15

(35)

rds8 =

gm7 =


W
L


=
7

rds7 =

gm
= 667 106
=
= 34
Cox V ef f
0.15(130 106

(36)

1
1
= 117K
=
ID
0.1750 106

(37)

The transistors of the active load of the first stage M3 and M4 are sized to have an small Veff:
2ID3,4
2 20 106
=
= 200 106
V ef f
0.2

gm3, 4 =


W
L


=
3,4

rds4 =

gm
200 106
=
= 27
Cox V ef f
0.2(36.5 106 )

1
1
=
= 294k
ID4
0.17 20 106

(38)

(39)

(40)

With the calculated values, the gain:

Av = gm1, 2(rds2||rds4) gm8(rds7||rds8) = 94.24 106 (294k||294K) 652 106 (117k||117k) (41)

Av = 827 = 58.35dB

(42)

Finally the tail transistor M6 is sized to be able to handle the current and to have an small Veff, using
the equations:
gm6 =
Problem 3 continued on next page. . .

2 40 106
2ID7
=
= 400 106
V ef f
0.2
11

(43)

Adriana C. Sanabria Borbon

ECEN 607: Homework #1

W
L


=
6

gm
400 106
=
= 15.38
Cox V ef f
0.2(130 106 )

(44)

1
1
= 147k
=
ID6
0.17 40 106

(45)

rds6 =
The CMRR is given by the expression:

CM RR = 2 gm3 rds6 gm1 (rds2||rds4) = 2 200 106 147 103 94.24 106 (249/2) 103 (46)

CM RR = 56.77dB

(47)

The design was adjusted by simulation in order to met the specs and at the same time make sure all
transistors were operating in the saturation region. All final sizes are specified in the table 2 except for
the compensation capacitor CC that, as mentioned before, was chosen to be 5pF. The table also include
the actual inversion level in which the transistors are operating, considering the sizes, current and the
parameters extracted from the characterization.
Transistor
L[m]
W [m]
if

M1,M2
0.36
1.8
23

M3,M4
0.36
20
14

M5
0.36
20
12

M6
0.36
7.3
11

M7
0.36
20.5
13

M8
0.36
110
17

Table 2: OTA sizing

Simulation results:
The simulation results are presented in the Figures 13, 14 and 15.

Figure 13: AC response: DC Gain, GBW and Phase margin

The power consumption is 255.96W that is pretty conservative recalling that the power budget is 500W .
b) Repeat the design but using one equation, all region transistor model, reduce the power consumption as
much as possible while meeting the above specs.

Problem 3 continued on next page. . .

12

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ECEN 607: Homework #1

Figure 14: Common mode Gain

Figure 15: Output Swing

In order to reduce the power consumption and according with the Fig 1, the inversion level should be
chosen small as possible. We know that the gm/Id is inversely proportional to the inversion level, it
means that in the weak inversion level the gm/Id is maxima. For that reason, the transistors M1, M2
and M8 are designed for an inversion level of 2. The other transistors are sized with a large W/L ratio
in order to reduce the power as well. In the case of the output stage we need to consider a small if that
provides an small Vdsat and an output common mode level near to Vdd/2.
With these considerations and using the parameters extracted from the characterization in the ACM
model equations, first we verify that the frequency at the chosen inversion level is enough, for L=360nm
(twice the minimum size):
ft =

p
t
2( 1 + if 1) = 9.7GHz >> 4M Hz
2
2 L

(48)

Then, using the equation:

W
gm
1
p
=
L
Cox t 1 + if 1)
we find the aspect ration of M1 and M2:19.26, and the aspect ratio on M8: 939.

Problem 3 continued on next page. . .

13

(49)

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ECEN 607: Homework #1

Then the currents for the same transistors are calculated using the equation:
p
t gm n(1 + 1 + if )
I=
2

(50)

and as the result IDS1,8 = 6.63A and IDS8 = 45A

Finally, the equation:
p
Vdsat = t (( 1 + if 1) + 4)

(51)

provide an idea that for an small Vdsat 0.15V the inversion level is 21.
After tuning the design in order to reduce the current, meet the specs and fix the proper biasing conditions,
the transistor sizes and the actual inversion levels are shown as bellow:
Transistor
L[m]
W [m]
if

M1,M2
0.36
6.84
2.5

M3,M4
0.36
60
27

M5
0.36
35
7

M6
0.36
5.2
6.68

M7
0.36
26
0.7

M8
0.36
480
2.7

As was the goal, all the transistors are operating in the moderate inversion except for the current mirror
that has a larger if in order to provide a good current copy.
The performance of the circuit is shown in the figures 16 and 17. All the specs are met.

Figure 16: AC Response:DC Gain, GBW and Phase margin

The current that the VDD source provides to the amplifier without considering the biasing branch is
88.24A so the power is 158.83W . The power consumption is actually 0.62 times the power achieved
with the quadratic equation design.

14

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ECEN 607: Homework #1

Figure 17: Output Swing

15

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ECEN 607: Homework #1

Problem 4
Design using one equation all region equation, an Ahuja current buffer amplifier that meets the specs in Prob.
3, except the SR but consumes at least 50% less than the one designed in 704 and can handle a 10X larger
load capacitance. Provide a table summarizing the results of Probs. 2 and 3, include in the comparison also
active area, PSR at DC and 100 KHz, 1% settling time, CMRR (0), SR-, and SR+. Comment these results
and trade-offs.
This design is based on the previous one, but now we add the current buffer and the correspondent biasing
circuitry as shown in the figure 18.

Figure 18: OTA miller with Ahuja compensation

Since the GBW is still determined by the first stage transconductance, the first stage remains almos same,
but now the second stage transconductance can be relaxed in order to save power. The current buffer was
sized in order to keep small Vdsat and a proper biasing.
The transistor sizes are tuned by simulation and the sizes are summarized on the table 3.
Transistor
L[m]
W [m]
if

M1,M2
0.36
8
2

M3,M4
0.36
60
2

M5
0.36
40
6

M6
0.36
5.8
6

M7
0.36
8
7

M8
0.36
38
10

M9
0.36
7
16

M10
0.36
4
4

M11
0.36
3
5

Table 3: Ahuja compensated OTA

The simulation results show that the circuit meets the specifications even for a CL=200p it is 10 times the
initial spec.
The current consumed by the circuit is 42.06A so the power is 75.7W .
The three designs are compared in the next table:
*The area includes the capacitor vncap of area 150mx62.2m = 9336m2 .
The three designs met the specs and in addition were characterized for othe performance metrics. Using the
ACM model and a low inversion level saves power significantly compared with the quadratic equation design,
keeping comparable GBW, Gain,CMRR and output swing but sacrificing on Slew rate, what is expected
because of the reduction on the current that charges the capacitor. The Ahuja compensation showed to
be really effective on handling large load capacitors and still met the same specs. The PSR is extended in
frequency for the Ahuja compensation, but in this design is lower than the conventional OTA Miller because
Problem 4 continued on next page. . .

16

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ECEN 607: Homework #1

Figure 19: AC response CL=20pF

Figure 20: AC response CL=200pF

Figure 21: Output Swing

Problem 4 continued on next page. . .

17

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Specification
Gain [dB]
GBW [MHz]
Phase margin [deg]
CMRR [dB]
Power [uW]
Output swing[V]
Area[m2 ]
Settling time[ns]
PSR @DC [dB]
PSR @100kHz[dB]
SR+ [V/s]
SR- [V/s]

ECEN 607: Homework #1

OTA Miller
61.4
4.61
60.12
63.47
255.96
1.43
9400.9
250.19
-62.74
-36.57
10.58
8.05

OTA Miller ACM

67.05
4.18
60.77
74.54
158.83
1.52
9620.6
289
-71.42dB
-32.39
2.67
2.40

Ahuja Compensated
63.61
24(20p),4.06(200p)
85.26(200p)
66.3
75.7
1.42
9398.6
958
-5
-5
36
0.8

of the small size of the current mirror, sized in that way in order to save power. In terms of area the main
contribution for the three designs is the capacitor area, however the design using ACM is the larger than the
one using quadratic equation because the transistor sizes are in general larger to operate with a low inversion
level. The Ajuha compensated OTA design has also an small area in comparison, because the transistors on
the output stage where reduced to save power.

References
[1] Coitinho, R.M.; Spiller, L.H.; Schneider, M.C.; Galup-Montoro, C., A simplified methodology for the
extraction of the ACM MOST model parameters, in Integrated Circuits and Systems Design, 2001, 14th
Symposium on. , vol., no., pp.136-141, 2001

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