Logic and Computer Design M Mano Sol

Solutions to Problems Marked with a * in
Logic and Computer Design Fundamentals, 3rd Edition
Chapter 1
2004 Pearson Education, Inc.
1-1.*
Decimal, Binary, Octal and Hexadecimal Numbers from (16)10 to (31)10
Dec
Bin
Oct
Hex
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1-4.*
( 1001101 ) 2 = 2 6 + 2 3 + 2 2 + 2 0 = 77
( 1010011.101 ) 2 = 2 6 + 2 4 + 2 1 + 2 0 + 2 1 + 2 3 = 83.625
( 10101110.1001 ) 2 = 2 7 + 2 5 + 2 3 + 2 2 + 2 1 + 2 1 + 2 4 = 174.5625
1-7.*
Decimal
Binary
Octal
369.3125
101110001.0101
561.24
Hexadecimal
171.5
189.625
10111101.101
275.5
BD.A
214.625
11010110.101
326.5
D6.A
62407.625
1111001111000111.101
171707.5
F3C7.A
1-8.*
a)
7562/8
945 + 2/8
=>
945/8
118 +1/8
=>
118/8
14 + 6/8
=>
14/8
1 + 6/8
=>
1/8
1/8
=>
0.45 8
3.6
=>
0.60 8
4.8
=>
0.80 8
6.4
=>
0.20x8
3.2
=>
(7562.45)10
(16612.3463)8
b)
(1938.257)10
(792.41CA)16
c)
(175.175)10
(10101111.001011)2
a)
(673.6)8
(110 111 011.110)2
(1BB.C)16
(1110 0111 1100.1011)2
(7174.54)8
1-9.*
b)
(E7C.B)16
Problem Solutions Chapter 1

c)
(310.2)4
a)
(BEE)r = (2699)10
(11 01 00.10)2
1-13.*
11 r 2 + 14 r 1 + 14 r 0 = 2699
11 r 2 + 14 r 2685 = 0
By the quadratic equation: r = 15 or 16.27
ANSWER: r = 15
b)
(365)r = (194)10
3 r 2 + 6 r 1 + 5 r 0 = 194
3 r 2 + 6 r 189 = 0
By the quadratic equation: r = 9 or 7

ANSWER: r = 7
Solutions are: r = 8, 2.618..., 0.381...
ANSWER: The chicken has 4 toes on each foot (half of 8).
1-15.*
(694)10
(0110 1001 0100)BCD
(835)10
(1000 0011 0101)BCD
0001
0110
1001
0100
+1000
+0011
+0101
1111
1100
1001
+0110
+0110
+0000
0101
1 0010
1001
1-16.*
a) (0100 1000 0110 0111)BCD
b) (0011 0111 1000.0111 0101)BCD
(4867)10
(1001100000011)2
(378.75)10
(101111010.11)2
1-23.*
a)
(101101101)2
b)
(0011 0110 0101)BCD
c)
0011 0011
0011 0110
0011 0101ASCII

Chapter 2
2-1*
a)
XYZ = X + Y + Z
Verification of DeMorgans Theorem

X
XYZ
XYZ
X+Y+Z
X + YZ = ( X + Y ) ( X + Z )
b)
The Second Distributive Law

X
YZ
X+YZ
X+Y
X+Z
(X+Y)(X+Z)
XY + YZ + XZ = XY + YZ + XZ
c)
X
XY
YZ
XZ XY+YZ+XZ XY
0
YZ
0
XZ XY+YZ+XZ
0
2-2.*
a)
XY + XY + XY
X+Y
= ( XY + XY ) + ( XY + XY )
= X( Y + Y) + Y(X + X)
= X+Y

b)
AB + BC + AB + BC
X+Y+Z
XY + XZ + YZ
= ( AB + AB ) + ( BC + BC )
= B(A + A) + B(C + C)
= B+B
=1
c)
Y + XZ + XY
= Y + XY + XZ
= ( Y + X ) ( Y + Y ) + XZ
= Y + X + XZ
= Y + (X + X )( X + Z)
= X+Y+Z
d)
XY + YZ + XZ + XY + YZ
= X Y + YZ ( X + X ) + XZ + XY + YZ
= XY + XYZ + XYZ + XZ + XY + YZ
= XY ( 1 + Z ) + XYZ + XZ + XY + YZ
= XY + XZ ( 1 + Y ) + XY + YZ
= XY + XZ + XY ( Z + Z ) + YZ
= XY + XZ + XYZ + YZ ( 1 + X )
= XY + XZ ( 1 + Y ) + YZ
= XY + XZ + YZ
= B C + ABC
2-7*.
a)
XY + XYZ + XY = X + XYZ = ( X + XY ) ( X + Z ) = ( X + X ) ( X + Y ) ( X + Z )
= ( X + Y ) ( X + Z ) = X + YZ
b)
X + Y ( Z + X + Z ) = X + Y ( Z + XZ ) = X + Y ( Z + X ) ( Z + Z ) = X + YZ + XY
= ( X + X ) ( X + Y ) + YZ = X + Y + YZ = X + Y
c)
WX ( Z + YZ ) + X ( W + WYZ ) = WXZ + WXYZ + WX + WXYZ

= WXZ + WXZ + WX = WX + WX = X
d)
( AB + AB ) ( CD + CD ) + AC = ABCD + ABCD + ABCD + ABCD + A + C

= ABCD + A + C = A + C + A ( BCD ) = A + C + C ( BD ) = A + C + BD
2-9*.
a)
F = ( A + B)(A + B)
b)
F = ( ( V + W )X + Y )Z
c)
F = [ W + X + ( Y + Z ) ( Y + Z ) ] [ W + X + YZ + YZ ]
d)
F = ABC + ( A + B )C + A ( B + C )
2-10.*
Truth Tables a, b, c
X
a)
XYZ + XYZ + XYZ + XYZ
Sum of Minterms:
Product of Maxterms: ( X + Y + Z ) ( X + Y + Z ) ( X + Y + Z ) ( X + Y + Z )
b)
ABC + ABC + ABC + ABC
Sum of Minterms:
Product of Maxterms: ( A + B + C ) ( A + B + C ) ( A + B + C ) ( A + B + C )
c)
WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
Sum of Minterms:
+ W XYZ
Product of Maxterms: ( W + X + Y + Z ) ( W + X + Y + Z ) ( W + X + Y + Z )
( W + X + Y + Z)( W + X + Y + Z)( W + X + Y + Z )
( W + X + Y + Z)( W + X + Y + Z)( W + X + Y + Z )
2-12.*
( AB + C ) ( B + CD ) = AB + ABCD + BC = AB + BC s.o.p.
a)
= B ( A + C ) p.o.s.
X + X( X + Y)( Y + Z) = ( X + X )(X + (X + Y)( Y + Z) )
b)
= ( X + X + Y ) ( X + Y + Z ) p.o.s.
= ( 1 + Y ) ( X + Y + Z ) = X + Y + Z s.o.p.
( A + BC + CD ) ( B + EF ) = ( A + B + C ) ( A + B + D ) ( A + C + D ) ( B + EF )
c)
= ( A + B + C ) ( A + B + D ) ( A + C + D ) ( B + E ) ( B + F ) p.o.s.
( A + BC + CD ) ( B + EF ) = A ( B + EF ) + BC ( B + EF ) + CD ( B + EF )
= A B + AEF + BCEF + BCD + CDEF s.o.p.
2-15.*
a)
1
X
b)
Y
1
Z
XZ + XY
1
1
1
A
c)
B
1
1
C
A + CB
1 1
A 1 1
1
1
C
B+C
2-18.*
a)
b)
1
1
C
1
Y
X
c)
1 1
A
1
Z
m ( 3, 4, 5, 7, 9, 13, 14, 15 )
m ( 3, 5, 6, 7 )
1
1
1
D
m ( 0, 2, 6, 7, 8, 10, 13, 15 )
2-19*
a) Prime = XZ, WX, XZ, WZ
b) Prime = CD, AC, BD, ABD, BC
Essential = XZ, XZ
c) Prime = AB, AC, AD, BC, BD, CD
Essential = AC, BD, ABD
Essential = AC, BC, BD
2-22.*
a) s.o.p. CD + AC + BD
c) s.o.p. BD + ABD + ( A BC or ACD )
b) s.o.p. AC + BD + AD
p.o.s. ( C + D ) ( A + D ) ( A + B + C )
p.o.s. ( C + D ) ( A + D ) ( A + B + C )
p.o.s. ( A + B ) ( B + D ) ( B + C + D )
2-25.*
b)
a)
B
X
A
1
1 X 1
W
1
C
Primes = AB, AC, BC, ABC
Essential = AB, AC, BC
F = AB + AC + BC
c)
Y
1
1
C
X X
1
Z
Primes = XZ, XZ, WXY, WXY, WYZ, WYZ
Essential = XZ
F = XZ + WXY + WXY
X 1
1 X
X X
D
Primes = AB, C, AD, BD
Essential = C, AD
F = C + AD + ( BD or AB )
2-30.*
X Y = XY + XY
Dual (X Y ) = Dual ( XY + XY )
= (X + Y)(X + Y)
= XY + XY
= XY + XY
= XY
LOGIC AND COMPUTER DESIGN FUNDMENTALS INSTRUCTORS MANUAL

Chapter 3
3-4.*
The longest path is from input C or D.
0.078 ns + 0.078 ns + 0.052 ns + 0.078 ns = 0.286 ns
3-9.*
P-Logic
X
Y NAND
NOR
Y NAND
N-Logic
NOR
Y NAND
NOR
3-11.*
C
1 1
1
F = AB + AC
3-24.*(Errata: Replace equations with F = W and G = W Y + WZ. See Fig. 4-10 for decoder diagram/table.)
F = D 0U D 1U D 2U D 3U = D 0U + D 1U + D 2U + D 3U = W ( XY + XY + XY + XY ) = W
G = D 0U D 2U D 1L D 2L = D 0U + D 2U + D 1L + D 3L = W ( XY + XY ) + W ( XZ + XZ )
= WY + WZ

Chapter 4
4-1.*
a)
b)
VDD
F7
F7
F6
F6
F5
F5
F4
F4
F3
F3
F2
F2
F1
F1
F0
F0
4-7.*(Errata: four should be two and 48 should be 32)

D0
D1
D2
D3
D4
D5
D6
D7
D8
DECODER
A0
A1
A2
A0
A1
A2
0
1
2
3
4
5
6
7
D9
D10
D11
D12
D13
D14
DECODER
A3
A4
A0
A1
A2
0
1
2
3
4
5
6
7
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
55
4-10.*
DECODER
A0
A1
A0
A1
0
1
2
3
D0
D1
D2
DECODER
A2
A0
D3
0
1
D4
D5
D3
0
X
X
X
1
D2
0
X
X
1
0
D1
0
X
1
0
0
D0
0
1
0
0
0
A1
X
0
0
1
1
A0
X
0
1
0
1
A1
V
0
1
1
1
1
A0
D1
X
1
D3
D1
1
1
D2
D3
V = D0 + D1 + D2 + D3
1
D0
D0
A0 = D0 ( D 1 + D2 )
1
1
A1 = D0 D 1
4-19.*
8x1 MUX
D(7:0)
D(7:0) Y
0
A(2:0)
S(2:0)
8x1 MUX
D(14:8)
D(6:0) Y
0
D(7)
S(2:0)
A(3)
3 OR gates
4-25.*
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
C
D
F=D
B
A
F=C D
4 x 1 MUX
S0
S1
D0
D1
D2
D3
VDD
F=C D
F=1
56
D2
4-28*
IN
00000
00001
00010
00011
00100
00101
00110
00111
OUT
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
IN
01000
01001
01010
01011
01100
01101
01110
01111
OUT
00 1000
00 1001
01 0000
01 0001
01 0010
01 0011
01 0100
01 0101
IN
10000
10001
10010
10011
10100
10101
10110
10111
OUT
01 0110
01 0111
01 1000
01 1001
10 0000
10 0001
10 0010
10 0011
IN
11000
11001
11010
11011
11100
11101
11110
11111
4-32*
PTERMS
XY
X
YZ
XY
Z
1
2
3
4
5
INPUTS
X Y Z
1
0
1
1
1
0
OUTPUTS
C D E
1
1
4-34*
PTERM
ABD
ABC
ACD
BCD
AD
CD
CD
D
Assume 3-input OR
gates.
1
2
3
4
5
7
8
A
0
0
0
INPUTS
B C
0
0 1
- 0
0 1
0 1
0
PTERM
A
BC
BD
BC
BD
BC D
CD
CD
D
-
1
2
3
4
5
6
7
8
9
-
A
1
57
OUTPUTS
D W X Y Z
1 1 1
1 1
0 1
- 1
1 1
1 1
0 1
1
INPUTS
B C
1 1
1- 0 1
0 1 0
1
0

1
0
1
0
OUT
10 0100
10 0101
10 0110
10 0111
10 1000
10 1001
11 0000
11 0001
4-39*
X1
N1
N2
X2
N6
N3
N4
X3
N5
X4
4-43.*
begin
F <= (X and Z) or ((not Y) and Z);
end;
4-46.*
4-49.*
X1
N1
N2
X2
N6
N3
N4
9 is the highest
priority.
X3
N5
X4
4-53.*
module circuit_4_53(X, Y, Z, F);
input X, Y, Z;
output F;
assign F = (X & Z) | (Z & ~Y);
endmodule
58

Chapter 5
5-2.*
C 1 = T 3 + T 2 = T 1 C 0 + T 2 = A 0 B 0 C 0 + A 0 + B 0 = ( A 0 + B 0 )C 0 + A 0 B 0 = ( A 0 B 0 + C 0 ) ( A 0 + B 0 )
C1 = A0 B0 + A0 C0 + B0 C0
S0 = C0 T4 = C0 T1 T2 = C0 A0 B0 ( A0 + B0 ) = C0 ( A0 + B0 ) ( A0 + B0 ) = C0 A0 B0 + A0 B0
S0 = A0 B0 C0
T3
T1
T4
T2
5-3.*
Unsigned
1001 1100 1001 1101 1010 1000 0000 0000 1000 0000
1s Complement 0110 0011 0110 0010 0101 0111 1111 1111 0111 1111
2s Complement 0110 0100 0110 0011 0101 1000 0000 0000 1000 0000
5-6.*
+36
0100100
36
- 24
1101000
+(24)
- 35
1011101
0100100
+
1101000
10001100
= 12
35
0001100
1011101
- (24)
0011000
= 11
1110101
5-17*
a)
b)
c)
d)
e)
S
0
1
1
0
1
A
0111
0100
1101
0111
0001
B
0111
0111
1010
1010
1000
C4
0
0
1
1
0
S3 S2 S1 S0
1 1 1 0
1 1 0 1
0 0 1 1
0 0 0 1
1 0 0 1
5-18.*
A0
A1
B3
B3
B2
B1
B2
B1
B0
B0
0
Augend
Addend
4-bit Adder
Sum
Cout
A2
B3
B2
B1
B0
Augend
Addend
4-bit Adder
Sum
Cout
A3
B3
B2
B1
B0
Augend
Addend
4-bit Adder
Sum
Cout
S7
S6 S5 S4 S3
S2
5-22.*
5-26.*
S1
S0

Chapter 6
6-6.*
a) There are no setup time violations. There is a hold time violation at 28 ns. There is an input
combination violation just before 24 ns.
b) There are no setup time violations. There is a hold time violation just before 24 ns. There is an input
combination violation just before 24 ns.
c) There is a setup time violation at 28ns.

d) There is a hold time violation at 16ns and a setup time violation at 24ns.
Present state
Input
X=0
Next state
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
000
100
001
110
010
011
111
101
X=1
001
100
010
101
000
111
011
110
State diagram is the combination of the above two diagrams.
6-9.*
00/1
01/0
00/0
11/0 1
0
10/1
11/1
x0/0, 01/1
01/1, 10/0
11/1
3
2
x0/1, 01/0
Format: XY/Z
11/0
6-10.*
SA = B
SB = X A
RA = B
RB = X A
Present state
Input
1/1
Next state
0/0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
Output
1/0
0/1
0/1
1/0
3
0/0
1/1
Format: X/Y
6-14.*
Present state
A
B
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
Input
X
0
1
0
1
0
1
0
1
DA
Next state
A
B
1
A 1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
1
0
DB
B
1
X
DA = AB + AX + BX
DB = AX + BX
Logic diagram not given.
6-15.*
Format: XY/Z (x = unspecified)
Present state
Inputs
Next state
Output
Q(t)
Q(t+1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
X
1
X
1
X
0
X
x1/x
00/0
x1/x
10/1
00/1
10/0
1
Present state
Inputs
Next state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
Output
Present state
Inputs
Next state
0
1
0
1
1
1
0
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
6-23.*
A
D
C
Y
B
C
Clock
6-24.*
a)
S
0
0
1
1
R
0
1
0
1
Q
Q
0
1
1
b)
Format: SR
No Change
Reset
Set
Set
10,11
00, 10, 11
00,01
1
0
01
c)
Present state
A=S
B = SR
Input
Next state
Q(t+1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
1
0
0
1
1
x
0
x
x
x
x
0
0
0
1
0
0
A
S
R
Clock
S
R
Output
6-29.*
2 8
1
00/0
RESET
7 11
x0/0, 01/1
01/0
Reset, 00, 01, 00, 01, 11, x0, x0, 01, 10,
01, 01, 11, 11, 11, 10.
00/1
11/0 1
14
10/1
12 11/1
4
15
01/1, 10/0
11/1
3
13
x0/1, 01/0
6 10
11/0
Format: XY/Z
6-31.*
Clock
J
K
Y
Q
0 ps
50 ns
100 ns
150 ns
This simulation was performed without initializing the state of the latches of the flip-flop beforehand.
Each gate in the flip-flop implementation has a delay of 1 ns. The interaction of these delays with the
input change times produced a narrow pulse in Y at about 55 ns. In this case, the pulse is not harmful
since it dies out well before the positive clock edge occurs. Nevertheless, a thorough examination of such
a pulse to be sure that it does not represent a design error or important timing problem is critical.
6-32.*
library IEEE;
use IEEE.std_logic_1164.all;
architecture mux_4to1_arch of mux_4to1 is

begin
entity mux_4to1 is
port (
S: in STD_LOGIC_VECTOR (1 downto 0);
D: in STD_LOGIC_VECTOR (3 downto 0);
Y: out STD_LOGIC
);
end mux_4to1;
process (S, D)
begin
case S is
when "00" => Y <= D(0);
when "01" => Y <= D(1);
when "10" => Y <= D(2);
when "11" => Y <= D(3);
when others => null;
end case;
-- (continued in the next column)
end process;
end mux_4to1_arch;
6-37.*
library IEEE;
entity jkff is
port (
J,K,CLK: in STD_LOGIC;
Q: out STD_LOGIC
);
end jkff;
case J is
when '0' =>
if K = '1' then
q_out <= '0';
end if;
when '1' =>
if K = '0' then
q_out <= '1';
else
q_out <= not q_out;
end if;
when others => null;
end case;
end if;
end process;
architecture jkff_arch of jkff is

signal q_out: std_logic;
begin
state_register: process (CLK)
begin
if CLK'event and CLK='0' then --CLK falling edge
Q <= q_out;
end jkff_arch;
-- (continued in the next column)
6-39.*
always @(S or D)
begin
if (S == 2'b00) Y <= D[0];
else if (S == 2'b01) Y <= D[1];
else if (S == 2'b10) Y <= D[2];
else Y <= D[3];
module problem_6_39 (S, D, Y) ;

input [1:0] S ;
input [3:0] D ;
output Y;
reg Y ;
end
endmodule
// (continued in the next column)
6-43.*
module JK_FF (J, K, CLK, Q) ;
always @(negedge CLK)

case (J)
0'b0: Q <= K ? 0: Q;
1'b1: Q <= K ? ~Q: 1;
endcase
endmodule
input J, K, CLK ;
output Q;
reg Q;
// (continued in the next column)

Chapter 7
7-4.*
Clock
Reset
Load
C
D
0000
0000
1010
0101
1010
0 ps
40 ns
0000
0101
80 ns
1001 1001
1100 0011
1000 0001
AND
1101 1011
OR
0101 1010
XOR
7-6.*
sl 1010 0110
sr 0010 1001
7-7.*
Connections to MUX data input 0 and data input 3 remain the same. Qi-1 is connected to MUX data input 2 instead of MUX
Data input 1. Finally, 0 is connected to MUX data input 1.
7-8.*
a) 1000, 0100, 0010, 0001, 1000
b) # States = n
+7-16.
*
The equations given on page 337 can be manipulated into SOP form as follows: D1 =
Q1, D2 = Q2 Q1Q8 = Q1Q2Q8 + Q1Q2 + Q2Q8, D4 = Q4 Q1Q2 = Q1Q2Q4 + Q1Q4
+ Q2Q4, D8 = Q8 (Q1Q8 + Q1Q2Q4) = Q8(Q1Q8+Q1Q2Q4) + Q8(Q1 + Q8)(Q1 + Q2
+ Q4) = Q1Q2Q4Q8 + Q1 Q8. These equations are mapped onto the K-maps for Table
7-9 below and meet the specifications given by the maps and the table.
Q2
D1
1 0 0 1
1 0 0 1
Q8 X X X X
1 0 X X
Q1
D2
0 1
0 1
Q4
0 0
0 1
0 1
Q8 X X X X
0 0 X X
Q1
D8
Q2
Q2
D4
Q2
1 0
0 1
Q4
To add the
change D1 to:
enable,
D1 = Q1 EN.
0
1 0
For the other three funcQ4 tions, AND EN with the

expression XORed with
Q8 X X X X
the state variable. The
1 0 X X
circuit below results.
Q1
1 1
Q4
X X
Q8 X X
0 0 X X
Q1
Q1
C
Q2
EN
C
Q4
D
C
Q8
D
C
Clock
7-17.*
Present state
Next state
0
0
0
0
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
a) DB = C
DC = B C
b) DA = BC + AC
DB = A BC + BC
DC = C
7-21.*
C3
Clock
R1
R2
Load
Load
7-23.*
R1
LOAD
C
C2C1C0
Q0
Q1
Q2
Q3
D0
D1
D2
D3
R2
LOAD
C
Q0
Q1
Q2
Q3
D0
D1
D2
D3
Clock
7-28.*
a)
CLK
CTR 4
R2
0
REG 4
D(0-3) Q(0-3)
CI
ADD 4
C1
C1
C2
A(0-3) C(0-3)
B(0-3)
CO
Load
Count
R1
D(0-3) Q(0-3)
CO
R1
b)
REG 4
D(0-3) L Q(0-3)
C1
C2
CI
ADD 4
R2
A(0-3) C(0-3)
B(0-3)
CO
REG 4
D(0-3) Q(0-3)
L
Clock
7-31.*
Replace multiplexer with:
R1
K1
4
R0
4
R2

a) Destination <- Source Registers
R0 <- R1, R2
R1 <- R4
R2 <- R3, R4
R3 <- R1
R4 <- R0, R2
b) Source Registers -> Destination

R0 -> R4
R1 -> R0, R3
R2 -> R0, R4
R3 -> R2
R4 -> R1, R2
c) The minimum number of buses needed for operation of the transfers

is three since transfer Cb requires three different sources.
d)
R0
R1
R2
R3
MUX
R4
MUX
MUX
7-34.*
a) Using two clock cycles, the minimum # of buses is 2 .
b)
R0
R1
R2
R3
MUX
R4
R5
R6
R7
R8
MUX
1000, 0100, 1010, 1101 0110, 0011, 0001, 1000
7-35.*
Shifts:
A
B
C
0
0111
0101
0
1
0011
0010
1
2
0001
0001
1
3
1000
0000
1
4
1100
0000
0
7-36.*
library IEEE;
entity reg_4_bit is
port (
CLEAR, CLK: in STD_LOGIC;
D: in STD_LOGIC_VECTOR (3 downto 0);
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end reg_4_bit;
architecture reg_4_bit_arch of reg_4_bit is
begin
process (CLK, CLEAR)
begin
if CLEAR ='0' then
Q <= "0000";
elsif (CLK'event and CLK='1') then
Q <= D;
end if;
end process;
--asynchronous RESET active Low

--CLK rising edge
end reg_4_bit_arch;
R9
R10
R11
clk
clear
d 0000
1010
q 0000
0101
1010
1111
0101
0000
40
7-39.*
module register_4_bit (D, CLK, CLR, Q) ;
input [3:0] D ;
input CLK, CLR ;
output [3:0] Q ;
reg [3:0] Q ;
always @(posedge CLK or negedge CLR)
begin
if (~CLR)
//asynchronous RESET active low
Q = 4'b0000;
else
//use CLK rising edge
Q = D;
end
endmodule
CLK
CLR
D 0000
Q 0000
0
1010
0101
1010
1111
0101
20
40
0000
60

Chapter 8
8-1.*
S0
Inputs: X1X2
Outputs: Z1Z2
Z1 = 0
Z2 = 0
0
X1
1
S1
Z1 = 0
Z2 = 1
00
10
X1X2
01
11
S2
Z1 = 1
Z2 = 0
00
11
X1X2
01
10
8-2.*
A: 0
B: 1
C: 0
State: ST1
Z: 0
1
1
1
ST1
0
1
0
0
ST2
0
0
1
1
ST3
1
1
0
0
ST1
0
1
1
1
ST2
1
0
0
0
ST3
1
1
1
1
ST1
0
ST2
8-5.*
STA
Reset
STB
STD
X
1
STC
STE
Z
0
X
Z
1
8-8.*
ST1(t + 1) = ST1A + ST2BC + ST3, ST2(t + 1) = ST1A, ST3(t + 1)= ST2(B + C), Z = ST2B + ST3
For the D flip-flops, DSTi = STi(t + 1) and STi = QSTi. Reset initializes the flip-flops: ST1 = 1, ST2 = ST3 = 0.
8-9.*
DY0
State Assignment
ST2
ST3
0 0
0 1
1 0
DY1
ST1
0
ST2
1
ST3
2
2
21
DY0
C
R
Reset
8-11.*
100110 (38)
110101 ( 53)
100110
000000
100110
000000
100110
100110
11111011110 (2014)
100110
110101
000000
100110
100110
0100110
00100110
100110
10111110
010111110
0010111110
100110
1100011110
01100011110
100110
11111011110
011111011110
Init PP
Add
After Add
After Shift
After Shift
Add
After Add
After Shift
After Shift
Add
After Add
After Shift
Add
After Add
After Shift
8-16.*
IN
CLK
LA
A(15:0)
LB
Bit 15
B(14:0)||0
A(14:0)||0
CLK
AR
DY1
Y1
DECODER
C
R
Y1 Y0
ST1
Y0
S 1 MUX 0
BR
CLK
LC
B(15:0)
L
R
CR
Zero
R is a synchronous reset that overides any
simultaneous synchronous transfer.
A
Reset
LA
B
LB
C
LC
G
D
C
R
C
R
LA
C
R
LB
Reset
8-19.*
library IEEE;
entity asm_819 is
port (
A, B, C, CLK, RESET: in STD_LOGIC;
Z: out STD_LOGIC
);
end asm_819;
architecture asm_819_arch of asm_819 is
type state_type is (ST1, ST2, ST3);
signal state, next_state : state_type;
begin
state_register: process (CLK, RESET)
begin
if RESET='1' then--asynchronous RESET active High
state <= ST1;
elsif (CLK'event and CLK='1') then --CLK rising edge
state <= next_state;
end if;
end process;
next_state_func: process (A, B, C, state)
begin
case (state) is
when ST1 =>
if A = '0' then
next_state <= ST1;
else
next_state <= ST2;
end if;
when ST2 =>
if ((B = '1') and (C = '0')) then
next_state <= ST1;
else
next_state <= ST3;
end if;
when ST3 =>
next_state <= ST1;
end case;
end process;
output_func: process (B, state)
begin
case (state) is
when ST1 =>
Z <= '0';
when ST2 =>
if (B = '1') then
Z <= '1';
else
Z <= '0';
end if;
when ST3 =>
Z <= '1';
end case;
end process;
end asm_819_arch;
LC
clk
reset
a
b
c
state st1
st2
st3
st1
st2
st1
st2
st3
st1
z
0
50
100
150
8-20.*
module asm_820 (CLK, RESET, A, B, C, Z) ;
input CLK, RESET, A, B, C ;
output Z ;
reg [1:0] state, next_state;
parameter ST1=2'b00, ST2=2'b01, ST3=2'b10;
reg Z;
//State register
always @(posedge CLK or posedge RESET)
begin
if (RESET) //asynchronous RESET active High
state <= ST1;
else
//use CLK rising edge
state <= next_state;
end
//Next state function
always @(A or B or C or state)
begin
case (state)
ST1: next_state <= A ? ST2: ST1;
ST2: next_state <= (B && ! C) ? ST1: ST3;
ST3: next_state <= ST1;
default: next_state <= ST1;
endcase
end
//Output function
always @(B or state)
begin
case (state)
ST1: Z <= 1'b0;
ST2: Z <= B ? 1'b1: 1'b0;
ST3: Z <= 1'b1;
default: Z <= 0'b0;
endcase
end
endmodule
CLK
RESET
A
B
C
Z
state 00
0
01
10
00
01
50
100
00
01
10
150
00
CHAPTER 9
9-1.*
a) A = 14, D = 8
b) A = 18, D = 16
c) A = 26, D = 32
d) A = 31, D = 8
9-2.
a) 214
b) 219
c) 228
d) 231
9-3.*
(835)10 = (11 0100 0011)2, (15,103)10 = (0011 1010 1111 1111)2
9-4.
Number of bits in array = 216 * 24 = 220 = 210 * 210
Row Decoder size = 210
a) Row Decoder = 10 to 1024, AND gates = 210 = 1024
Column Decoder = 6 to 64, AND gates = 26 = 64
Total AND gates required = 1024 + 64 =1088
b) (32000)10 = (0111110100 000000)2, Row = 500, Column = 0
9-5.
512M = 229,
a) Number of RAM cell arrays = 8

b)
213 x 213 = 226
A26 A27 A28

S0
S1
S2
0 1 2 3 4 5 6 7
Each line is connected to the respective array decoder enable
9-6.
14 row pins + 13 column pins = 227= 128M addresses
9-7.
With 4-bit data, the RAM cell array contains 64M = 226 words.
The number of address pins is 26/2 = 13.
9-8.
Interval between refreshes = 128ms/4096 = 31.25 s
Minimum number of pins = 12
9-9.*
a) 4
b) 19,17
c) 2, 2to4
9-10.
Lines
18 17 16
Lines 0 - 15
Data 0 - 7
Data 8 - 15
3-to-8-Line
Decoder
7
64K x 8 RAM
64K x 8 RAM
8
16
From Read/Write
From Decoder
Data
Address
CS
R/W
8
16
64K x 8 RAM
8
16
Data
Address
CS
R/W
Data
Address
CS
R/W
Data
Address
CS
R/W
64K x 8 RAM
8
16
Out Data 0 - 7
64K x 8 RAM
8
16
64K x 8 RAM
8
16
Data
Address
CS
R/W
Data
Address
CS
R/W
Out Data 8 - 15
9-11.
An SDRAM simultaneously reads the desired row and stores all of the information in the I/O
logic. Next the desired column is read from the I/O logic and the data appears on the output.
During burst transfers, the subsequent data words are read from the I/O logic and placed on
the output. This occurs for the predetermined number of words known as the burst length.
For burst transfers, this is faster since the row has already been pre-read.
9-12.
A DDR SDRAM uses both the positive and negative edges of the clock to transfer data. This
allows the DRAM to transfer twice as much data while keeping the same clock frequency.

Chapter 10
10-2.*
C = C8
V = C8 C7
Z = F7 + F6 + F5 + F4 + F3 + F2 + F1 + F0
N = F7
10-3.*
Cin
X = S0A + S0A
Y = S1 Cin B + S1S0 B + S1S0B + S1S0Cin
A0
D0
A0
D1
B0
C0
D0
D1
S
Adder
D3
S1 S0
C1
X
S1
A1
D0
A1
D1
Adder
Y
S1 S0
B1
C2
D0
D1
S0
D2
D3
10-4.*
Ci
S1
X = A S1 + A S0
Y = B S1 S0 + B S1
S0
Ai
S1 S0
Bi
D0
D1
Bi
D2
Bi
D3
X
FA
Y
CI + 1
10-6.*
a) XOR = 00, NAND = 01,
NOR = 10
XNOR = 11
Out = S1 A B + S0 B + S1AB + S1 S0 B
b) The above is a simplest result.
10-8.*
(a) 0101
(b) 0110
(c)1010
10-10.*
G0
D2
(d) 0110
Gi
G1
(a)
(b)
(c)
R5 R4 R5
R6 R2 + R4 + 1
R5 R0
R5 = 0000 0100
R6 = 1111 1110
(d)
(e)
R5 = 0000 0000
(f)
R5 R0
R4 srConstant
R3 Data in
R5 = 0000 0000
R4 = 0000 0011
R3 = 0001 1011
10-14.*
a) Opcode = 7 bits
b) 20 bits
c) 1,048,576
d) 524288 to +524287

Chapter 11
11-2.*
a) LD
LD
R1, E
b) MOV T1, A
R2, F
c) LD
ADD T1, B
MUL F
MUL R1, R1, R2
MUL T1, C
ST
LD
R2, D
MOV T2, E
LD
SUB
R1, R2, R1
MUL T2, F
SUB
T1
LD
R2, C
MOV T3, D
ST
T1
DIV
R1, R2, R1
SUB
T3, T2
LD
LD
R2, A
DIV
T1, T3
ADD B
LD
R3, B
MOV Y, T1
T1
MUL C
ADD R2, R2, R3
DIV
T1
MUL R1, R1, R2
ST
ST
Y, R1
11-3.*
a) (A - B) x (A + C) x (B - D) = A B - A C +x B D -x
b, c)
PUSH A
A
PUSH B
B
A
SUB
A-B
PUSH A
A
A-B
PUSH C
C
A
A-B
MUL
(A-B)x(A+C)
PUSH B
B
(A-B)x(A+C)
PUSH D
D
B
(A-B)x(A+C)
SUB
B-D
(A-B)x(A+C)
MUL
(A-B)x(A+C)x(B-D)
ADD
A+C
A-B
11-6.*
a) X = 195 208 1 = 14
b) X = 1111 1111 1111 0010
The number is negative because the branch is backwards. The 1

assumes that the PC has been incremented to point to the address
after that of the address word of the instruction.
11-10.*
a) 3 Register Fields x 4 bits/Field = 12 bits.
32 bits - 12 bits = 20 bits. 220 = 1048576
b) 64 < 100 < 128 => 7 bits. 2 Register Fields x 4 bits/Field => 8 bits. 32 bits - 7 bits - 8 bits => 17 Address Bits
11-14.*
b) R0 7B + 4B ,
a) ADD R0, R4
R0 = C6,
C=0
ADC
R1, R5
R1 24 + ED + 0 ,
R1 = 11,
C=1
ADC
R2, R6
R2 C6 + 57 + 1 ,
R2 = 1E,
C=1
ADC
R3, R7
R3 1F + 00 + 1 ,
R3 = 20,
C=0
11-17.*
Result
Register
0110 1001
0011 0100
0110 1000
0011 0100
0110 1000
0011 0100
0110 1000
1011 0100
01101000
OP
SHR
SHL
SHRA
SHLA
ROR
ROL
RORC
ROLC
C
1
1
1
1
1
1
1
0
1
11-19.*
Smallest Number =
0.5
2255
Largest Number
(1 226)
2+255
11-20.*
E
(e)2
+8
+7
+6
+5
+4
+3
+2
+1
0
1
2
3
4
5
6
7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
11-23.*
TEST (0001)16, R
BNZ ADRS
(AND Immediate 1 with Register R)

(Branch to ADRS if Z = 0)
11-25.*
a)
A=
0101 1101
93
B=
0101 1100
- 92
0000 0001
AB =
b) C (borrow) = 0,
Z=0
c) BH, BHE, BNE
11-27.*
PC
SP
TOS
a) Initially
2000
2000
3000
b) After Call
0301
1999
2002
c) After Return
2002
2000
3000
11-30.*
External Interrupts:
1) Hard Disk
2) Mouse
3) Keyboard
4) Modem
5) Printer
Internal Interrupts:
1) Overflow
2) Divide by zero
3) Invalid opcode
4) Memory stack overflow
5) Protection violation
A software interrupt provides a way to call the interrupt routines normally associated with
external or internal interrupts by inserting an instruction into the code. Privileged system
calls for example must be executed through interrupts in order to switch from user to
system mode. Procedure calls do not allow this change.

Chapter 12
12-2.*
a) The latency time = 1.25ns x 6 = 7.5ns.
b) The maximum throughput is 1 instruction per cycle or 800 million instructions per second.
c) The time required to execute is 12 instruction + 6 pipe stages -1 = 17 cycles *1.25ns = 21.25ns
12-6.*
Cycle 1:
PC = 10F
Cycle 2:
PC-1 = 110,
IR = 4418 2F0116
Cycle 3:
PC-2 = 110,
RW = 1, DA = 01, MD = 0, BS = 0, PS = X, MW = 0, FS = 2, SH = 01, MA = 0, MB = 1
Cycle 4:
RW = 1, DA = 01, MD = 0, D0 = 0000 2F20, D1 = XXXX XXXX, D2 = 0000 00000
Cycle 5:
R1 = 0000 2F20
BUS A = 0000 001F, BUS B = 0000 2F01
12-10.*
MOVA R7, R6
IF
DOF
IF
SUB R8, R8, R6
AND R8, R8, R7
EX
4
WB
6
Data Hazard
DOF
EX
WB
IF
DOF
EX
WB
12-12.*
a)
MOV R7,R6
IF
SUB R8,R8,R6
DOF
EX
WB
IF
DOF
EX
IF
DOF
EX
WB
IF
DOF
EX
NOP
AND R8,R8,R7
b)
SUB R7,R7,R6
NOP
BNZ R7,000F
NOP
IF
WB
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
IF
DOF
EX
WB
IF
DOF
EX
IF
DOF
EX
WB
IF
DOF
EX
NOP
AND R8,R7,R6
NOP
OR R5,R8,R5
WB
WB
WB
WB
12-15.*
Time Cycle 1
IF PC: 0000 0001
DOF PC-1: XXXX XXXX IR: XXXX XXXX
EX PC-2: XXXX XXXX BA: XXXX XXXX BB: XXXX XXXX RW: X DA: X MD: X BS: X PS: X MW: X FS: X
WB D0: XXXX XXXX D1: XXXX XXXX D2: XXXX XXXX RW: X DA: X MD: X RX:
Time Cycle 2
IF PC: 0000 0002
DOF PC-1: 0000 0002
IR: 0A73 9800
EX PC-2: XXXX XXXX BA: XXXX XXXX BB: XXXX XXXX RW: X DA: X MD: X BS: X PS: X MW: X FS: X
WB D0: :XXXX XXXX D1: XXXX XXXX D2: XXXX XXXX RW: X DA: X MD: X RX:
SH: XX
SH: XX
Time Cycle 3
IF PC: 0000 0003
DOF PC-1: 0000 0003
IR:A003800F
EX PC-2: 0000 0002
BA: 0000 00020
BB: 0000 0010
RW: 1 DA: 07 MD: 00 BS: 00 PS: X MW: 0 FS: 5 SH: 0F
WB D0: XXXX XXXX D1: XXXX XXXX D2: XXXX XXXX RW: X DA: X MD: X RX:
IF
DOF
EX
WB
Time Cycle 4
PC: 0000 0004
PC-1: 0000 0004 IR: 1083 9800
PC-2: 0000 0003 BA:0000 0010
BB: XXXXXXXX RW: 0 DA: XX MD: XX BS: 01 PS:1 MW: 0 FS: 0
D0: 0000 0010 D1: XXXX XXXX D2: 0000 0000
RW: 1 DA: 07 MD: 00
IF
DOF
EX
WB
PC: 0000 0012

PC-1: 0000 0005
PC-2: 0000 0004
D0: 0000 0010
IF
DOF
EX
WB
Time Cycle 6
PC: 0000 0013
PC-1: 0000 0013 IR: XXXX XXXX
PC-2: 0000 0005 BA:0000 0010
BB: 0000 0000
RW: 1 DA: 05 MD: 00 BS: 00 PS: X MW: 0 FS: 9
D0: 0000 0010 D1: XXXX XXXX D2: 0000 0000
RW: 1 DA: 08 MD: 00
0000 0010
IF
DOF
EX
WB
Time Cycle 7
PC: 0000 0014
PC-1: 0000 0014 IR: XXXX XXXX
PC-2: 0000 0013 BA:XXXX XXXX BB: XXXX XXXX RW: X DA: X MD: X BS: X PS: X MW: X FS: X SH: X
D0: 0000 0010 D1: XXXX XXXX D2: 0000 0000
RW: 1 DA: 05 MD: 00 R8: 0000 0010
SH: 00
Time Cycle 5
IR: 1254 1400
BA:0000 0010
D1: XXXX XXXX
BB: 0000 0010

D2: 0000 0000
RW: 1 DA: 08 MD: 00 BS: 00 PS: X MW: 0 FS: 8

RW: 0 DA: 00 MD: 00 R7:
0000 0010
SH: 00
SH: 00
Time Cycle 8
R5:
0000 0010
Based on the register contents, the branch is taken. The data hazards are avoided, but due to the control hazard, the last two
instructions are executed.
12-18.*
AA3:0
D0
AX3:0
D1
FAA3:0
FAA4
S0
AX4
DA3:0
D0
BA3:0
D1
BX3:0
BX3:0
BA3:0
D0
DA3:0
D1
D2
DX3:0
D2
D3
S1 S0
DX3:0
D3
S1 S0
FBA3:0
FBA4
BX4
FDA3:0
FDA4
DX4
DX0
DX1
DX2
DX3
DX4
12-22.*
(a) Add with carry
Action
R 31 CC 00010
R 16 R [ SA ] + R [ SB ]
if (R31=0) MC AWC5
else MC MC + 1
MC MC + 1 (NOP)
R [ DR ] R 16 + 1
MC IDLE
Address MZ
AWC0
AWC1
01
01
AWC2
AWC3
AWC4
AWC5
CA
02
00
R
M
P M
L
M
W DX D BS S W FS C MA B AX BX CS
1 1F 0 00 0
1 10 0 00 0
0
0
8 0 10 1 00 00 11
2 0 00 0 00 00 00
11 AWC5
0 00 0 00 0
0 0 00 0 1F 00 00
01
01
00
0 00 0 00 0
1 01 0 00 0
0 00 0 00 0
0
0
0
0 0 00 0 00 00 00
2 0 00 1 10 00 11
0 0 00 0 00 00 00
00
01
IDLE
(a) Subtract with borrow

Action
R 31 CC 00010
R 16 R [ SA ] R [ SB ]
if (R310) MC SWB5
else MC MC + 1
MC MC + 1 (NOP)
R [ DR ] R 16 1
MC IDLE
Address MZ
SWB0
SWB1
01
01
SWB2
SWB3
SWB4
SWB5
CA
02
00
R
M
P M
L
M
1 1F 0 00 0
1 10 0 00 0
0
0
8 0 10 1 00 00 11
5 0 00 0 00 00 00
11 SWB5
0 00 0 00 1
0 0 00 0 1F 00 00
01
01
00
0 00 0 00 0
1 01 0 00 0
0 00 0 00 0
0
0
0
0 0 00 0 00 00 00
5 0 00 1 10 00 11
0 0 00 0 00 00 00
00
01
IDLE
12-24.*
Memory Scalar Add (Assume R[SB] > 0 to simplify coding)
Action
R 16 R [ SB ]
R 18 R 0
R 16 R 16 1
MC MC + 1 (NOP)
R 17 R [ SA ] + R 16
MC MC + 1 (NOP)
if (R160) MC MSA2
else MC MC + 1
R 18 M [ R 17 ] + R 18
R [ DR ] R 17
MC IDLE
Address MZ
MSA0
MSA1
MSA2
MSA3
MSA4
MSA5
01
01
01
01
01
01
MSA6
MSA7
MSA8
MSA9
CA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
2
0
11 MSA2
0 00 0 00 0
0 0 00 0 10 00 00
01
01
00
1 12 1 00 0
1 01 0 00 0
0 00 0 00 0
0
0
0
0 0 00 0 11 12 00
0 0 00 0 11 00 00
0 0 00 0 00 00 00
00
00
01
00
00
00
R
M
P M
L
M
00
00
IDLE
1
1
1
0
1
0
10
12
10
00
11
00
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
00
00
00
00
00
00
0
0
1
0
0
0
00
00
10
00
00
00
00
00
00
00
10
00
00
00
11
00
00
00

Chapter 13
13-1.*
Heads x (cylinders/Head) x (sectors/cylinder) x (1 cylinder/track) x (bytes/sector)
a) 1 x 1023 x 63 x 512
32,224.5 Kbytes (K = 1024)
b) 4 x 8191 x 63 x 512
1,032,066 Kbytes
c) 16 x 16383 x 63 x 512 =
8,257,032 Kbytes
13-4.*
a)
If each address line is used for a different CS input, there will be no way to address
the four registers so 2 bits are needed to address the registers. Only 14 lines can be used
for CS inputs permitting at most 14 I/O Interface Units to be supported.
b)
Since two bits must be used to address the four registers, there are 14 bits remaining and
214 or 16,384 distinct I/O Interface Units can be supported.
13-6.*
A given address can be shared by two registers if one is written and one is read. If a register is both
read and written, then it needs its own address. Each RW operation requires its own address. Since
there are more read only addresses than write only addresses, the write only addresses can be shared
with read addresses. Since there are twice as many read only registers as there are RW registers, the
number of RW registers is 16/3 = 5. The number of read only registers is 2 5 = 10, and the number
of write only registers is 5. This gives a total of 20 registers. (Due to integer numbers of registers
with the % distributions, there is one address left over.)
13-8.*
(a)
(b)
Read Operation
Data Bus
Address Bus
CPU
RD Strobe
Data bus
From I/O
Address bus
I/O
Device
WR Strobe
Read
Strobe
Write
Strobe
Data bus
Address bus
13-10.*
a) 57,600 Baud/ 11 Bits = 5236 Characters/sec
b) 57,600 Baud/ 10 Bits = 5760 Characters/sec
c) 115,200 Baud/ 11 Bits = 10,472 Characters/sec
115,200 Baud/ 10 Bits = 11,520 Characters/sec
Read
Strobe
Write
Strobe
Write Operation
From CPU
13-13.*
There are 7 edges in the NRZI waveform for the SYNC pattern that can be used for synchronization.
13-15.*
SYNC
8 bits
Type
4 bits
1001
Endpoint
Address
0010
Device
Address
0100111
Check
4 bits
0110
CRC
EOP
CRC
EOP
(a) Output packet
SYNC
8 bits
Type
4 bits
1100
Check
4 bits
0011
Data
010000101001111010100110
(b) Data packet (Data0 type) (bits LSB first)
SYNC
8 bits
Type
4 bits
0111
Check
4 bits
1000
EOP
(c) Handshake packet (Stall type)
13-18.*
Description
PI
Initially
0
Before CPU acknowledges Device 2 0
After CPU sends acknowledge
1
Device 0
PO RF VAD PI
0
0
0
0
1
0
0
1
0
0
Device 1
PO RF VAD PI
0
0
0
0
0
0
0
0
0
Device 2
PO RF VAD
0
1
0
1
0
1
-
13-20.*
Replace the six leading 0s with 000110.
13-22.*
This is Figure 13-17 with the Interrupt and Mask Registers increased to
6 bits each, and the 4x2 Priority Encoder replaced by a 8x3 Priority
Encoder. Additionally, VAD must accept a 3rd bit from the Priority
Encoder.
13-24.*
When the CPU communicates with the DMA, the read and write lines are used as DMA
inputs. When the DMA communicates with the Memory, these lines are used as
outputs from the DMA.

Chapter 14
14-1.*
Binary
54 0010 1 01 00
58 0010 1 10 00
104 1000 0 01 00
5C 0010 1 11 00
108 1000 0 10 00
60 0011 0 00 00
F0 0111 1 00 00
64 0011 0 01 00
54 0010 1 01 00
58 0010 1 10 00
10C 1000 0 11 00
5C 0010 1 11 00
110 1000 1 00 00
60 0011 0 00 00
F0 0111 1 00 00
64 0011 0 01 00
a
M
M
M
M
M
M
M
M
H
H
M
H
M
H
M
H
b
M
M
M
M
M
M
M
M
H
H
M
H
M
H
H
H
c
M
M
M
M
M
M
M
M
M
H
M
H
M
M
M
H
14-4.*
Since the lines are 32 bytes, 5 bits are used to address bytes in the lines.
Since there are 1K bytes, there are 1024/32 = 25 cache lines.
a) Index =
5 Bits,
b) Tag
32 5 5 = 22 Bits
c) 32 (32 8 + 22 + 1) = 8928 bits
14-6.*
a) See Instruction and Data Caches section on page 635 of the text.
b) See Write Methods section on page 631 of the text.
14-8. *
000000 00 00 (i0)
000001 00 00 (i4)
000001 10 00 (i6)
000010 10 00 (i10)
000000 01 00 (i1)
000011 00 00 (d)
00001 11 00 (i7)
000011 10 00 (d)
000000 10 00 (i2)
000001 01 00 (i5)
000010 00 00 (i8)
000010 11 00 (i11)
000000 11 00 (i3)
000011 01 00 (d)
000010 01 00 (i9)
000011 11 00 (d)
Addresses of instructions (i) and Data (d) in sequence down and then to the right with the instructions in a loop with
instruction i0 following i11. For the split cache, the hit - miss pattern for instructions is (assuming the cache initially
empty and LRU replacement) M, M, M, M, M, M, M, M, M, M, M, M, M, ... since there are only eight locations
available for instructions. For the unified cache, the hit-miss pattern for instructions with the same assumptions is M,
M, M, M, M, M, M, M, M, M, M, M, H, H, H, ... since there are 12 locations indexed appropriately for instructions
and four indexed appropriately for data.
14-11.*
a) Effective Access Time
0.91 * 4ns + 0.09 * 40 ns = 7.24 ns
b) Effective Access Time
0.82 * 4ns + 0.18* 40 ns = 10.48 ns
c) Effective Access Time
0.96 * 4ns + 0.04 * 40 ns = 5.44 ns
14-14.*
a) Each page table handles 512 pages assuming 64-bit words. There
are 4263 pages which requires 4263/512 8.33 page tables. So 9 page
tables are needed.
b) 9 directory entries are needed, requiring 1 directory page.
c) 4263 - 8*512 = 167 entries in the last page table.
14-18.*
In section 14-3, it is mentioned that write-through in caches can slow down processing, but this can be
avoided by using write buffering. When virtual memory does a write to the secondary device, the amount of
data being written is typically very large and the device very slow. These two factors generally make it
impossible to do write-through with virtual memory. Either the slow down is prohibitively large, or the buffering cost is just too high.

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Solutions to Problems Marked with a * in

Logic and Computer Design Fundamentals, 3rd Edition

(110 111 011.110)2

(1110 0111 1100.1011)2

Problem Solutions Chapter 1

By the quadratic equation: r = 9 or 7

(0110 1001 0100)BCD

(1000 0011 0101)BCD

(0011 0110 0101)BCD

Solutions to Problems Marked with a * in

Verification of DeMorgans Theorem

The Second Distributive Law

Problem Solutions Chapter 2

WX ( Z + YZ ) + X ( W + WYZ ) = WXZ + WXYZ + WX + WXYZ

( AB + AB ) ( CD + CD ) + AC = ABCD + ABCD + ABCD + ABCD + A + C

Problem Solutions Chapter 2

XYZ + XYZ + XYZ + XYZ

ABC + ABC + ABC + ABC

WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ

Problem Solutions Chapter 2

b) Prime = CD, AC, BD, ABD, BC

c) Prime = AB, AC, AD, BC, BD, CD

Essential = AC, BD, ABD

Essential = AC, BC, BD

c) s.o.p. BD + ABD + ( A BC or ACD )

LOGIC AND COMPUTER DESIGN FUNDMENTALS INSTRUCTORS MANUAL

Solutions to Problems Marked with a * in

Solutions to Problems Marked with a * in

4-7.*(Errata: four should be two and 48 should be 32)

Problem Solutions Chapter 4

Problem Solutions Chapter 4

Problem Solutions Chapter 4

Solutions to Problems Marked with a * in

Problem Solutions Chapter 5

Solutions to Problems Marked with a * in

c) There is a setup time violation at 28ns.

State diagram is the combination of the above two diagrams.

Problem Solutions Chapter 6

Logic diagram not given.

Problem Solutions Chapter 6

Problem Solutions Chapter 6

architecture mux_4to1_arch of mux_4to1 is

-- (continued in the next column)

Problem Solutions Chapter 6

architecture jkff_arch of jkff is

-- (continued in the next column)

module problem_6_39 (S, D, Y) ;

// (continued in the next column)

always @(negedge CLK)

Solutions to Problems Marked with a * in

Problem Solutions Chapter 7

For the other three funcQ4 tions, AND EN with the

Problem Solutions Chapter 7

Problem Solutions Chapter 7

b) Source Registers -> Destination

c) The minimum number of buses needed for operation of the transfers

1000, 0100, 1010, 1101 0110, 0011, 0001, 1000

--asynchronous RESET active Low

Problem Solutions Chapter 7

Solutions to Problems Marked with a * in

Problem Solutions Chapter 8

Problem Solutions Chapter 8

Problem Solutions Chapter 8