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1 MOS DEVICE FUNDAMENTALS Professor A. K. Majumdar Computer Science and Engineering Department Indian Institute

1

MOS DEVICE FUNDAMENTALS

Professor A. K. Majumdar

Computer Science and Engineering Department Indian Institute of Technology, Kharagpur

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Induced Channel in NMOS Transistor Enhancement mode NMOS transistor with V GS >0 showing induced
Induced Channel in NMOS
Transistor
Enhancement mode NMOS transistor with
V GS >0 showing induced channel
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with V GS >0 showing induced channel MOS-SLIDES-AKM 3 5 NMOS Transistor Analysis • Induced Channel

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NMOS Transistor Analysis

• Induced Channel Charge / Unit Area Q(x) = - C OX [ V GS – V(x) – V th ]

Where C OX =

ε OX / t OX capacitance per unit

area due to gate oxide Drain current I DS = v n (x) Q(x)W v n (x) = drift velocity of electron

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v n (x) = drift velocity of electron MOS-SLIDES-AKM Metal-Oxide Semiconductor (MOS) Field Effect Transistors

Metal-Oxide Semiconductor (MOS) Field Effect Transistors

Metal-Oxide Semiconductor (MOS) Field Effect Transistors NMOS enhancement mode transistor MOS-SLIDES-AKM 2 Current

NMOS enhancement mode transistor

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Current – Voltage characteristics of NMOS transistors MOS-SLIDES-AKM 4
Current – Voltage characteristics
of NMOS transistors
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characteristics of NMOS transistors MOS-SLIDES-AKM 4 NMOS Transistor Analysis Contd • • μ n = Mobility

NMOS Transistor Analysis Contd

μ n = Mobility of electrons

• Hence I DS = - μ n Q(x)W dV/dx • Substituting for Q(x),

• I DS dx = μ n C OX W[V GS – V(x) – V th ] dV Integrating

• I DS = μ n C OX W/L[(V GS - V th ) - V DS /2 ] V DS

• I DS = η n [(V GS - V th ) - V DS /2 ] V DS

v n (x) =

- μ n E(x)

= μ n dV/dx

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  NMOS Transistor Analysis in Linear Region • k n = μ n C O
 

NMOS Transistor Analysis in Linear Region

• k n =μ n C OX = μ n ε OX / t OX is called process transconductance parameter

η n = k n (W/L) is called gain factor

 

• For small V DS , V DS 2 /2 can be ignored and I DS depends linearly on V DS

• R linear = 1/ (η n (V GS - V th ))

 
 

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G S - V t h ))     MOS-SLIDES-AKM 7   NMOS Transistor Analysis Saturation
 

NMOS Transistor Analysis Saturation Region

 

• V DS V GS – V th

 

• Channel is pinched off

• Assuming voltage difference over induced channel from source to pinch off point fixed at

V GS V th

 

• I DS = η n /2 (V GS – V th ) 2

• In saturation region, MOS transistor acts as a constant current source.

• Transconductance in saturation region

 

• g m = η n (V GS – V th )

 

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n (V G S – V t h )   MOS-SLIDES-AKM 9   Channel Length Modulation
 

Channel Length Modulation

• In saturation region, the transistor does not operate as a perfect current source, i.e. I DS is not independent of V DS

• As V DS is increased beyond (V GS – V th ) effective channel length decreases.

• Since I DS α 1/L, reduction in effective channel length increases I DS

 

• More accurate representation

• I DS = η n /2.(V gs – V th ) 2 ( 1 + λV DS )

 

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  NMOS Transistor Analysis in Linear Region   • Transconductance of NMOS transistor • g
 

NMOS Transistor Analysis in Linear Region

 

Transconductance of NMOS transistor

g m = (dI DS / dV GS )V DS = constant

 
 

In linear region

 

g m = η n V DS

 

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  g m = η n V DS   MOS-SLIDES-AKM 8   Current – Voltage Relationship
 

Current – Voltage Relationship of NMOS Transistor

 

The drain-to-source current-voltage dependence for a NMOS transistor is given by the following equations

I DS = 0

for V DS < V th (off)

 

I DS = η n /2.(V GS – V th ) 2

for 0 < V DS – V th < V DS (saturation)

I DS = η n (V GS – V th – V DS /2)V DS for V GS > V th and V GS – V th V DS (linear)

 

η n = (μ n ε ox /t ox ).W/L

 

where μ

n

is the mobility of electron, ε

ox

is the permittivity

of the oxide material, and t ox is the thickness of the oxide.

 

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10

is the thickness of the oxide.   MOS-SLIDES-AKM 10   Current – Voltage Relationship of PMOS
 

Current – Voltage Relationship of PMOS Transistor

 

Cut off V GS > V th I DS = 0

 

Linear Region: V GS V th and V DS > V GS – V th

 

I DS = η p (V GS – V th – V DS /2)V DS

 
 

Saturation region V GS V th, and V DS < V GS –V th I DS = η p /2.(V GS –V th ) 2

where the gain factor η p = (μ p ε ox /t ox ).W/L and μ p is mobility of holes

 

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Lateral diffusion of source and drain regions Lateral diffusion = L d Effective channel length
Lateral diffusion of source and
drain regions
Lateral diffusion = L d
Effective channel length L eff = L -2 Ld
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MOS transistor gate capacitances for three operating regions 15 Capacitance Cutoff Linear Saturation  
MOS transistor gate capacitances for three operating regions 15 Capacitance Cutoff Linear Saturation  
MOS transistor gate capacitances for three operating regions 15 Capacitance Cutoff Linear Saturation  
MOS transistor gate capacitances for three operating regions 15 Capacitance Cutoff Linear Saturation  

MOS transistor gate capacitances for three operating regions

MOS transistor gate capacitances for three operating regions 15 Capacitance Cutoff Linear Saturation  
MOS transistor gate capacitances for three operating regions 15 Capacitance Cutoff Linear Saturation  

15

Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS
Capacitance Cutoff Linear Saturation   0 0 C GB C ox WL eff C GS

Capacitance

Cutoff

Linear

Saturation

 

0

0

C

GB

C

ox WL eff

C

GS

C

ox WL d

C

ox WL d +½C ox WL eff

C

ox WL d +2/3C ox WL eff

C

GD

C

ox WL d

C

ox WL d +½C ox WL eff

C

ox WL d

WL d +2/3C o x WL e f f C GD C ox WL d C
WL d +2/3C o x WL e f f C GD C ox WL d C
WL d +2/3C o x WL e f f C GD C ox WL d C

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ox WL eff C ox WL d MOS-SLIDES-AKM Pull Up and Pull Down transistors • The

Pull Up and Pull Down transistors

• The depletion mode transistor is a pull up device. It is always on (V gs = 0)

• The enhancement mode transistor is the pull down device.

• With no current drawn from output, current in both pull up and pull down transistors must be same.

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and pull down transistors must be same. MOS-SLIDES-AKM 17 MOSFET Capacitances MOS-SLIDES-AKM 14 NMOS Inverter

MOSFET Capacitances

must be same. MOS-SLIDES-AKM 17 MOSFET Capacitances MOS-SLIDES-AKM 14 NMOS Inverter MOS-SLIDES-AKM 16 Current

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NMOS Inverter MOS-SLIDES-AKM 16
NMOS Inverter
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Current Voltage Characteristics of NMOS Inverter MOS-SLIDES-AKM 18
Current Voltage Characteristics of
NMOS Inverter
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NMOS Inverter

 

• The points of intersection of the pull up (for V

gs

=0 )

and pull down curves give points on the transfer characteristics for the inverter

 

• As V

in

exceeds V

Tpd

(pull down transistor threshold)

 

current will flow and V

falls. Further increase in V

in

out

will cause pull down transistor to be out of saturation and will behave as resistor

 

• Pull up device is initially resistive when pull down is turned on

 

• The point at which V in = V out is called V inv

 

• V

inv

can be shifted by variation of ratios of pull up and

down resistances – determined by the length to width ratio of the transistor.

     
 

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CMOS INVERTER MOS-SLIDES-AKM 21
CMOS INVERTER
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CMOS Fabrication MOS-SLIDES-AKM 23
CMOS Fabrication
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NMOS Inverter

 

• With NMOS Depletion Mode transistor

• High Dissipation: When V IN is high current flows through both the devices.

 

• Output switching: occurs when V in exceeds V thpd

 

• During fall 10 transition, pull up offers lower resistance to charge capacitive load.

• Degrades 0 value : Low output value is determined by pull down resistance.

 
 

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CMOS Inverter

N Well

CMOS Inverter N Well

V

 

V

DD

PMOS In NMOS
PMOS
In
NMOS

Out

PMOS

2λ Contacts
Contacts
DD Out In
DD
Out
In

NMOS

Metal 1

GND

Polysilicon

 
   

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CMOS Fabrication

 
      MOS-SLIDES-AKM 22   CMOS Fabrication     MOS-SLIDES-AKM 24  
 

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Current Voltage Characteristics MOS-SLIDES-AKM 25
Current Voltage Characteristics
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CMOS INVERTER - CONTD

 

Region R1: 0 < V in < V

thn

, NMOS transistor is off, PMOS

device operates in the linear region.

 

Region R2: V

thn

<

V

in

<

V

DD

- |V

thp

|

and Vin + |V

thp

| < V

out

V

DD

, NMOS transistor in saturation, and PMOS transistor

still in the linear region.

 

Region R3: V

thn

<V

in

<V

DD

- |V

thp

|

and V

in

- V

thn

V out

V in + |V thp |, both the transistors are in saturation.

Region R4: V

thn

<

V

in

<

V

DD

– |V

thp

| and V

out

< V

in - V thn ,

 

NMOS transistor is in the linear region and PMOS

remains in saturation.

 

Region R5: V

DD

– |V

thp

|

< V

in

< V DD , PMOS transistor in

cut-off, NMOS in the linear region.

 
 

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Static Analysis of CMOS Inverter

 

Current – Voltage Relationship of NMOS transistor : V GSn = V in , V DSn = V out

 

η n = (μ n ε/t ox ) (W/L) n

 

Cut-off (V in V thn )

:

I DS = 0

Linear (V in – V thn V out )

:

 
 

I DS = η n (V GSn V thn V DSn /2)V DSn

 

Saturation ( V thn V in , V out > V in – V thn ):

 
 

I DS = η n /2(V GSn – V thn ) 2

 

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CMOS INVERTER –VOLTAGE TRANSFER CHARACTERISTICS MOS-SLIDES-AKM 26
CMOS INVERTER –VOLTAGE
TRANSFER CHARACTERISTICS
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CMOS Inverter Characteristics MOS-SLIDES-AKM 28
CMOS Inverter Characteristics
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Current – Voltage Relationship of PMOS transistor   V G S p = - (V

Current – Voltage Relationship of PMOS transistor

 

V GSp = - (V DD – V in ), η p = (μ p ε/tox) (W/L) n

V DSp = - (V DD – V out )

 

Cut-off (V in > V DD - |V thp |)

:

I DS = 0

Linear (V in V DD - |V thp |) and (V out >V in +|V thn |) : I DS = η n (V GSp – |V thp | –V DSp /2)V DSp

Saturation (V in V DD - |V thp |) and (V out V in +|V thp |) :I DS = η p /2(V GSn – |V thp |) 2

 

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  Static Analysis of CMOS Inverter- Contd • V OH = V DD   •
 

Static Analysis of CMOS Inverter- Contd

V OH = V DD

 

V OL = 0

V inv = [ V thn + (1/√β)(V DD + V thp )] / (1 + 1/√β)

β = η n /η p =[μ n (ε ox /t ox ) n (W/L) n ]/ [μ p (ε ox /t ox ) p (W/L) p ]

 

• for β = 1,

• (W/L) n / (W/L) p = μ p /μ n 1/2.5

• (W/L) p 2.5 (W/L) n

 

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(W/L) p ≈ 2.5 (W/L) n   MOS-SLIDES-AKM 31   NOISE MARGINS   • N ML
 

NOISE MARGINS

 

• N ML = V IL – V OL = V IL

 

• N MH = V OH – V IH = V DD – V IH

 

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– V IH = V DD – V IH   MOS-SLIDES-AKM 33   Switch model of
 

Switch model of a static CMOS inverter

 
 
 

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static CMOS inverter     MOS-SLIDES-AKM 35 Static Analysis of CMOS Inverter- Contd • V I

Static Analysis of CMOS Inverter- Contd

V IL = (2V out + V thp – V DD + βV thn ) / (1 + β)

β = 1, and V thn = V thp

• V IL = 1/8 (3V DD +2 V thn )

• V IH = [V DD + V thp + β(2 V out + V thn )] / (1 + β)

• with β = 1, and V thn = V thp ,

• V IH = (5V DD – 2V thn ) /8

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Switching Characteristics of a CMOS Inverter Parasitic capacitances in a cascaded CMOS inverter MOS-SLIDES-AKM 34
Switching Characteristics of a
CMOS Inverter
Parasitic capacitances in a cascaded CMOS
inverter
MOS-SLIDES-AKM
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Propagation delay times and rise and fall times of an inverter MOS-SLIDES-AKM 36
Propagation delay times and rise and fall
times of an inverter
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CMOS inverter equivalent circuit during high-to-low and low-to-high output transitions MOS-SLIDES-AKM 37
CMOS inverter equivalent circuit during
high-to-low and low-to-high output
transitions
MOS-SLIDES-AKM
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Propagation Delay Estimation – Contd. • Low to High Transition C ⎡ 2| V |
Propagation Delay Estimation –
Contd.
• Low to High Transition
C
2|
V
|
4|
V
| ⎞ ⎤
thp
thp
L
+
ln ⎜ 3
• τ pLH =
η(
V
− | V
|)
(
V
|
V
|)
V
p
DD
thp
DD
thp
DD
• For τ pHL = τ pLH , (W/L) p ≈ 2.5 (W/L) n
MOS-SLIDES-AKM
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Power Dissipation in CMOS Inverter

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage

Leaking diodes and transistors

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Propagation Delay Estimation • High to Low Transition   • τ pHL = τ pHL1

Propagation Delay Estimation

• High to Low Transition

 

τ pHL = τ pHL1 + τ pHL2

 

τ pHL1 = the period during which V out drops from V DD to V DD – V thn .

 

τ pHL1 = 2 C L V thn / η n (V DD V thn ) 2

τ pHL2 = the period during which Vout drops from V DD – V thn to V DD /2.

C

L

ln 3

4 V ⎞ ⎤

thn

τ pHL2 =

η (

n

V

DD

V

thn

)

V

DD

 

MOS-SLIDES-AKM

 

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Typical input - output and load capacitor current waveforms in a CMOS inverter MOS-SLIDES-AKM 40
Typical input - output and load
capacitor current waveforms in a
CMOS inverter
MOS-SLIDES-AKM
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current waveforms in a CMOS inverter MOS-SLIDES-AKM 40 Dynamic Power Consumption E-charge = C L V

Dynamic Power Consumption

CMOS inverter MOS-SLIDES-AKM 40 Dynamic Power Consumption E-charge = C L V D D 2 E-discharge

E-charge = C L V DD 2

E-discharge = ½ C L V DD 2 Average Power dissipation

P Avg = 1/T C L V DD 2

= C L V DD 2 f

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Switching Power Dissipation in CMOS Inverter • f max = 1/2τ p • Power Delay
Switching Power Dissipation in
CMOS Inverter
• f max = 1/2τ p
• Power Delay Product,
• PDP = Pavg τ p
For f = f max , PDP = C L V DD 2 f max τ p
= ½ C L V DD 2
Note: average switching power dissipation of a CMOS
inverter is independent of transistor sizes and
characteristics provided there is full voltage swing
Analysis is valid when output node of the gate
undergoes one transition (0 to V DD ) in a clock cycle.
MOS-SLIDES-AKM
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ShortShort CircuitCircuit CurrentCurrent inin CMOSCMOS InverterInverter MOS-SLIDES-AKM 45
ShortShort CircuitCircuit CurrentCurrent inin CMOSCMOS InverterInverter
MOS-SLIDES-AKM
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inin CMOSCMOS InverterInverter MOS-SLIDES-AKM 45 Sub Sub Threshold Threshold Leakage Leakage MOS-SLIDES-AKM

SubSub ThresholdThreshold LeakageLeakage

45 Sub Sub Threshold Threshold Leakage Leakage MOS-SLIDES-AKM 47   Switching Power Dissipation -

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  Switching Power Dissipation - Contd   • When node transition rate is slower than
 

Switching Power Dissipation - Contd

 

When node transition rate is slower than clock rate

P Avg =

α

T

C L V DD 2 f

where

α

T

is the node transition factor (effective number

 

of power consuming transition per cycle)

 
 

Energy Delay Product EDP = PDP τ p = ½ C L V DD 2 τ p

 

MOS-SLIDES-AKM

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½ C L V D D 2 τ p   MOS-SLIDES-AKM 44   Short Circuit Current
 

Short Circuit Current

 
 

Short circuit current is large if output load capacitance is low and input rise/fall time is large.

To reduce short circuit power dissipation input/output rise and fall times should be

 

of same order =

τ

 

P Avg (short-circuit) = 1/12[k

τ

f (V DD - V thn -|V thp |) 3 ]

 

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ReverseReverse--BiasedBiased DiodeDiode LeakageLeakage GATE p + p + N Reverse Leakage Current + - V
ReverseReverse--BiasedBiased DiodeDiode LeakageLeakage
GATE
p +
p +
N
Reverse Leakage Current
+
- V dd
I DL = J S × A
qV bias /kT
Reverse leakage Current of a p-n junction I reverse = A J S (e
- 1)
Reverse saturation current Density J S = 10-100 pA/μm2 at 25 deg C for 0.25μm CMOS,
J S doubles for every 9 deg C!
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  Advantages of CMOS Inverter • The high and low output voltages are equal to
 

Advantages of CMOS Inverter

• The high and low output voltages are equal to V

dd

and

 

ground respectively so that the voltage swing is the same as the supply voltage

• The logic levels are not dependent on the relative device sizes and hence the size of the transistors can be minimized.

• There is always a finite resistance between the output

 

and either V

dd

or ground in the steady state. The inverter

can, therefore, be designed to have a low input impedance, making it less sensitive to noise.

• The CMOS inverter has a very high input resistance and

 

draws no dc input current as the gate of a MOS transistor is virtually a perfect insulator.

 

MOS-SLIDES-AKM

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Effects of scaling on MOS transistor characteristics  

Effects of scaling on MOS transistor characteristics

 
 
 
 

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COMPLEMENTARY CMOS NAND GATE MOS-SLIDES-AKM 53
COMPLEMENTARY CMOS NAND GATE
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Technology Scaling  

Technology Scaling

 

Full Scaling (Constant Field Scaling)

Constant Voltage Scaling

 

Parameter

     

Channel Length (L)

   

Channel Width (W)

   

Gate oxide thickness (t ox )

   
     

Supply voltage V DD

   

Junction depth (X j )

   

Threshold voltage (V th )

   
   

Doping densities – N D (N A )

   

50

 

N D κ (N A κ)

N D κ 2 (N A κ 2 )

MOS-SLIDES-AKM

COMPLEMENTARY CMOS DESIGN   V DD   In 1 PMOS Circuit PUN …… PDN NMOS

COMPLEMENTARY CMOS DESIGN

 

V

DD

 

In

1

PMOS Circuit PUN …… PDN NMOS Circuit
PMOS Circuit
PUN
……
PDN
NMOS Circuit
 

In

2

In

 

N

OUT= F(In 1 ,In 2 ,…In N )

 

In

1

   

In

2

In

N

Static Complementary CMOS Circuit

 
 

MOS-SLIDES-AKM

 

52

CMOS Circuit     MOS-SLIDES-AKM   52   CMOS NAND GATE   • With both input
 

CMOS NAND GATE

 

• With both input A =1, and B = 1

• PMOS pull up transistors are in cut off.

• NMOS pull down transistors create conducting path.

 

• For other input combinations one of the pull up PMOS transistors will be on and NMOS network will be cut- off

 

MOS-SLIDES-AKM

 

54

CMOS NAND GATE • Taking (W/L) to be same for each type of transistors, i.e.

CMOS NAND GATE

• Taking (W/L) to be same for each type of transistors, i.e. (W/L) n,A = (W/L) n,B and

(W/L) p,A = (W/L) p,B

V inv =

[V thn + 2 sqrt(η p / η n ) (V DD – |V thp |)] /

(1+ 2 sqrt(η p / η n ))

• Assuming V thn = |V thp | , for V inv = V DD /2, one should select η n = 4 η p .

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should select η n = 4 η p . MOS-SLIDES-AKM 55 4-Input NAND gate Elmore Delay

4-Input NAND gate

η n = 4 η p . MOS-SLIDES-AKM 55 4-Input NAND gate Elmore Delay Model: t

Elmore Delay Model:

t pHL = 0.69 R n (C 1 +2C 2 +3C 3 +4C L )

•Propagation delay deteriorates rapidly as a function of fan-in – quadratically

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2-input NOR gate MOS-SLIDES-AKM 59
2-input NOR gate
MOS-SLIDES-AKM
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Lumped parameter switching model of a two input CMOS NAND gate

parameter switching model of a two input CMOS NAND gate •Delay is dependent on the input

•Delay is dependent on the input pattern :

t pLH =0.69 R p /2 C L for low to high output transition when both inputs go low. t pLH = 0.69 R p C L when one input goes low. t pHL = 0.69 * 2 R n C L for low to high transition of both inputs.

To have same pull-down delay as the minimum sized inverter the NMOS devices in the PDN of the NAND gate should be twice as wide.

MOS-SLIDES-AKM

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CMOS TWO INPUT NAND GATE LAYOUT

 
 
 
 
 

Stick Diagram

 

Layout

 

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58

 

CMOS NOR GATE

 

V OL = 0 and V OH =V DD

 

• Switching Threshold Computation

 

Assume (W/L) to be same for each type of transistors, i.e. (W/L) n,A = (W/L) n,B and (W/L) p,A = (W/L) p,B both input voltage switch simultaneously, i.e. V A = V B Neglect body effect for PMOS transistors

 

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CMOS NOR GATE • At switching Threshold V A = V B = V o

CMOS NOR GATE

• At switching Threshold V A = V B = V out = V inv

• NMOS transistors are in saturation (since V GS =

V DS )

• Lower PMOS transistor (with A-input) is in linear region, the upper PMOS (B-input) is in saturation

• V inv =

[V thn + sqrt(η p /4 η n ) (V DD – |V thp |)] /

(1+ sqrt(η p /4 η n ))

• Assuming V thn = |V thp | , for V inv = V DD /2, one should select η p = 4 η n .

MOS-SLIDES-AKM

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CMOS realization of a switching function F = (A+D) B + CD MOS-SLIDES-AKM 63
CMOS realization of a switching function
F = (A+D) B + CD
MOS-SLIDES-AKM
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Pass Transistor MOS-SLIDES-AKM 65
Pass Transistor
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XOR Gate MOS-SLIDES-AKM 62
XOR Gate
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Features of Complementary CMOS Design • No static power consumption   • High noise margins

Features of Complementary CMOS Design

No static power consumption

 

• High noise margins

:

 

V OH = V DD ,

V OL = GND

 

Low output impedance

• Very high input resistance

• Logic levels independent of relative device sizes of the NMOS and PMOS transistors : ratioless

.

•With proper sizing , rise same order

and fall times are of

 
 

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times are of     MOS-SLIDES-AKM   64   Pass Transistor   • NMOS pass transistor
 

Pass Transistor

 

• NMOS pass transistor :

 

Passes 0 (low ) well but degrades 1 (high) Maximum value of output is V DD – V thn

• PMOS pass transistor

 

Passes 1 without any degradation Low value is degraded to V thp

 
 

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PASS TRANSISTOR LOGIC • When the input A is high, Q1 is turned on and

PASS TRANSISTOR LOGIC

PASS TRANSISTOR LOGIC • When the input A is high, Q1 is turned on and input

• When the input A is high, Q1 is turned on and input B is copied to the output Z.

• If A is low, the pass transistor Q2 is turned on and passes 0 to Z.

• The transistor Q2 offers low impedance path to the supply rails even when A is low.

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COMPLEMENTARY PASS TRANSISTOR LOGIC MOS-SLIDES-AKM 69
COMPLEMENTARY PASS TRANSISTOR LOGIC
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CMOS transmission gate realization of XOR function. MOS-SLIDES-AKM 71
CMOS transmission gate realization of XOR function.
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  PASS TRNASISTOR LOGIC - PROBLEMS   • NMOS pass transistor passes but degrades V
 

PASS TRNASISTOR LOGIC - PROBLEMS

 

NMOS pass transistor passes but degrades V OH to VDD –V thn .

0V(V OL ) correctly,

•PMOS pass transistor passes 1 i.e. V DD correctly but degrades 0 to |V thp |

•Signal level degradation can be remedied by insertion of a CMOS inverter or by the usage of suitable level restoration circuits.

 

•Pass transistor gates should not be cascaded

 

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should not be cascaded   MOS-SLIDES-AKM 68     CMOS Transmission Gate Logic      
 

CMOS Transmission Gate Logic

 
 
 
 

With CMOS transmission gates : No signal degradation

 

Equivalent resistance of a CMOS transmission gate is almost independent of the output voltage.

Compared to the corresponding static CMOS realization the

transmission gate realization would have speed advantage.

 

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would have speed advantage.   MOS-SLIDES-AKM 70   Six transistor CMOS transmission gate realization of
 

Six transistor CMOS transmission gate realization of the XOR function.

 
 

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Dynamic CMOS Design The circuit operates in two phases, pre-charge and evaluation , and the
Dynamic CMOS Design
The circuit operates in two phases, pre-charge and
evaluation , and the mode of operation is determined by
the clock signal CLK
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is determined by the clock signal CLK MOS-SLIDES-AKM 73 DYNAMIC CMOS DESIGN - ADVANTAGES The number

DYNAMIC CMOS DESIGN - ADVANTAGES

The number of transistors required is (N + 2) in dynamic CMOS as compared to 2N for static design.

The dynamic design is non-ratioed. The size of the CMOS pre-charge transistor is not important for proper realization of the gate and hence can be increased to improve the low-to- high transition time.

The dynamic gates have reduced load capacitance

because of a fewer number of transistors and hence faster switching speeds.

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Charge sharing in a dynamic CMOS Circuit MOS-SLIDES-AKM 77
Charge sharing in a dynamic CMOS Circuit
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DYNAMIC CMOS LOGIC OPERATION When CLK = 0, the output is pre-charged to V DD
DYNAMIC CMOS LOGIC OPERATION
When CLK = 0, the output is pre-charged to V DD by the transistor Q p .
The evaluation NMOS transistor Q e remains off during this time thus
disabling the pull-down path.
For CLK = 1, the evaluation Q e is turned on while the pre-charge
transistor Q p is turned off.
The output is conditionally discharged depending upon the inputs
and the topology of the PDN - if the PDN is conducting, it would offer
a low resistance path between out and the ground. On the other
hand, if the PDN is turned off, the pre-charged value will remain
stored in the output capacitance C L .
Once the node out is discharged, it cannot be charged again till the
next pre-charge begins. Thus during the evaluation phase the inputs
can make not more than just one transition.
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Dynamic CMOS realization of the Boolean function F=AB+BD+CD MOS-SLIDES-AKM 76
Dynamic CMOS realization of the Boolean function F=AB+BD+CD
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of the Boolean function F=AB+BD+CD MOS-SLIDES-AKM 76 CHARGE SHARING PROBLEMS WITH DYNAMIC LOGIC MOS-SLIDES-AKM

CHARGE SHARING PROBLEMS WITH DYNAMIC LOGIC

function F=AB+BD+CD MOS-SLIDES-AKM 76 CHARGE SHARING PROBLEMS WITH DYNAMIC LOGIC MOS-SLIDES-AKM 78 MOS-SLIDES-AKM 13

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Cascading problem in dynamic CMOS gates MOS-SLIDES-AKM 79
Cascading problem in dynamic CMOS gates
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Cascading problem in dynamic CMOS gates MOS-SLIDES-AKM 79 DOMINO LOGIC OPERATION A static inverter (buffer) follows

DOMINO LOGIC OPERATION

A static inverter (buffer) follows an n-type dynamic logic block.

Pre-charge phase: CLK=Low, output of the dynamic gate is charged up to V DD through Q p which is ON and Inverter output is Low.

Evaluation phase: CLK=High, Q p turns off, inverter output can change for Low to High depending on the inputs – if PDN conducts, dynamic gate will discharge and inverter output will become high, else output of dynamic gate will remain charged (high) and the poutput of domino gate will remain low.

The inverter output voltage can make at most one transition from 0 to 1 during the evaluation phase.

The buffer output can never make 1 to 0 transition during the evaluation phase for any combination of the input values.

Hence a domino gate can only implement non-inverting logic.

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can only implement non-inverting logic. MOS-SLIDES-AKM 81 MOS-SLIDES-AKM 83 DOMINO LOGIC MOS-SLIDES-AKM 80
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DOMINO LOGIC MOS-SLIDES-AKM 80
DOMINO LOGIC
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81 MOS-SLIDES-AKM 83 DOMINO LOGIC MOS-SLIDES-AKM 80 REFERENCES 1. Rabaey J. M.,Chandrakasan A., and Nikolic B.,

REFERENCES

1. Rabaey J. M.,Chandrakasan A., and Nikolic B., “ Digital Integrated Circuits”, Prentice- Hall of India, 2003.

2. Kang, Sung-Mo and Leblebici, Y.: CMOS Digital Integrated Circuits, McGraw Hill Pub., 2003

3. Weste N.H.E and Eshraghlan, K: Principles of CMOS VLSI Design, Pearson Education, 2004.

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