Lecture 1:

Introduction
1.
2.
3.
4.

Introduction
MOS Transistors
CMOS Logic Gates
IC Design Flow

1: Introduction

1. Introduction

Integrated circuits (IC): many transistors on one chip.

Very Large Scale Integration (VLSI): bucket loads!

Complementary Metal Oxide Semiconductor (CMOS)
Fast, cheap, low power transistors

Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication

Rest of the course: How to build a good CMOS chip

1: Introduction

CMOS VLSI Design

4th Ed.

Invention of the Transistors

Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable

1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
See Crystal Fire
by Riordan, Hoddeson

AT&T Archives.
Reprinted with
permission.

1: Introduction

CMOS VLSI Design

4th Ed.

Brief history

1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas
Instruments

2010
Intel Core i7 processor
2.3 billion transistors
64 Gb Flash memory
> 16 billion transistors

Courtesy Texas Instruments

[Trinh09]
2009 IEEE.

1: Introduction

CMOS VLSI Design

4th Ed.

Growth Rate

53% compound annual growth rate over 50 years
No other technology has grown so fast so long

Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society

[Moore65]
Electronics Magazine

1: Introduction

CMOS VLSI Design

4th Ed.

Annual Sales

>1019 transistors manufactured in 2008
1 billion for every human on the planet

1: Introduction

CMOS VLSI Design

4th Ed.

Transistor Types

Bipolar junction transistors (BJT)
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density

Metal Oxide Semiconductor Field Effect Transistors
(MOSFET)
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
1: Introduction

CMOS VLSI Design

4th Ed.

MOS Integrated Circuits

1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle

Intel
Museum.

[Vadasz69]

Reprinted
with
permission.

1969 IEEE.

Intel 1101 256-bit SRAM

Intel 4004 4-bit Proc

1980s-present: CMOS processes for low idle power
1: Introduction

CMOS VLSI Design

4th Ed.

Moores Law: Then

1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI:

10 gates

MSI: 1000 gates

LSI:
[Moore65]

10,000 gates

VLSI: > 10k gates

Electronics Magazine

1: Introduction

CMOS VLSI Design

4th Ed.

And Now

1: Introduction

CMOS VLSI Design

4th Ed.

Feature Size

Minimum feature size shrinking 30% every 2-3 years

1: Introduction

CMOS VLSI Design

4th Ed.

Corollaries

Many other factors grow exponentially
Ex: clock frequency, processor performance

1: Introduction

CMOS VLSI Design

4th Ed.

2. MOS Transistors

Transistors are built on a silicon substrate

Silicon is a Group IV material

Forms crystal lattice with bonds to four neighbors
Si

Si

Si

Si

Si

Si

Si

Si

Si

1: Introduction

CMOS VLSI Design

4th Ed.

Dopants

Silicon is a semiconductor

Pure silicon has no free carriers and conducts
poorly

Adding dopants increases the conductivity

Group V: extra electron (n-type)

Group III: missing electron, called hole (p-type)

1: Introduction

Si

Si

Si

Si

Si

Si

As

Si

Si

Si

Si

Si

Si

Si

+
-

CMOS VLSI Design

Si
Si
Si

4th Ed.

p-n Junctions

A junction between p-type and n-type semiconductor
forms a diode.

Current flows only in one direction

1: Introduction

p-type

n-type

anode

cathode

CMOS VLSI Design

4th Ed.

nMOS Transistor

Four terminals: gate, source, drain, body

Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS)
capacitor
Even though gate is
no longer made of metal

1: Introduction

CMOS VLSI Design

4th Ed.

nMOS Operation

Body is usually tied to ground (0 V)

When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
Source

Gate

Drain
Polysilicon
SiO2
0

n+

n+
S
p

1: Introduction

bulk Si

CMOS VLSI Design

4th Ed.

nMOS Operation Cont.

When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

1: Introduction

CMOS VLSI Design

4th Ed.

pMOS Transistor

Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

1: Introduction

CMOS VLSI Design

4th Ed.

Power Supply Voltage

GND = 0 V

In 1980s, VDD = 5V

VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
Lower V -> increase f

VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

1: Introduction

CMOS VLSI Design

4th Ed.

10

Transistors as Switches

We can view MOS transistors as electrically
controlled switches

Voltage at gate controls path from source to drain
g=0
d

d
nMOS

d
OFF

ON

pMOS

g=1

OFF

ON
s

1: Introduction

CMOS VLSI Design

4th Ed.

3. CMOS logic gates

CMOS Inverter
A

OFF
ON

0
1

ON
OFF

3: CMOS Technology

CMOS VLSI Design

4th Ed.

11

CMOS NAND Gate

A

ON
OFF
OFF
ON

A
B

3: CMOS Technology

1
0

ON
OFF

1
0
1
0

CMOS VLSI Design

OFF
ON

OFF
ON
ON
OFF

4th Ed.

CMOS NOR Gate

A

3: CMOS Technology

A
B
Y

CMOS VLSI Design

4th Ed.

12

3-input NAND Gate

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0

Y
A
B
C
3: CMOS Technology

CMOS VLSI Design

4th Ed.

4. IC Design Flow

1: Introduction

CMOS VLSI Design

4th Ed.

13

Logic Design

Define the top-level chip interface and block diagram

Specify the logic with a Hardware Description Language (HDL),
which provides a higher level of abstraction than schematics or
layout.

This code is called the Register Transfer Level (RTL) description.

module adder(
input logic [7:0] a, b,
input logic
c,
output logic [7:0] s,
output logic
cout);

1: Introduction

CMOS VLSI Design

4th Ed.

Circuit Design

Circuit design is to arrange transistors to perform a
particular logic function.

A particular logic function can be implemented in
many ways

Circuit designers often draw schematics at the
transistor and/or gate level.

1: Introduction

CMOS VLSI Design

4th Ed.

14

Physical Design

Physical design is to map the RTL into actual geometric representations

of all electronics devices, such as capacitors, resistors, logic gates, and
transistors
Physical design step:
Floorplanning: The RTL of the chip is assigned to gross regions of
the chip, input/output (I/O) pins are assigned and large objects
(arrays, cores, etc.) are placed.
Placement: The gates in the netlist are assigned to non-overlapping
locations on the die area.
Clock insertion: Clock signal wiring is (commonly, clock trees)
introduced into the design.
Routing: The wires that connect the gates in the netlist are added.
Final checking
Tapeout: and mask generation: the design data is turned into
photomasks

1: Introduction

CMOS VLSI Design

4th Ed.

Design Verification

Design verification is essential to catching the

errors before manufacturing
A testbench is used to verify that the logic is
correct
Formal verification tools are to check that a
circuit performs the same Boolean function as
the associated logic.
Layout vs. Schematic tools (LVS) check that
transistors in a layout are connected in the
same way as in the circuit schematic.
Design rule checkers (DRC) verify that the
layout satisfies design rules.
Electrical rule checkers (ERC) scan for other
potential problems such as noise or premature
wearout;

1: Introduction

CMOS VLSI Design

4th Ed.

15

Fabrication, Packaging, and Testing

The mask descriptions are sent to the
manufacturer electronically for fabrication.

Two common formats for mask descriptions:
Caltech Interchange Format (CIF) (mainly
used in academia)
Calma GDS II Stream Format (GDS:
Graphic Database System) (used in
industry).

A set of masks for a nanometer process can be very expensive.
In a 65 nm process, the mask set costs about $3 million
With a university discount, the cost for a run of 40 small chips
on a multi-project wafer can run about $10,000 in a 130 nm
process down to $2000 in a 0.6 m process.
1: Introduction

CMOS VLSI Design

4th Ed.

Review
1. What do they mean?
1. IC, VLSI, HDL, RTL, LVS, DRC, ERC, CIF, GDSII, BJT,
MOSFET, CMOS
2. Describe brief history of transistors
3. How to make a MOS transistor?
4. What are differences between nMOS and pMOS?
5. What is IC design flow?
6. Describe logic design
7. Describe circuit design
8. Describe physical design
9. What are CMOS logic gates?
10. Sketch a transistor-level schematic for a CMOS 4-input NOR
11. Sketch a transistor-level schematic for a CMOS 4-input NAND
1: Introduction

CMOS VLSI Design

4th Ed.

16