ASIC Design Interview Questions: Verilog Interview Questions Explained

10/12/2016
ASICinterviewQuestion&Answer:VerilogInterviewQuestions
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Showing posts with label Verilog Interview Questions. Show all

posts
Wednesday, June 2, 2010
Newinterviewquestions
1) There is a waveform
in _____|====|________
out_____|=|___|=|______
The output is "high" when the input change the value.
Verilog code
always@(posedge clk or reset)

begin
if(!reset)
begin
in_reg <= 1'b0; // initial value
out <= 1'b0;
end
else
begin
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May (2)
April (7)
February (12)
January (23)
Visitor'scounter
if(in != in_reg)
begin
out <= 1'b1;
in_reg <= in;
end
else
out <= 1'b0;
end
end
VisitorCounter
After synthesis, what will it be look like?
AboutMe
Roy Chan
Specialties in ASIC Design and
Verification from frontend to backend
activities, including RTL coding,
verification (testbench development,
testcase generation and test regression),
logic synthesis, static timing analysis,
Place and route, power analysis, ECO
and final tapeout process. Currently, I
am still looking for a new career.
View my complete profile
There was an error in this gadget
It's like a DFF and a XOR

in D_FFin_reg|XOR| ___ out
|__________________| |
2) How to write a C or C++ code for Strlen
Answer:
int strlen (char *s)

begin
for (int len =0; *s='\0'; s++)
len++;
return (len);
end
Use recurve way

int strlen_r (char *s)
begin
if(*s='\0') return 0;
else return (1 + strlen_r(s+1));
end
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end
Posted by Roy Chan at 10:33 AM No comments:

Labels: Verilog Interview Questions
Friday, January 8, 2010
VerilogInterviewQuestionPart#5
1) What is the difference between unary and logical operators?
Answer:
Unary operators have only one operand, where as logical operators are of two
operands.
2) What is the difference between transport delay and inertial delay?
Answer:
Transport delay is the delay caused by the wires connecting the gates. Wire do
delay the signal they carry, this is due to the wire resistance, capacitance, and
inductance. Simply transport delay is propagation delay on a wire. In verilog
transport delay is modeled as follows:
a <= #10 b; Inertial delay is the time taken by a gate to change its output. It is the
gate delay. In verilog inertial delay is modeled as follows: assign #10 a = b;
Posted by Roy Chan at 9:32 AM 1 comment:
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Thursday, January 7, 2010
VerilogInterviewQuestionsPart#4
1) Write code for 2:1 MUX using different coding methods?
Use assign statement:
7 module mux_using_assign(
8 din_0 , // Mux first input
9 din_1 , // Mux Second input
10 sel , // Select input
11 mux_out // Mux output
12 );
13 //Input Ports
14 input din_0, din_1, sel ;
15 //Output Ports
16 output mux_out;
17 //Internal Variables
18 wire mux_out;
19 //Code Start
20 assign mux_out = (sel) ? din_1 : din_0;
21
22 endmodule //End Of Module mux
Use if statement
7 module mux_using_if(
12 );
13 //Input Ports
15 //Output Ports
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output mux_out;
//Internal Variables
reg mux_out;
//Code Starts Here
always @ (sel or din_0 or din_1)
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end
endmodule //End Of Module mux
Use Case statement

7 module mux_using_case(
12 );
13 //Input Ports
15 //Output Ports
16 output mux_out;
17 //Internal Variables
18 reg mux_out;
19 //Code Starts Here
20 always @ (sel or din_0 or din_1)
21 begin : MUX
22 case(sel )
23 1'b0 : mux_out = din_0;
24 1'b1 : mux_out = din_1;
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25 endcase
26 end
27
28 endmodule //End Of Module mux
2) What's the difference between === and ==?

Answer:
"a===b" a equal to b, including x and z (Case equality)
"a==b" a equal to b, result may be unknown (logical equality)
The equality operators ( = = , ! = ) will yield an x if either operand
has x or z in its bits. Where as the case equality operators ( = = = ,
! = = ) compare both operands bit by bit and compare all bits,
including x and z.
3) Write code for a parallel encoder and a priority encoder?

module pri_encoder_using_assign (
8 binary_out , // 4 bit binary output
9 encoder_in , // 16bit input
10 enable // Enable for the encoder
11 );
12
13 output [3:0] binary_out ;
14 input enable ;
15 input [15:0] encoder_in ;
16
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wire [3:0] binary_out ;

assign binary_out = ( ! enable) ? 0 : (
(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
endmodule
module encoder_using_case(
8 binary_out , // 4 bit binary Output
9 encoder_in , // 16bit Input
10 enable // Enable for the encoder
11 );
12 output [3:0] binary_out ;
13 input enable ;
14 input [15:0] encoder_in ;
15
16 reg [3:0] binary_out ;
17
18 always @ (enable or encoder_in)
19 begin
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binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out
endcase
end
end
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;
12;
13;
14;
15;
endmodule
Posted by Roy Chan at 10:58 PM No comments:

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1) What is the difference between the following two lines of verilog code?
#5 a=b;
a= #5 b;
Answer:
#5 a=b; Wait 5 time units before doing the action for "a=b".
a= #5 b; The value of b is calculated and stored in an internal temp register. After
5 time units, assign this stored value to a.
2) What is the difference between
c foo ? a:b;
and
if(foo) c=a; else c=b;
Answer:
The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a=2'b10
and b=2'b11,
you'd get c=2'b1x.
On the other hand, if treats Xs and Zs as FALSE, so you'd always get c=b.
3) what's difference between $monitor and $display?
Answer:
$monitor: display every time one of it's parameters change.
$display : display once every time they are executed.
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$strobe: display only at the end of the current simulation time

4) What's the different between casex, casez and case statements?
Answer:
casez treats all z as "Don't care".
casex treat all z or x as "Don't care".
case pass all z or x to the result.
Example:
Driving 0
Normal : Logic 0 on sel
CASEX : Logic 0 on sel
CASEZ : Logic 0 on sel
Driving 1
Normal : Logic 1 on sel
Driving x
Normal : Logic x on sel
CASEZ : Logic x on sel
Driving z
Normal : Logic z on sel
5) What's the differenece between wire and reg data type?

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Answer:
Wire is a net data type, represents connections between hardware elements. It's
default value is z.
Reg is a register data type, which represent data storage elements. Registers
retain value until another value is placed onto them. It's default value is x.
e reg.
6) What is defparam used for?
Answer:
Defparam is used to pass a new set of parameters during instantiation
For example:
1 module secret_number;
2 parameter my_secret = 0;
3
4 initial begin
5 $display("My secret number is %d", my_secret);
6 end
7
8 endmodule
9
10 module defparam_example();
11
12 defparam U0.my_secret = 11;
13 defparam U1.my_secret = 22;
14
15 secret_number U0();
16 secret_number U1();
17
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18 endmodule

Wednesday, January 6, 2010
1) Given the following Verilog Code, what value of a "a" is displayed?
always @(clk) begin
a = 0;
a <= 1; $display(a); end Answer: Verilog scheduling semantics basically imply a 4
level deep queue for the current simulation time: 1: Active Evens ( blocking
statements) 2: Inactive Events ( #0 delays, etc) 3: NonBlocking Assign updates (
nonblocking statements ) 4: Monitor Events ($display, $monitor, etc ). Since the
"a=0" is an active event, it's scheduled into the 1st "queue". The "a<= 1" is a non
blocking event, so it's placed into the 3rd queue. Finally, the display statement is
placed into the 4th queue. Only events in the active queue are completed this sim
cycle: 1st sim cycle: a=0, display show a=0; 2nd sim cycle: display a =1; 2)
Show the waveform of the following code:
always @(a)
always@(a)
begin
begin
#10 ( same as blocking statement )
b2 = #10 a; ( #10 as the delay )
b1 =a;
end
end
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Answer:
always @(a)
begin
#10 ( same as blocking statement )
b1 =a;
end
always@(a)
begin
b2 = #10 a; ( #10 as the delay )
end
a ====____________________
b1 _______________________
t =0, t=10ns
at t=10ns, b1 = a;
a ===_____________________
b1 ______________===______
t =0, t=10ns
Read a at time t=0, assign the b2 =a at
10ns
2) Given the following snipet of Verilog code, draw out the waveforms for clk and
a
always @(clk)
begin
a=0;
#5 a=1;
end
Answer:
You should add the always@(posedge clk), otherwise, the result will be unstable.
10 30 50 70 90
clk ___===___===___===___===___===___
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a __________________===__________

1) How re blocking and nonblocking statements executed?
Answer:
In the blocking statement, the RHS will be evaluated and the LHS will be then
updated without any interruptions.
In the nonblocking statement, RHS will be evaluated at the beginning of the time
step. Then the LHS will be updated at the end of the time step. Within the whole
period, the other process can run in parallel.
2) How do you model a synchronous and asynchronous reset in Verilog?
Answer:
Synchronous reset:
always @(posedge clk)
begin
if (reset)
begin
end
end
Asynchronous reset:
always @(posedge clk or negedge reset)
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begin
if (!reset)
begin
end
end
In asynchronous reset, the always block will invoked at the negative edge of the
reset signal, irrespective of clock's value.
3) What happens if there is connecting wires width mismatch?
Answer:
For examples:
RHS[7:0] = LHS[15:0]
The end result is LHS[7:0] = RHS[7:0];
The assignments starts from LSBs of the signals, and ends at the MSB of smaller
width signal.
4) What are different options that can be used with $display statement in Verilog?
%b binary
%c ASCII character
%d Decimal
%h Hexadecimal
%m Hierarchical name
%o Octal
%s Steing
%t Time
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%v Net signal strength

5) Give the precedence order of the operators in Verilog.
Answer:
Precedence rules for operators

+ ! ~ (unary)
highest precedence
*/%
+ (binary)
<< >>
< <= > >=
== != === !==
& ~&
^ ^~
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| ~|
&&
||
?: (conditional operator) lowest precedence
6) Should we include all the inputs of a combinational circuit in the sensitivity

lists? Give reason.
Answer:
Yes, in combinational circuit all inputs should be included in the sensitivity lists,
otherwise, it will result in a synthesis error.
7) What is the difference between a task and a function in verilog?
Answer:
TimeControl statements
Call function or tasks
Function
No, shall execute in one
simulation time unit
Task
Yes
Cannot call tasks
Can call both tasks and

functions
at least 1 input type

argument and shall not
have an output or inout
can have 0 or more

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input type argument
have an output or inout

type argument
arguments of any type
return value
return a single value
shall not return a value

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veerabhadra.vasa@gmail.com Dashboard SignOut

Showing posts with label Verilog Interview Questions. Show all

always@(posedge clk or reset)

After synthesis, what will it be look like?

It's like a DFF and a XOR

int strlen (char *s)

Use recurve way

Posted by Roy Chan at 10:33 AM No comments:

Friday, January 8, 2010

Thursday, January 7, 2010

Use Case statement

2) What's the difference between === and ==?

3) Write code for a parallel encoder and a priority encoder?

wire [3:0] binary_out ;

Posted by Roy Chan at 10:58 PM No comments:

$strobe: display only at the end of the current simulation time

5) What's the differenece between wire and reg data type?

Posted by Roy Chan at 9:59 PM No comments:

Wednesday, January 6, 2010

Posted by Roy Chan at 11:17 PM No comments:

%v Net signal strength

Precedence rules for operators

6) Should we include all the inputs of a combinational circuit in the sensitivity

Cannot call tasks

Can call both tasks and

at least 1 input type

can have 0 or more

input type argument

have an output or inout

arguments of any type

return a single value

shall not return a value

Posted by Roy Chan at 10:04 PM No comments:

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