1

VLSI implementation of an improved multiplier for FFT computation in biomedical

applications

Design of optimized reversible Binary and BCD adders

A novel realization of reversible LFSR for its application in cryptography

Trace Buffer Attack: Security versus observability study in post-silicon debug

FPGA implementation of efficient AES encryption

A secure and lightweight authentication protocol for RFID

Low power high speed VLSI architecture for 1-D Discrete wavelet transform

FPGA implementation of Discrete Wavelet Transform using Distributed Arithmetic

Architecture

Parallel and High-Speed Computations of Elliptic Curve Cryptography Using

Hybrid-Double Multipliers

10

High performance and area efficient Signed Baugh-Wooley multiplier with Wallace
tree using compressors

11

Design of low power and high speed Carry Select Adder using Brent Kung adder

12

Fine-grained pipelining for multiple constant multiplications

13

Implementation of redundant carry save adders on FPGA

14

A Modified Partial Product Generator for Redundant Binary Multipliers

15

Design of carry select adder for low-power and high speed VLSI applications

16

Analysis of test sequence generators for built-in self-test implementation

17

An enhanced architecture for high performance BIST TPG

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A concurrent BIST scheme for read only memories

19

SoC test integration platform

20

A fault tolerant response analyzer with self-error-correction capability

21

Design and Testing of Combinational Logic Circuits Using Built in Self Test Scheme
for FPGAs

22

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

23

Efficient Coding Schemes for Fault-Tolerant Parallel Filters

24

Fault Tolerant Parallel Filters Based on Error Correction Codes

25

An efficient floating point multiplier design for high speed applications using
Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

26

High speed 16-bit digital Vedic multiplier using FPGA

27

FPGA implementation of delay optimized single precision floating point multiplier

28

Implementation of a high speed multiplier for high-performance and low power

applications

29

A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate

30

Generalized parallel CRC computation on FPGA

31

FPGA implementation of efficient AES encryption

32

Serial and parallel interleaved modular multipliers on FPGA platform

33

FPGA realisation of multiplierless FIR filter architectures

34

Wireless sensor network specific low power FIR filter design and implementation on
FPGA

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New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without PreComputation

36

Index-based Round-Robin Arbiter for NoC Routers