Fault characterisation and testability issues of

complementary pass transistor logic circuits

M. Faisal, A. Hasib and A.B.M.H. Rashid
Abstract: Testability of basic and complex logic gates employing complementary pass transistor
logic (CPL) circuits under various single stuck faults has been investigated. Results show that all
stuck-on faults, bridging faults and more than 90% of stuck-at faults in basic CPL gates are
detectable only by current monitoring, generally known as IDDQ testing. It is also shown that all
stuck-open faults in the basic CPL gates are detectable only by logic monitoring using an
appropriate two-pattern test. Testability analysis of a CPL full-adder under a single stuck-on fault
condition shows that stuck-on faults on all MOS transistors of the SUM logic and the CARRY
logic circuit can be detected by signal source current monitoring with appropriate test vectors.
Similarly, stuck-at faults on all MOS transistors of the full-adder can be detected by current
monitoring only, and stuck-open faults on all MOS transistors of the full-adder can be detected by
an appropriate two-pattern test. It is concluded that signal source current monitoring (IDDQ testing)
is the best method for fault detection in CPL circuits, and gives more than 94% fault coverage of
stuck-at, stuck-on and bridging faults; and logic monitoring gives 100% fault coverage of stuckopen faults.

Introduction

Complementary pass transistor logic (CPL) is a new family

of advanced differential CMOS logic that has much higher
speed and lower power consumption compared to conventional static CMOS logic [1]. The main concept behind CPL
is the use of an nMOS pass transistor network for logic
organisation and elimination of the pMOS latch. CPL
consists of complementary inputs/outputs, an nMOS logic
network, and CMOS output inverters. Other attractive
features of this family are lower delay, a lower number of
transistors and less silicon area compared to conventional
CMOS circuits for the same functionality. Arbitrary
Boolean functions can be constructed from the pass
transistor network by combining the basic circuit modules,
an AND/NAND module, an OR/NOR module, and a
XOR/XNOR module. The powerful logic functionality of
CPL due to the multilevel pass transistor network realises
complex Boolean functions efciently with a small number
of nMOS transistors, thus further reducing area and delay
time. Avci et al. [2] presented a general and effective CPL
design method for pipeline circuits that have enhanced
performance over conventional CMOS circuits in terms of
silicon area, speed, and reduced power dissipation. Yano
and co-workers [1] fabricated a 3.8 ns CMOS 16
16 bit
multiplier using CPL, having a speed more than twice as
fast as conventional CMOS due to lower input capacitance

and higher logic functionality. Abu-Khater et al. [3] have

shown that a full adder constructed with CPL provides a
power saving of 50% compared to a conventional CMOS
full adder, and CPL implementation of a Booth encoder for
a multiplier provides 30% power saving and 15% speed
improvement compared to static CMOS implementation. A
novel low-power 32-bit adder has been designed using
conditional sum adder (CSA) architecture and CPL-like
logic structure that outperforms several architectures using
CMOS circuit styles in terms of power and speed [4].
Additionally, many authors have fabricated CPL circuits
and have shown the improvement in both speed and power
compared to conventional CMOS [57]. However, the fault
characterisation and testability issues of CPL circuits have
not yet been presented.
Todays high-performance integrated circuits contain
millions of transistors on a single chip [8]. It is essential to
adopt a design-for-testability (DFT) approach in designing
such complex integrated circuits in order to facilitate testing
and save cost [9]. In previous papers, we reported on a
preliminary study of the testability issue of basic CPL
circuits [10, 11]. This paper reports on rigorous analytic and
simulation results regarding the testability of basic CPL
gates and CPL full-adder circuits for stuck-on, stuck-open,
stuck-at and bridging faults. First a qualitative analysis of
the fault behaviour is performed by fault simulation. The
qualitative analysis and SPICE simulation results show that
for CPL circuits, steady-state supply current testing (IDDQ
testing) gives a very wide range of fault coverage.

r IEE, 2005
IEE Proceedings online no. 20041113
doi:10.1049/ip-cds:20041113
Paper rst received 27th October 2003 and in revised form 23rd August 2004
M. Faisal and A.B.M.H. Rashid are with the Department of Electrical and
Electronic Engineering, Bangladesh University of Engineering and Technology,
Dhaka-1000, Bangladesh
A. Hasib is with the Institute of Information and Communication Technology,
Bangladesh University of Engineering and Technology, Dhaka-1000,
Bangladesh
E-mail: abdulhasib@iict.buet.ac.bd
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005

Fault analysis of basic CPL circuits

Figure 1 shows basic CPL circuits. The behaviour of these

circuits for various single stuck-on, stuck-open, stuck-at and
bridging faults has been analysed. The fault strength for all
cases except stuck-open faults was varied from 0 to 20 kO.
SPICE level-3 parameters were used for the simulations and
the normal operating current was 5 pA.
215

M1

M4

M3

Q
NAND

M1

M3

A
M4

M2

Q
AND

B
M2

M4

B
M2

2.1

M1

Fig. 1

M3

Q
OR

Q
EXOR

NOR

EXNOR

Basic CPL circuits

Struck-on fault

If a transistor is permanently ON irrespective of the input

signal applied at the gate then it is referred to as stuck-on.
This fault may occur when the source and drain terminals
of a transistor are short-circuited due to mask misalignment
or excessive sourcedrain out-diffusion. This type of fault
can be modelled by placing a resistance Rf indicating fault
strength in parallel with the transistor between the
respective terminals.
Figure 2 shows the fault simulation circuit of a stuck-on
fault on MOS M1 in a CPL AND gate with test vector
[A 1, B 0]. The test vectors [A 0, B 0], [A 0, B 1]
and [A 1, B 1] produce the correct logic and no
signicant current ows. However, when input vector
[A 1, B 0] is applied, M2 turns ON and a huge current
ows through Rf and M2. In a fault-free circuit, the vector
[A 1, B 0] would have pulled the output node down to
ground level, i.e. would produce the correct logic. In the
faulty circuit, the output voltage becomes


1
Vout Ron =Rf Ron VIH
where Ron is the ON resistance of M2 and VIH is the input
high logic level at A. When fault strength is maximum, i.e.
Rf approaches zero, Vout approaches VIH, and when Rf is
very large Vout approaches 0 V. Now since Vout can attain
any value from 0 to VIH, hence, the stuck-on fault at M1

VIH

cannot be detected by logic monitoring. However, steadystate current is very large due to the low resistance path
between VIH and ground. Steady-state current is given by
I VIH =Rf Ron
2
Hence, the fault can be detected by current monitoring, i.e.
IDDQ testing.
SPICE simulation has been used to analyse the effect of
stuck-on fault on all transistors of all the basic CPL gates.
Figure 3 shows the variation of output voltage Vout and
signal current IDDQ as a function of Rf for a fault on the
transistor M1 of the basic CPL AND gate with test vector
[A 1, B 0]. This is in agreement with the analysis made
above. The simulation revealed that the current under fault
condition, varied from 3 mA to 0.24 mA, whereas the
normal operating current was only 5 pA. Thus, this fault
can be detected by current monitoring. Similarly it has been
found that all single stuck-on faults in all CPL basic circuits
can be detected by current monitoring by applying
appropriate test vectors, but no logic monitoring is possible.
The result is summarised in Table 1.

2.2

Stuck-at fault

It is assumed that this fault causes a line in the circuit to

behave as if it were permanently at logic 0 or logic 1. If
the line is permanently at logic 0 it is said to be stuck-at-0:
if the line is permanently at logic 1 it is said to be stuck-at-1
[12]. We have considered two types of stuck-at fault: (i) a

A
0

5
M1

output voltage, V

VIH

Rf

M2

1
3
current (mA)
2

output voltage

current IDDQ, mA

3
0
0

10

15

20

fault strength Rf, k

Vout

Fig. 2 Simulation circuit for stuck-on fault on MOS M1 of CPL

AND gate for test vector [A 1, B 0]
216

Fig. 3 Variation of output voltage Vout and signal current IDDQ

with fault strength Rf for stuck-on fault on M1 of CPL AND circuit
for test vector [A 1, B 0]
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005

Table 1: Simulation results for stuck-on faults

circuit the output voltage is given by



Vout Rf =Rf Ron VIH

Stuck-on
MOS

Test vector AND/NAND OR/NOR

/ABS
gate
gate

XOR/XNOR
gate

M1

(00)

no

no

no

(01)

no

yes

yes

(10)

yes

no

no

(11)

no

no

yes

(00)

no

no

yes

When fault strength is maximum, i.e. Rf approaches zero,

Vout approaches 0 V and when Rf is very large Vout
approaches VIH. Now since Vout can attain any value from
0 to VIH depending on Rf, the stuck-at fault at M2 cannot
be detected by logic monitoring. However, the steady-state
current is large due to the low resistance path between VIH
and ground. The steady-state current is given by

(01)

yes

no

no

I VIH =Rf Ron

(10)

no

yes

yes

(11)

no

no

no

(00)

no

no

yes

(01)

yes

no

no

(10)

no

yes

yes

(11)

no

no

no

(00)

no

no

no

(01)

no

yes

yes

(10)

yes

no

no

(11)

no

no

yes

M3

M4

Minimum fault current, IDDQ 0.1588 mA

In all cases no logic monitoring is possible, but current monitoring
is possible with an appropriate test vector (denoted yes)

Hence, the fault can be detected by current monitoring, i.e.

IDDQ testing.
SPICE simulation was carried out for single stuck-at
faults between gate and source/drain terminals in all basic
gates. Figure 5 shows that output current varies from
3.05 mA to 0.158 mA. Hence the fault is detectable by
current monitoring. Similar analysis and SPICE simulations
were performed for other gates. It has been found that all
stuck-at faults can be detected by current monitoring,
except for MOS M3 in AND/NAND gates and MOS M2 in
OR/NOR gates in which the gate and drain terminals have
the same input variable. Simulation results are summarised
in Tables 2 and 3.

4
1
output voltage, V

stuck-at fault between gate and source; and (ii) a stuck-at

fault between gate and drain. As with the stuck-on fault,
this fault is modelled by placing a resistor Rf between the
gate and source/drain terminals of the faulty device as
shown in Fig. 4. This gure shows the simulation circuit for
a gate to source stuck-at fault on MOS M2 of the basic CPL
AND gate for test vector [A 1, B 1].
The test vector [A 0, B 1] produces the correct output
logic and no signicant current ows. However, when
vectors [A 0, B 0], [A 1, B 1] and [A 1, B 0] are
applied, the fault can be detected. When test vector [A 1,
B 1] is applied, MOS M1 turns ON and a short circuit
current ows through Rf and M1. In a fault-free circuit this
vector would produce a high level output. In the faulty

2
current (mA)
output voltage

3
0

0
VIH

current IDDQ, mA

M2

10

15

20

fault strength Rf , k

VIH

Fig. 5 Variation of output voltage Vout and signal source current

IDDQ as a function of Rf for stuck-at fault between gate and source
on MOS M2 of AND gate for test vector [A 1, B 1]

VIH
M1

2.3

M2
B
Rf

Vout

Fig. 4 Simulation circuit for stuck-at fault between gate and

source of MOS M2 of AND gate for test vector [A 1, B 1]
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005

Stuck-open fault

Physical defects or electromigration in aluminum conductors may cause a MOS transistor to become permanently
open and insensitive to its input signal. To model a stuckopen fault a large resistance is inserted between the source/
drain terminal and the circuit node to which the terminal
would otherwise be connected.
A single stuck-open fault can be detected by applying a
two-pattern test; the rst vector to be applied is called the
initialisation vector and the second vector is called the test
vector [13, 14]. Two vectors are applied to the faulty circuit
sequentially. These two vectors are chosen so that under
fault-free conditions, the outputs are complements to each
other. The rst one initialises the relevant output node to a
denite logic state. The second one sensitises the fault; it
causes both nMOS devices connected to the same output
node to be OFF. As a result the output node becomes
217

Table 2: Simulation results for stuck-at fault between gate

and source of MOS trasnsistor
Stuck-at
MOS

Test vector AND/NAND OR/NOR

/ABS
gate
gate

XOR/XNOR
gate

M1

(00)

yes

VIH

VIH

VIH
M1

M2

M3

M4

no

yes

(01)

yes

yes

yes

(10)

no

no

no

(11)

no

yes

no

(00)

yes

no

no

(01)

no

no

no

(10)

yes

yes

yes

(11)

yes

no

yes

(00)

no

yes

yes

(01)

yes

yes

yes

(10)

no

no

no

(11)

no

yes

no

(00)

yes

no

no

(01)

no

no

no

(10)

yes

yes

yes

(11)

yes

no

yes

Minimum fault current, IDDQ 0.1588 mA

In all cases no logic monitoring is possible, but current monitoring
is possible with an appropriate test vector (denoted yes)

Table 3: Simulation results for stuck-at fault between gate

and drain
Stuck-at
MOS
M1

M2

M3

M4

Test Vector AND/NAND OR/NOR

/ABS
gate
gate

XOR/XNOR
gate
yes

o004

no

yes

o014

yes

no

no

o104

yes

no

no

o114

no

yes

yes

o004

yes

no

yes

o014

yes

no

no

o104

yes

no

no

o114

yes

no

yes

o004

no

yes

no

o014

no

yes

yes

o104

no

yes

yes

o114

no

yes

no

B
Rf

Cout
Vout

Fig. 6 Stuck-open fault in M1 of CPL AND gate with test vector

[A 1, B 1] applied after initialisation vector [A 0, B 0]

node is disconnected from either of the two input nodes A

and B, and is oating, thereby retaining the previous logic
low level. This faulty level can be read quickly to indicate
the presence of the stuck-open fault on M1. Similar analysis
of all the circuits of Fig. 1 shows that all single stuck-open
faults result in incorrect output logic and therefore can be
detected by logic monitoring.
SPICE simulations were carried out for all single stuckopen faults in all the basic CPL gates. The output node was
connected to a 0.1 pF capacitor. For all SPICE simulations
of stuck-open faults, the minimum value of fault strength
was taken as 10 MO. In all cases, the sensitising vector was
applied within 10 ns after application of the initialisation
vector. The output was monitored after a time delay of
100 ns. This monitoring time is far less than the leakage
current time constant. The result is summarised in Table 4.

2.4

Bridging fault

A bridging fault is generally dened as a short between two

or more signal lines in the circuit as shown in Fig. 7. Such a
Table 4: Simulation results for stuck-open faults

o004

yes

yes

yes

Stuck-open

AND/NAND

OR/NOR

XOR/XNOR

o014

no

no

no

MOS

o104

no

no

no

o114

yes

yes

yes

Successful
2-pattern
test
oAB,AB4

Successful
2-pattern
test
oAB,AB4

Successful
2-pattern
test
oAB,AB4

Minimum fault current, IDDQ 0.25 mA

In all cases no logic monitoring is possible, but current monitoring
is possible with an appropriate test vector (denoted yes)

M1
M2

oating and the circuit exhibits sequential behaviour. The

output node retains its previous logic level for some time
before being discharged due to leakage current owing in
the circuit. Reading the output logic level soon after
application of the sensitising vector would show a faulty
output thereby indicating the presence of a stuck-open fault.
In the circuit of Fig. 6, application of input vector [A 0,
B 0] initialises the output node to a logic low level. When
the sensitising vector [A 1, B 1] is applied, the output
218

M2

M3
M4

o00, 114

o01,004

o01,004

o10,114

o11,004

o10,004

o11,004

o00,014

o00,014

o11,104

o00,114

o11,014

o11,004

o00,014

o00,014

o11,104

o00,114

o11,014

o00,114

o01,004

o01,004

o10,114

o11,004

o10,004

Maximum fault current, IDDQ 132.8 nA

In all cases the fault is detectable by logic monitoring using an
appropriate two-pattern test
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005

Figure 9 shows CPL full-adder SUM and CARRY logic

circuits. The behaviour of these circuits under various single
stuck-on, stuck-at and stuck-open faults has been analysed
and is detailed in the following Sections.

M4

M1

Fault characterisation of CPL full-adder

3.1
M2

M3

Q
OR

Rf

Q
NOR

Fig. 7 Bridging fault between complementary output terminals of

OR/NOR gate

output voltage, V

3
1.0
2
0.5

Q
Q

IDDQ

source current IDDQ, mA

1.5

Stuck-on fault

Similar analysis and SPICE simulations as done for basic

CPL gates was performed for a single stuck-on fault on all
the transistors of SUM logic and CARRY logic circuits. It
was found that for the SUM logic circuit a single stuck-on
fault on all the eight transistors was detectable by current
monitoring using appropriate test vectors. For some test
vectors, the fault was detected by logic monitoring, but in
all cases a large ow of signal current was observed.
Consider a single stuck-on fault on MOS M5 of the CPL
full-adder SUM logic circuit. The fault is modelled in Fig. 9.
The test vectors (000), (010), (100) and (110) produce
correct logic and no signicant current ows in the circuit.
Hence these vectors are incapable of detecting the fault. For
test vectors (001), (011), (101) and (111), a large signal
source current ows and the fault is detected by current
monitoring. In Fig. 10, the test vector (001) is applied, M3,
M4, M7 and M8 turn ON and steady-state current IDDQ
ows through M4, M7, Rf and M3 of the circuit. In the
faulted circuit, the output voltage is


5
Vout Rf Ron =Rf 3Ron VIH

M2
A

M1

A
0

10
fault strength, k

15

M3

0
20
M4
M6

Fig. 8 Variation of Vout and IDDQ with fault strength Rf for output
bridging of AND/NAND module

M5

fault may occur due to defective masking or etching,

breakdown of insulator, etc. [15].
In the case of output bridging, as the output logic levels
are complementary, one MOS from each section of a basic
logic module remains ON for any test pattern. Obviously,
this type of fault cannot be detected by logic monitoring,
however, signal current owing through the MOS transistors and the fault resistance Rf is large and is given by
I VIH =2Ron Rf . In the case of input bridging, for
appropriate test patterns the steady state current is very
large compared to the normal operating current and is given
by I VIH =Rf .
SPICE simulation was carried out to analyse the effect of
input/output bridging faults for all the basic CPL circuit
modules. Figure 8 shows the variation of output voltage
Vout and signal source current IDDQ as a function of Rf for
AND/NAND module. The current under fault conditions
varies from 1.46 mA to 0.156 mA, which is much higher
than the normal operating current, and hence, this type of
fault can be detected by current monitoring. Similar results
have been obtained for other gates.
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005

M8

M7
a

M1

M2

M6

M5

B
B

M7

M3
M4

M8
M10
M9

A
M11

C
M12
b

Fig. 9

CPL full-adder logic circuit

a SUM
b CARRY
219

VIH

3.2

VIH

A
VIH

M3
M4

VIH

3.3

Stuck-open fault

Similar fault analysis and SPICE simulations have been

performed for stuck-open faults on all transistors of SUM
logic and CARRY logic circuits of the full-adder. Simulation results are summarised in Tables 9 and 10.

Stuck-at fault

Similar analysis and SPICE simulations have been carried

out for stuck-at faults on all transistors of SUM logic and
CARRY logic circuits, and simulation results are summarised in Tables 7 and 8.

M5

M7

Rf

Testability issues of CPL circuits

The qualitative analysis and simulation results presented in

Sections 2 and 3 show that for CPL basic circuits steadyVout

Fig. 10 Equivalent circuit for stuck-on fault on M5 of CPL fulladder SUM circuit for test vector [A 0, B 0, C 1]

The above equation shows that when fault strength is a

maximum, i.e. Rf approaches zero, Vout approaches VIH/3
and when Rf is very large Vout approaches VIH. Now since
Vout can attain any value from VIH/3 to VIH depending on
Rf. Hence the stuck-on fault at M5 cannot be detected by
logic monitoring. However, the steady state current is high
due to the low resistance path between VIH and ground.
The steady-state current is given by
I VIH =Rf 3Ron

Table 6: Simulation results for stuck-on faults in CPL fulladder CARRY circuit
Fault

Successful Test Vector oABC4

LM

CM

M1

(001),(100)

no

yes

M3

(011),(110)

no

yes

M5

(011),(110)

no

yes

M7

(001),(100)

no

yes

M9

(001),(011)

no

yes

M11

(100),(110)

no

yes

Minimum fault current, IDDQ 0.195mA

Logic monitoring LM, current monitoring CM

Hence, the fault can be detected by current monitoring

(IDDQ testing).
The signal source current is approximately 5.4 mA with a
fault strength of 100 ohms, compared to the normal
operating current of 5 pA. The result is summarised in
Table 5. Similarly, for the CARRY logic circuit, a stuck-on
fault on all twelve transistors can be detected by current
monitoring with appropriate test vectors. For some test
vectors, the fault can be detected by logic monitoring, but in
all cases, it is also accompanied by large signal source
current ow. The result is summarised in Table 6. For the
CPL full-adder CARRY circuit, M1 and M2; M3 and M4;
M5 and M6; M7 and M8; M9 and M10; and M11 and M12
have the same results.

Table 7: Simulation results for stuck-at faults in CPL fulladder SUM circuit
Fault

Successful Test Vector oABC4

LM

CM

M1

(010),(011), (110), (111)

no

yes

M2

(000),(001), (100), (101)

no

yes

M3

(000),(001), (100), (101)

no

yes

M4

(010),(011), (110), (111)

no

yes

M5

(000),(001), (110), (111)

no

yes

M6

(010),(011), (100), (101)

no

yes

M7

(010),(011), (100), (101)

no

yes

M8

(000),(001), (110), (111)

no

yes

Minimum fault current, IDDQ 0.232 mA

Logic monitoring LM, current monitoring CM

Table 5: Simulation results for stuck-on faults in CPL fulladder SUM circuit
Fault

Successful test vector oABC4

LM

CM

M1

(000),(001), (010), (011)

no

yes

M2

(000),(001), (010), (011)

no

yes

M3

(100),(101), (110), (111)

no

M4

(100),(101), (110), (111)

no

M5

(001),(011), (101), (111)

M6

Table 8: Simulation results for stuck-at faults in CPL fulladder CARRY logic circuit
Fault

Successful test vector oABC4

LM

CM

yes

M1

(001), (010) (011),(101)

no

yes

yes

M3

(000),(100) (110),(111)

no

yes

no

yes

M5

(000),(001) (011),(111)

no

yes

(001),(011), (101), (111)

no

yes

M7

(010),(100) (101),(110)

no

yes

M7

(000),(010), (100), (110)

no

yes

M9

(011), (100)

no

yes

M8

(000),(010), (100), (110)

no

yes

M11

(000),(001) (010),(101) (110),(111)

no

yes

Minimum fault current, IDDQO 0.194 mA

Logic monitoring LM, current monitoring CM
220

Minimum fault current, IDDQ 0.2329 mA

Logic monitoring LM, current monitoring CM
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005

Table 9: Simulation results for stuck-open fault in CPL fulladder SUM circuit

Table 10: Simulation results for stuck-open faults in CPL

full-adder CARRY logic circuit

Fault

Successful
two-pattern
vectors

O/P logic
level
un-faulted

O/P logic
level
faulted

LM

CM

Fault

Successful
two-pattern
vectors
oABC4

M1

(000,100)

01

00

yes

no

(011,100)

01

00

yes

no

M1

(000,111)

0,1

0,0

yes

no

(100,110)

0,1

0,0

yes

no

M2

(101,100)

01

00

yes

no

(110,100)

01

00

yes

no

M7

M8

(011,100)

1,0

1,1

yes

no

1,0

1,1

yes

no

10

11

yes

no

10

11

yes

no

(110,100)

1,0

1,1

yes

no

no

(111,100)

1,0

1,1

yes

no

no

(100,101)

0,1

0,0

yes

no

(101,000)

1,0

1,1

yes

no

10
10

11
11

yes
yes

M5

(101,111)

01

00

yes

no

(110,111)

01

00

yes

no

(111,000)

1,0

1,1

yes

no

no

(101,001)

1,0

1,1

yes

no

no

(110,001)

1,0

1,1

yes

no

(111,001)

1,0

1,1

yes

no

(001,000)

10
10

11
11

yes
yes

(011,000)

10

11

yes

no

(100,000)

10

11

yes

no

(111,000)

10

11

yes

no

(000,010)

01

00

yes

no

M7
M9

(100,011)

0,1

0,0

yes

no

(110,010)

0,1

0,0

yes

no

(011,100)

1,0

1,1

yes

no

0,1

0,0

yes

no
no

(111,101)

10

11

yes

no

(000,101)

(000,001)

01

00

yes

no

(001,101)

0,1

0,0

yes

no

(010,100)

0,1

0,0

yes

no

(101,010)

1,0

1,1

yes

no

(011,001)

M6

CM

(001,110)

(010,000)

M5

LM

(001,101)
(111,101)

M4

O/P logic
level
faulted

(101,100)

(010,101)

M3

M3

O/P logic
level
un-faulted

01

00

yes

M11

(101,001)

01

00

yes

no

(001,011)

10

11

yes

no

(110,010)

1,0

1,1

yes

no

(100,011)

10

11

yes

no

(111,010)

1,0

1,1

yes

no

(111,011)

10

11

yes

no

(001,000)

10

11

yes

no

(111,000)

10

11

yes

no

(000,110)

01

00

yes

no

(110,010)

01

00

yes

no

(001,100)

10

11

yes

no

(101,100)

10

11

yes

no

(001,110)

01

00

yes

no

(111,110)

01

00

yes

no

(000,001)

01

00

yes

no

(110,001)

01

00

yes

no

(010,011)

10

11

yes

no

(100,011)

10

11

yes

no

(000,111)

10

11

yes

no

(110,111)

10

11

yes

no

(010,101)

01

00

yes

no

(100,101)

01

00

yes

no

Maximum fault current, IDDQ 16.91 nA

Logic monitoring LM, current monitoring CM

state supply current (IDDQ) testing gives fault coverage of

more than 94% for stuck-on, stuck-at and bridging faults.
For stuck-on and stuck-at faults on the CPL full adder
circuit, IDDQ testing gives fault coverage of 100% for both
the SUM logic circuit and the CARRY logic circuit. This
gives a tremendous opportunity to use IDDQ testing for fault
monitoring in CPL circuits.
For both on-chip and off-chip current testing, rst the
upper limit of device complexity for which current testing is
applicable has to be determined. As seen from the results
presented in Sections 2 and 3, the smallest increase in power
IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005

Maximum fault current, IDDQ 56.99 nA

Logic monitoring LM, Current monitoring CM

supply current occurs for a bridging fault between output

terminals. In this case, the minimum current under fault
conditions is 0.156 mA for a fault strength of 20 kO,
whereas the maximum normal operating current is 100 pA.
The ratio of this fault current to normal operating current is
1.56
106. If we consider a safety factor of 100, then for
every 15 600 basic CPL circuits, one current monitoring unit
is required. To facilitate this, the main power supply rail can
be divided into multiple rails, each supplying current to
approximately 15600 basic CPL gates. One current
monitoring circuit will be required for each VDD rail.
To examine the effect of process parameter variations on
IDDQ testing of CPL circuits, SPICE simulations were
carried out by varying the key process parameters of the
model 720% from their nominal value. It has been found
that the fault current in such cases varies from approximately 1.17 mA to 1.75 mA for the device under consideration. This is much higher than the normal operating current,
which is in the range of a few picoamps. This indicates that
the IDDQ testing method works for our devices even with a
large variation of process parameters.
Stuck-open faults are detectable only by a two-pattern
test. While IDDQ testing for a complete chip can be done by
monitoring the steady state current owing through the
VDD bus, a two-pattern test requires application of test
vectors at the basic gate level, which is almost impossible for
a VLSI chip containing hundreds of thousands of gates.
However, a scan based test using shift registers can be
applied to the critical portion of the circuit detect to stuckopen fault.
221

There are many new defect mechanisms affecting

advanced CMOS technologies. These are gate oxide failure,
ultra-thin oxide reliability etc. Dielectric breakdown of gate
oxide would turn on the drain-back-gate or source-backgate junction and a large forward current would ow, which
could be detected by IDDQ testing. However, gate oxide
thickness reduction in deep submicron technology could
lead to parametric failure. Parametric failure in CMOS ICs
leads to severe detection problem. Detection of these new
types of fault is still a nascent research area and much work
is being done to overcome the difculties [1618].
5

Conclusions

Theoretical analysis and SPICE simulations of the testability of basic CPL circuits under various single stuck faults
has been presented. It was found that all stuck-on faults on
all CPL basic gates were detected by current monitoring but
no logic monitoring was possible. Similar results have been
obtained for stuck-at faults between gate and source of the
MOS devices of all basic CPL gates. However, for stuck-at
faults between gate and drain, it was found that all stuck-at
faults between gate and drain could be detected by current
monitoring except for the following two MOS devices: (i)
MOS M3 of the basic AND/NAND gate and (ii) MOS M2
of the basic OR/NOR gate for which the gate and drain
terminals have the same input variable. In the case of stuckopen faults, it was found that stuck-open faults on all MOS
transistors of all basic CPL gates were detected with logic
monitoring by applying an appropriate two-pattern test.
Stuck-at and stuck-on are the most common faults on VLSI
circuits and for CPL basic gate circuits IDDQ testing gives
fault coverage of more than 94% for stuck-at, stuck-on and
bridging faults. In the case of a CPL full-adder, we have
found that stuck-on and stuck-at faults on all transistors of
SUM logic and CARRY logic circuits can be detected by
current monitoring, i.e. IDDQ testing provides 100% fault
coverage. Like CPL basic circuits, stuck-open faults on all
transistors of a CPL full-adder are detectable by logic
monitoring applying an appropriate two-pattern test.
Therefore, it can be concluded that signal source current
monitoring (IDDQ testing) is the best method for common
fault detection in CPL circuits and that it gives a very wide
range of fault coverage. Again for detecting stuck-open
faults, logic monitoring with a two-pattern test is the only
available method so far and for CPL basic circuits it gives
fault coverage of 100%. Therefore, other than low power

222

consumption, higher speed and higher logic functionality,

CPL circuits are also very promising from a testability point
of view.
6

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IEE Proc.-Circuits Devices Syst., Vol. 152, No. 3, June 2005