An all-pass filter is that which passes all frequency components of the input signal without

attenuation but provides predictable phase shifts for different frequencies of the input signals. The
all-pass filters are also called delay equalizers or phase correctors. An all-pass filter with the output
lagging behind the input is illustrated in figure.

The output voltage vout of the filter circuit shown in fig. (a) can be obtained by using the superposition
theorem
vout = -vin +[ -jXC/R-jXC]2vin
Substituting -jXC = [1/j2fc] in the above equation, we have
vout = vin [-1 +( 2/ j2Rfc)]
or vout / vin = 1- j2Rfc/1+ j2Rfc

where / is the frequency of the input signal in Hz.

From equations given above it is obvious that the amplitude of v out / vin is unity, that is |vout | = |vin|
throughout the useful frequency range and the phase shift between the input and output voltages is
a function of frequency.By interchanging the positions of R and C in the circuit shown in fig. (a), the
output can be made leading the input.These filters are most commonly used in communications. For
instance, when signals are transmitted over transmission lines (such as telephone wires) from one
point to another point, they undergo change in phase. To compensate for such phase changes, allpass filters are employed.

Band Pass Filter

A band-pass filter is a circuit which is designed to pass signals only in a certain band of frequencies
while attenuating all signals outside this band. The parameters of importance in a bandpass filter are

the high and low cut-off frequencies (fH and fl), the bandwidth (BW), the centre frequency f c, centrefrequency gain, and the selectivity or Q.
There are basically two types of bandpass filters viz wide bandpass and narrow bandpass
filters. Unfortunately, there is no set dividing line between the two. However, a bandpass filter is
defined as a wide bandpass if its figure of merit or quality factor Q is less than 10 while the
bandpassfilters with Q > 10 are called the narrow bandpass filters. Thus Q is a measure of
selectivity, meaning the higher the value of Q the more selective is the filter, or the narrower is the
bandwidth (BW). The relationship between Q, 3-db bandwidth, and the centre frequency f c is given by
an equation For a wide bandpass filter the centre frequency can be defined as where fH and fL are
respectively the high and low cut-off frequencies in Hz.In a narrow bandpass filter, the output voltage
peaks at the centre frequency fc.

Wide Bandpass Filter

A wide bandpass filter can be formed by simply cascading high-pass and low-pass sections and is
generally the choice for simplicity of design and performance though such a circuit can be realized
by a number of possible circuits. To form a 20 db/ decade bandpass filter, a first-order high-pass
and a first-order low-pass sections are cascaded; for a 40 db/decade bandpass filter, second-order
high- pass filter and a second-order low-pass filter are connected in series, and so on. It means that,
the order of the bandpass filter is governed by the order of the high-pass and low-pass filters it
consists of. A 20 db/decade wide bandpass filter composed of a first-order high-pass filter and a
first-order low-pass filter, is illustrated in fig. (a). Its frequency response is illustrated in fig. (b).

Narrow Bandpass Filter.

A narrow bandpass filter employing multiple feedback is depicted in figure. This filter employs only
one op-amp, as shown in the figure. In comparison to all the filters discussed so far, this filter has
some unique features that are given below.
1. It has two feedback paths, and this is the reason that it is called a multiple-feedback filter.
2. The op-amp is used in the inverting mode.
The frequency response of a narrow bandpass filter is shown in fig(b).Generally, the narrow
bandpass filter is designed for specific values of centre frequency f c and Q or fcand BW. The circuit
components are determined from the following relationships. For simplification of design calculations
each of C1 and C2 may be taken equal to C.
R1 = Q/2 fc CAf

R2 =Q/2 fc C(2Q2-Af)
and R3 = Q / fc C
where Af, is the gain at centre frequency and is given as
Af = R3 / 2R1
The gain Af however must satisfy the condition Af < 2 Q2.
The centre frequency fc of the multiple feedback filter can be changed to a new frequency f c without
changing, the gain or bandwidth. This is achieved simply by changing R 2 to R2 so that
R2 = R2 [fc/fc]2

Active High Pass Filter

The basic electrical operation of an Active High Pass Filter (HPF) is exactly the same as we
saw for its equivalent RC passive high pass filter circuit, except this time the circuit has an
operational amplifier or op-amp included within its filter design providing amplification and gain
control.Like the previous active low pass filter circuit, the simplest form of an active high pass
filter is to connect a standard inverting or non-inverting operational amplifier to the basic RC
high pass passive filter circuit as shown.

First Order High Pass Filter

Technically, there is no such thing as an active high pass filter. Unlike Passive High Pass
Filters which have an infinite frequency response, the maximum pass band frequency
response of an active high pass filter is limited by the open-loop characteristics or bandwidth of
the operational amplifier being used, making them appear as if they are band pass filters with a
high frequency cut-off determined by the selection of op-amp and gain.
In the Operational Amplifier tutorial we saw that the maximum frequency response of an opamp is limited to the Gain/Bandwidth product or open loop voltage gain ( A V ) of the operational
amplifier being used giving it a bandwidth limitation, where the closed loop response of the op
amp intersects the open loop response.
A commonly available operational amplifier such as the uA741 has a typical open-loop
(without any feedback) DC voltage gain of about 100dB maximum reducing at a roll off rate of
-20dB/Decade (-6db/Octave) as the input frequency increases. The gain of the uA741 reduces
until it reaches unity gain, (0dB) or its transition frequency ( t ) which is about 1MHz. This
causes the op-amp to have a frequency response curve very similar to that of a first-order low
pass filter and this is shown below.

Frequency response curve of a typical Operational Amplifier.

Then the performance of a high pass filter at high frequencies is limited by this unity gain
crossover frequency which determines the overall bandwidth of the open-loop amplifier. The
gain-bandwidth product of the op-amp starts from around 100kHz for small signal amplifiers up
to about 1GHz for high-speed digital video amplifiers and op-amp based active filters can
achieve very good accuracy and performance provided that low tolerance resistors and capacitors
are used.Under normal circumstances the maximum pass band required for a closed loop active
high pass or band pass filter is well below that of the maximum open-loop transition frequency.
However, when designing active filter circuits it is important to choose the correct op-amp for
the circuit as the loss of high frequency signals may result in signal distortion.

Active High Pass Filter

A first-order (single-pole) Active High Pass Filter as its name implies, attenuates low
frequencies and passes high frequency signals. It consists simply of a passive filter section
followed by a non-inverting operational amplifier. The frequency response of the circuit is the
same as that of the passive filter, except that the amplitude of the signal is increased by the gain
of the amplifier and for a non-inverting amplifier the value of the pass band voltage gain is given
as 1 + R2/R1, the same as for the low pass filter circuit.

Active High Pass Filter with Amplification

This first-order high pass filter, consists simply of a passive filter followed by a noninverting amplifier. The frequency response of the circuit is the same as that of the
passive filter, except that the amplitude of the signal is increased by the gain of the
amplifier.

For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a
function of the feedback resistor ( R2 ) divided by its corresponding input resistor ( R1 ) value
and is given as:

Gain for an Active High Pass Filter

Where:

AF = the Pass band Gain of the filter, ( 1 + R2/R1 )

= the Frequency of the Input Signal in Hertz, (Hz)

c = the Cut-off Frequency in Hertz, (Hz)

Just like the low pass filter, the operation of a high pass active filter can be verified from the
frequency gain equation above as:

1. At very low frequencies,

< c

2. At the cut-off frequency,

3. At very high frequencies,

= c
> c

Then, the Active High Pass Filter has a gain AF that increases from 0Hz to the low frequency
cut-off point, C at 20dB/decade as the frequency increases. At C the gain is0.707AF, and
after C all frequencies are pass band frequencies so the filter has a constant gain AF with the
highest frequency being determined by the closed loop bandwidth of the op-amp.
When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally
expressed in decibels or dB as a function of the voltage gain, and this is defined as:

Magnitude of Voltage Gain in (dB)

For a first-order filter the frequency response curve of the filter increases by 20dB/decade or
6dB/octave up to the determined cut-off frequency point which is always at -3dB below the
maximum gain value. As with the previous filter circuits, the lower cut-off or corner frequency
( c ) can be found by using the same formula:

The corresponding phase angle or phase shift of the output signal is the same as that given for the
passive RC filter and leads that of the input signal. It is equal to +45o at the cut-off
frequency c value and is given as:

A simple first-order active high pass filter can also be made using an inverting operational
amplifier configuration as well, and an example of this circuit design is given along with its
corresponding frequency response curve. A gain of 40dB has been assumed for the circuit.

Inverting Operational Amplifier Circuit

Frequency Response Curve

Active High Pass Filter Example No1

A first order active high pass filter has a pass band
gain of two and a cut-off corner frequency of 1kHz. If
the input capacitor has a value of 10nF, calculate the
value of the cut-off frequency determining resistor
and the gain resistors in the feedback network. Also,
plot the expected frequency response of the filter.
With a cut-off corner frequency given as 1kHz and a
capacitor of 10nF, the value of R will therefore be:

or 16ks to the nearest preferred value.

The pass band gain of the filter, AF is given as
being, 2.

As the value of resistor, R2 divided by

resistor, R1 gives a value of one. Then, resistor R1must
be equal to resistor R2, since the pass band
gain, AF = 2. We can therefore select a suitable value
for the two resistors of say, 10ks each for both
feedback resistors.
So for a high pass filter with a cut-off corner
frequency of 1kHz, the values of R and Cwill
be, 10ks and 10nF respectively. The values of the
two feedback resistors to produce a pass band gain of
two are given as: R1 = R2 = 10ks
The data for the frequency response bode plot can be
obtained by substituting the values obtained above
over a frequency range from 100Hz to 100kHz into
the equation for voltage gain:

Voltage
Frequen
Gain, (dB)
Gain
cy,
20log( Vo / V
( Vo / Vin
( Hz )
in )
)

100

0.20

-14.02

200

0.39

-8.13

500

0.89

-0.97

800

1.25

1.93

1,000

1.41

3.01

3,000

1.90

5.56

5,000

1.96

5.85

10,000

1.99

5.98

50,000

2.00

6.02

100,000

2.00

6.02

This then will give us the following table of data.

The frequency response data from the table above can now be plotted as shown below. In the
stop band (from 100Hz to 1kHz), the gain increases at a rate of 20dB/decade. However, in the
pass band after the cut-off frequency, C = 1kHz, the gain remains constant at 6.02dB. The upperfrequency limit of the pass band is determined by the open loop bandwidth of the operational
amplifier used as we discussed earlier. Then the bode plot of the filter circuit will look like this.

The Frequency Response Bode-plot for our example.

Applications of Active High Pass Filters are in audio amplifiers, equalizers or speaker systems
to direct the high frequency signals to the smaller tweeter speakers or to reduce any low
frequency noise or rumble type distortion. When used like this in audio applications the active
high pass filter is sometimes called a Treble Boost filter.

Second-order High Pass Active Filter

As with the passive filter, a first-order high pass active filter can be converted into a secondorder high pass filter simply by using an additional RC network in the input path. The frequency
response of the second-order high pass filter is identical to that of the first-order type except that
the stop band roll-off will be twice the first-order filters at 40dB/decade (12dB/octave).
Therefore, the design steps required of the second-order active high pass filter are the same.

Second-order Active High Pass Filter Circuit

Higher-order high pass active filters, such as third, fourth, fifth, etc are formed simply by
cascading together first and second-order filters. For example, a third order high pass filter is
formed by cascading in series first and second order filters, a fourth-order high pass filter by
cascading two second-order filters together and so on.
Then an Active High Pass Filter with an even order number will consist of only second-order
filters, while an odd order number will start with a first-order filter at the beginning as shown.

Cascading Active High Pass Filters

Although there is no limit to the order of a filter that can be formed, as the order of the filter
increases so to does its size. Also, its accuracy declines, that is the difference between the actual
stop band response and the theoretical stop band response also increases.
If the frequency determining resistors are all equal, R1 = R2 = R3 etc, and the frequency
determining capacitors are all equal, C1 = C2 = C3 etc, then the cut-off frequency for any order
of filter will be exactly the same. However, the overall gain of the higher-order filter is fixed
because all the frequency determining components are equal.
In the next tutorial about filters, we will see that Active Band Pass Filters, can be constructed
by cascading together a high pass and a low pass filter.
A monostable multivibrator (MMV) often called a one-shot multivibrator, is a pulse generator
circuit in which the duration of the pulse is determined by the R-C network,connected externally to
the 555 timer. In such a vibrator, one state of output is stable while the other is quasi-stable
(unstable). For auto-triggering of output from quasi-stable state to stable state energy is stored by an
externally connected capacitor C to a reference level. The time taken in storage determines the pulse
width. The transition of output from stable state to quasi-stable state is accomplished by external
triggering. Theschematic of a 555 timer in monostable mode of operation is shown in figure.

555-timer-monostable-multivibrator

Monostable Multivibrator Circuit details

Pin 1 is grounded. Trigger input is applied to pin 2. In quiescent condition of output this input is kept
at + VCC. To obtain transition of output from stable state to quasi-stable state, a negative-going pulse
of narrow width (a width smaller than expected pulse width of output waveform) and amplitude of
greater than + 2/3 VCC is applied to pin 2. Output is taken from pin 3. Pin 4 is usually connected to +
VCC to avoid accidental reset. Pin 5 is grounded through a 0.01 u F capacitor to avoid noise problem.
Pin 6 (threshold) is shorted to pin 7. A resistor R A is connected between pins 6 and 8. At pins 7 a
discharge capacitor is connected while pin 8 is connected to supply VCC.

555 IC Monostable Multivibrator Operation.

For explaining the operation of timer 555 as a monostable multivibrator, necessary internal
circuitry with external connections are shown in figure.

555 monostable-multivibrator-operation

The operation of the circuit is explained below:

Initially, when the output at pin 3 is low i.e. the circuit is in a stable state, the transistor is on and
capacitor- C is shorted to ground. When a negative pulse is applied to pin 2, the trigger input falls
below +1/3 VCC, the output of comparator goes high which resets the flip-flop and consequently the
transistor turns off and the output at pin 3 goes high. This is the transition of the output from stable to
quasi-stable state, as shown in figure. As the discharge transistor is cutoff, the capacitor C begins

charging toward +VCC through resistance RA with a time constant equal to R AC. When the increasing
capacitor voltage becomes slightly greater than +2/3 VCC, the output of comparator 1 goes high,
which sets the flip-flop. The transistor goes to saturation, thereby discharging the capacitor C and the
output of the timer goes low, as illustrated in figure.
Thus the output returns back to stable state from quasi-stable state.
The output of the Monostable Multivibrator remains low until a trigger pulse is again applied. Then
the cycle repeats. Trigger input, output voltage and capacitor voltage waveforms are shown in figure.

Monostable Multivibrator Design Using 555 timer IC

The capacitor C has to charge through resistance R A. The larger the time constant RAC, the longer it
takes for the capacitor voltage to reach +2/3VCC.
In other words, the RC time constant controls the width of the output pulse. The time during which
the timer output remains high is given as
tp

=1.0986RAC

where RA is in ohms and C is in farads. The above relation is derived as below. Voltage across the
capacitor at any instant during charging period is given as
vc = VCC (1- e-t/RAC)
Substituting vc = 2/3 VCC in above equation we get the time taken by the capacitor to charge from 0
to +2/3VCC.
So +2/3VCC. = VCC. (1 et/RAC) or t RAC loge 3 = 1.0986 RAC
So pulse width, tP = 1.0986 RAC s 1.1 RAC
The pulse width of the circuit may range from micro-seconds to many seconds. This circuit is widely
used in industry for many different timing applications.
An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave
generating circuit. Unlike the monostable multivibrator, this circuit does not require any external
trigger to change the state of the output, hence the name free-running. Before going to make the
circuit, make sure your 555 IC is working. For that go through the article: How to test a 555 IC for
working An astable multivibrator can be produced by adding resistors and a capacitor to the basic

timer IC, as illustrated in figure. The timing during which the output is either high or low is determined
by the externally connected two resistors and a capacitor. The details of the astable multivibrator
circuit are given below. Take a look @ 555 Ic Pin configuration and 555 block diagram before
reading further.Pin 1 is grounded; pins 4 and 8 are shorted and then tied to supply +Vcc, output
(VOUT is taken form pin 3; pin 2 and 6 are shorted and the connected to ground through capacitor C,
pin 7 is connected to supply + VCC through a resistor RA; and between pin 6 and 7 a resistor RB is
connected. At pin 5 either a bypass capacitor of 0.01 F is connected or modulation input is applied.

555-Astable-Multivibrator

Astable Multivibrator Operation

For explaining the operation of the timer 555 as an astable multivibrator, necessary internal circuitry
with external connections are shown in figure.

Astable-Multivibrator-Operation
In figure, when Q is low or output VOUT is high, the discharging transistor is cut-off and the capacitor C
begins charging toward VCC through resistances RA and RB. Because of this, the charging time
constant is (RA + RB) C. Eventually, the threshold voltage exceeds +2/3 VCC, the comparator 1 has a
high output and triggers the flip-flop so that its Q is high and the timer output is low. With Q high, the
discharge transistor saturates and pin 7 grounds so that the capacitor C discharges through
resistance RB with a discharging time constant RB C. With the discharging of capacitor, trigger voltage
at inverting input of comparator 2 decreases. When it drops below 1/3V CC, the output of comparator 2
goes high and this reset the flip-flop so that Q is low and the timer output is high. This proves the
auto-transition in output from low to high and then to low as, illustrated in fig ures. Thus the cycle
repeats.

Astable

Multivibrator

using

555

IC

-Design method
The time during which the capacitor C charges from 1/3 VCC to 2/3 VCC is equal to the time the
output is high and is given as tc or THIGH = 0.693 (RA + RB) C, which is proved below.
Voltage across the capacitor at any instant during charging period is given as,vc=VCC(1-et/RC)
The time taken by the capacitor to charge from 0 to +1/3 VCC

1/3 VCC = VCC (1-et/RC)

The time taken by the capacitor to charge from 0 to +2/3 VCC

or t2 = RC loge 3 = 1.0986 RC
So the time taken by the capacitor to charge from +1/3 VCC to +2/3 VCC
tc = (t2 t1) = (10986 0.405) RC = 0.693 RC
Substituting R = (RA + RB) in above equation we have
THIGH = tc = 0.693 (RA + RB) C
where RA and RB are in ohms and C is in farads.
The time during which the capacitor discharges from +2/3 VCC to +1/3 VCC is equal to
the time the output is low and is given as
td or TL0W = 0.693 RB C where RB is in ohms and C is in farads The above equation is worked out
as follows: Voltage across the capacitor at any instant during discharging period is given as
vc = 2/3 VCC e td/ RBC
Substituting vc = 1/3 VCC and t = td in above equation we have
+1/3 VCC = +2/3 VCC e td/ RBC
Or td = 0.693 RBC
Overall period of oscillations, T = THIGH + TLOW = 0.693 (RA+ 2RB) C , The frequency of oscillations
being the reciprocal of the overall period of oscillations T is given as
f = 1/T = 1.44/ (RA+ 2RB)C
Equation indicates that the frequency of oscillation / is independent of the collector supply voltage
+VCC.

Often

the

term

duty

cycle

is

used

in

conjunction

with

the

astable

multivibrator.

The duty cycle, the ratio of the time t c during which the output is high to the total time period
T is given as
% duty cycle, D = tc / T * 100 = (RA + RB) / (RA + 2RB) * 100
From the above equation it is obvious that square wave (50 % duty cycle) output can not be obtained
unless RA is made zero. However, there is a danger in shorting resistance R A to zero. With RA = 0
ohm, terminal 7 is directly connected to + V CC. During the discharging of capacitor through R B and
transistor, an extra current will be supplied to the transistor from V CC through a short between pin 7
and +VCC. It may damage the transistor and hence the timer.
However, a symmetrical square wave can be obtained if a diode is connected across resistor R B, as
illustrated in dotted lines in figure. The capacitor C charges through R A and diode D to approximately
+ 2/3VCC and discharges through resistor RB and terminal 7 (transistor) until the capacitor voltage
drops to 1/3 VCC. Then the cycle is repeated. To obtain a square wave output, R A must be a
combination of a fixed resistor R and a pot, so that the pot can be adjusted to give the exact square
wave.Although the timer 555 has been used in a wide variety of often unique applications it is very
hard on its power supply lines, requiring quite a bit of current, and injecting many noise transients.
This noise will often be coupled into adjacent ICs falsely triggering them. The 7555 is a CMOS
version of the 555. Its quiescent current requirements are considerably lower than that of 555, and
the 7555 does not contaminate the power supply lines. It is pin compatible with the 555. So this
CMOS version of the 555 should be the first choice when a 555 timer IC is to be used.

r-2r

An alternative to the binary-weighted-input DAC is the so-called R/2R DAC, which

uses fewer unique resistor values. A disadvantage of the former DAC design was its
requirement of several different precise input resistor values: one unique value per
binary input bit. Manufacture may be simplified if there are fewer different resistor
values to purchase, stock, and sort prior to assembly.
Of course, we could take our last DAC circuit and modify it to use a single input
resistance value, by connecting multiple resistors together in series:

Unfortunately, this approach merely substitutes one type of complexity for another:
volume of components over diversity of component values. There is, however, a more
efficient design methodology.
By constructing a different kind of resistor network on the input of our summing circuit,
we can achieve the same kind of binary weighting with only two kinds of resistor
values, and with only a modest increase in resistor count. This ladder network looks
like this:

Mathematically analyzing this ladder network is a bit more complex than for the
previous circuit, where each input resistor provided an easily-calculated gain for that
bit. For those who are interested in pursuing the intricacies of this circuit further, you
may opt to use Thevenins theorem for each binary input (remember to consider the
effects of the virtual ground), and/or use a simulation program like SPICE to

determine circuit response. Either way, you should obtain the following table of
figures:
--------------------------------| Binary | Output voltage |
--------------------------------| 000

0.00 V

--------------------------------| 001

-1.25 V

--------------------------------| 010

-2.50 V

--------------------------------| 011

-3.75 V

--------------------------------| 100

-5.00 V

--------------------------------| 101

-6.25 V

--------------------------------| 110

-7.50 V

--------------------------------| 111

-8.75 V

---------------------------------

As was the case with the binary-weighted DAC design, we can modify the value of the
feedback resistor to obtain any span desired. For example, if were using +5 volts for
a high voltage level and 0 volts for a low voltage level, we can obtain an analog
output directly corresponding to the binary input (011 = -3 volts, 101 = -5 volts, 111 =
-7 volts, etc.) by using a feedback resistance with a value of 1.6R instead of 2R.
Successive approx.
This type of converter is used to convert analog voltage to its corresponding digital output. The
function of the analog to digital converter is exactly opposite to that of a DIGITAL TO ANALOG
CONVERTER. Like a D/A converter, an A/D converter is also specified as 8, 10, 12 or 16 bit. Though
there are many types of A/D converters, we will be discussing only about the successive
approximation type.

Successive

Approximation

Type

Analog

to

Digital

Converter
A successive approximation A/D converter consists of a comparator, a successive approximation
register (SAR), output latches, and a D/A converter. The circuit diagram is shown below. The main
part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A converter. The analog output
Va of the D/A converter is then compared to an analog signal V in by the comparator. The output of the
comparator is a serial data input to the SAR. Till the digital output (8 bits) of the SAR is equivalent to
the analog input Vin, the SAR adjusts itself. The 8-bit latch at the end of conversation holds onto the
resultant digital data output.

Working

At the start of a conversion cycle, the SAR is reset by making the start signal (S)

high. The MSB of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is introduced.
The output is given to the D/A converter which produces an analog equivalent of the MSB and is
compared with the analog input Vin.If comparator output is LOW, D/A output will be greater than
Vin and the MSB will be cleared by the SAR.If comparator output is HIGH, D/A output will be less than
Vin and the MSB will be set to the next position (Q7 to Q6) by the SAR.According to the comparator
output, the SAR will either keep or reset the Q6 bit. This process goes on until all the bits are tried.
After Q0 is tried, the SAR makes the conversion complete (CC) signal HIGH to show that the parallel
output lines contain valid data. The CC signal in turn enables the latch, and digital data appear at the
output of the latch. As the SAR determines each bit, digital data is also available serially. As shown
in the figure above, the CC signal is connected to the start conversion input in order to convert the
cycle continuously.
The biggest advantage of such a circuit is its high speed. It may be more complex than an A/D
converter, but it offers better resolution.

Successive Approximation Type Analog to Digital Converter

DUAL SLOPE TYPE ADC

In dual slope type ADC, the integrator generates two different ramps, one
with the known analog input voltage VA and another with a known reference
voltage Vref. Hence it is called a s dual slope A to D converter. The logic
diagram for the same is shown below.

Operation:
The binary counter is initially reset to 0000; the output of integrator reset to
0V and the input to the ramp generator or integrator is switched to the
unknown analog input voltage VA.
The analog input voltage VA is integrated by the inverting integrator and
generates a negative ramp output. The output of comparator is positive and
the clock is passed through the AND gate. This results in counting up of the
binary counter.
The negative ramp continues for a fixed time period t1, which is determined
by a count detector for the time period t1. At the end of the fixed time period
t1, the ramp output of integrator is given by
VS=-VA/RCt1
When the counter reaches the fixed count at time period t1, the binary
counter resets to 0000 and switches the integrator input to a negative
reference voltage Vref.
Now the ramp generator starts with the initial value Vs and increases in
positive direction until it reaches 0V and the counter gets advanced. When
Vs reaches 0V, comparator output becomes negative (i.e. logic 0) and the
AND gate is deactivated. Hence no further clock is applied through AND gate.
Now, the conversion cycle is said to be completed and the positive ramp
voltage is given by
VS=Vref/RCt2
Where Vref & RC are constants and time period t2 is variable.
The dual ramp output waveform is shown below.

Since ramp generator voltage starts at 0V, decreasing down to Vs and then
increasing up to 0V, the amplitude of negative and positive ramp voltages
can be equated as follows.
Vref/RCt2=-VA/RCt1
t2=-t1VA/Vref
VA=-Vreft1/t2
Thus the unknown analog input voltage VA is proportional to the time period
t2, because Vref is a known reference voltage and t1 is the predetermined
time period.
The actual conversion of analog voltage VA into a digital count occurs during
time t2. The binary counter gives corresponding digital value for time period
t2. The clock is connected to the counter at the beginning of t2 and is
disconnected at the end of t2. Thus the counter counts digital output as
Digital output=(counts/sec) t2
Digital output=(counts/sec)[t1VA/Vref ]
For example, consider the clock frequency is 1 MHz, the reference voltage is
-1V, the fixed time period t1 is 1ms and the RC time constant is also 1 ms.
Assuming the unknown analog input voltage amplitude as VA = 5V, during
the fixed time period t1 , the integrator output Vs is
VS=-VA/RCt1=(-5)/1ms1ms=-5V
During the time period t2, ramp generator will integrate all the way back to
0V.
t2=VS/Vref RC=(-5)/(-1)1ms=5ms=5000s
Hence the 4-bit counter value is 5000, and by activating the decimal point of
MSD seven segment displays, the display can directly read as 5V.