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EECS 242
Class A/B/C
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Class F
Class F Waveforms
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Class F Efficiency
Class F Disadvantages
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Switching Amplifiers
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ce is on the voltage waveform for part of the cycle and on the current
o, but when open the current is is forced to zero. If the set of times during
( vs = 0 )
(3.4)
( D)
( is = 0 )
(3.5)
For
trans-conductance
non-zero portions
require
additional effort.
i
)e
= Zin ( kis
) off, the
take on any value. Likewise, when
the switch
k k
(3.6)
influence it could have on the waveforms is to demanding that, at all
switch current is zero, but the voltage
take
on any
k { 1, 2can
, 3, 4,
}
he ratio between
the voltage and current on its port be equal its port
value
Although this condition is easily written down, it is still not obvious how to apply it in
ntal period T. Similarly, the waveforms will be assumed to be periodic, having the
damental period.
Impedance at Harmonics
ilizing this assumption, the switch voltage and current waveforms, vs and is
harmonic:
v s ( ) = V DC +
v k cos ( k + k )
( v k ik )e
k=1
is ( ) = I DC +
i k cos ( k + k )
k=1
(3.1)
j( k k)
= Zin ( k )
k { 1, 2, 3, 4, }
(3.2)
Although this condition is easily written down, it is still not obvious how
determine
the where
waveforms.
The difficulty lies in the fact that (3.6
ik ,
the normalized
values of the parameters VDC, Iorder
DC,vk, to
k, and k, and
infinite shape,
number therefore,
of independent
frequency domain
conditions which must
The waveform
is completely
determined
with
the--t- very impedance
tight time-domain
conditions
demanded by the switch. Cons
by the
load
network
(its
a
linear
system
2f
t
=
2
(3.3)
0
T
viewed from
this
perspective)
has been exerted
to solve for these waveforms even for specific cases such
Waveform Constraints
of class-E solutions [4,31-42] each solving for a slightly different circuit top
approximations
and
assumptions.
determination the voltages and different
currents for
the a switching
amplifier
can be Typically the solutions are deriv
domain
using
network
utilizing
to determining the voltages and
currents
on the
switch theory,
itself. Once
these different simplifying assumpti
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a dual or inverse switching amplifier tuning. This can be done by simply inv
drive of the switch (so that the switch will be on at times where before it was
Inverseadmittance
Class
of
numerically
equalOperation
to the original load networks impedance. To see
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is ( ) = I DC +
i k cos ( k + k )
k=1
v s ( ) = V DC +
v k cos ( k + k )
k=1
( D)
( is = 0 )
( D)
( vs = 0 )
( i k v k )e
j ( k k )
= Y in ( k )
k { 1, 2, 3, 4, }
Bias Scaling
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Impedance Scaling
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Switch Losses
ZVS
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Switching Inductors
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Class D
Class D-1
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Class E
Class E Currents
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When switch is closed, all the current flows through it. When
open, this same current must flow through the capacitor. The
voltage across the capacitor is given by the integral of the
current since
Class E Voltages
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Class E Current/Voltage
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Switch FOM
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FOM (cont)
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The smaller this ratio, the more the design can tolerate output
capacitance, and hence a larger transistor with lower conductive losses.
I RMS Ron
VSW
---------------------- + -------------------------------------D1 V
I DC
DC I DC 4X CS V
(4.16)
DC
Device
Size Limited
Maximum Drain Efficiency
becomes:
IRMS R on
D 1 ---------------------V DC I DC
(4.17)
P DC Pdiss
VDC I DC I RMS R on
= ----------------------------- = -----------------------------------------------P in
P in
(4.18)
All terms except the third are invariant and only depend on the
tuning strategy.
Minimize the third term by using the highest peak voltage
possible (minimize current through device).
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I RMS Ron
VSW
---------------------- + -------------------------------------D1 V
I DC
DC I DC 4X CS V
(4.16)
DC
becomes:
IRMS R on
D 1 ---------------------V DC I DC
(4.17)
Increase device
2 size until the switch output capacitance equals
P DC Pdiss
VDC I DC I RMS R on
the
total
output capacitance
(4.18)
= ----------------------------- = -----------------------------------------------P in
P in
All terms except the last are invariant (bias, impedance
scaling) and only depend on the switching network. Note the
third term depends on technology but is independent of
transistor size. Voltage waveform properties do not come into
play.
To minimize the final term, maximize Cout. Final efficiency
only depends on technology RC time constant:
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optimized,
constraint
that
Cout
cannot
be larger than CS
2 under
in efficiency, increasing the voltage and
decreasing
theIthe
current
in
this
case
has
no
I RMS
VDC
DC
D 1 ------------ ----------------------------- ( Ron C out ) ( 2f 0 )
(4.36)
,
it
is
clearly
best
to
choose
Cout as
improves
with
increasing
C
2
I
out constant under
on the efficiency. This is due to the fact that
transistor
size is not
DC the 2f
C
V
0 s DC
optimal asized
device is of
therefore
the one
hange. In order to trade voltage for current,
combination
impedance
andwith
biasoutput capacitance eq
The further illuminate the meaning of the somewhat mysterious second term, consider
2
ng must be used. During this process, the RMS current scales Iinversely
with Ithe
V
RMS
DC
that VDCIDC is approximately the equal
to the
output
power
and
thatDC
the- 1( R
( 2f
is )
0 C S) () 2f
-------------------------------------
1
C
on
out
D
0
2
ge level, whereas
the circuit
impedances
scalefurther
proportionally
toIDC
the square
of
the
The
second
term
needs
explanation:
2f
C
V
the magnitude ZC of the switch parallel capacitances impedance
0 s at
DCthe fundamental
ge level. The
capacitance
CS therefore
scalesamplifier,
inversely with
voltage level.
The to
For a highly
efficient
the the
numerator
is equal
frequency:
The further illuminate the meaning of the somewhat mysterious
the
output
power,
and
thethen
denominator
has
thetheswitch
stor size proportional to CS in this case must
scale inversely
with
square
thatI VDCIDC
2 isPapproximately the equal to the output power and th
capacitance
admittance:
RMS
out
e voltage level, causing the on-resistance
scale
the)square
----------- proportionally
--------------------- ( RontoC out
D 1 to
( 2f 0 ) of the
(4.37)
the Imagnitude2 ZC of the switch parallel capacitances impedanc
V DC of
ZCk under the conditions of
ge level. Thus for an increase in the voltageDC
by a factor
frequency:
This is a ratio of the output power to the switchs stored
ant output power, there is a decrease in the ZRMS
current
by)a factor of k and an
(4.38)
(
2f
C
C to use a
0 tuning
S
reactive power. We2 wish
strategy
that
2
2
ase in the on-resistance by a factor of k . The product I RMS RonIRMS
thereforePstays
out
------------------------------- ( Ron C out ) ( 2f 0 )
DC cannot
C
the RMS current through the switch. The voltage
be traded
currentaslike
the previous
s before, the efficiency
may befor
expressed
waveform
figures of case.
merit:Z 1 ( 2f C )
e:
2 ( Ron C out )
2
D 1 ( FI FC ) -------------------------------1 f0
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0 S
Pout
FC ----------------------(4.39)
2
V DC ZC
The transistor property of interest in this case is the RonCout product, whic
Prof. Ali M. Niknejad (C) 2009
Under assumption of
high drain efficiency
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Summary
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Switch/Cap Current
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Cap Voltage
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Constraint Equations
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ZVS
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ZdVS
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ZVS Switching
Inclusion of device output capacitance
Simple circuit implementation
Lower peak voltage (Fv)
Lower RMS current (Fi)
Capacitance Tolerance (Fc)
Class E versus F
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More Waveforms
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Overall Comparison
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Direct Implementation
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Push-Pull Amplifiers
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