Solid-State Electronics 49 (2005) 10811085

www.elsevier.com/locate/sse

Study of 4HSiC trench MOSFET structures

L. Chen *, O.J. Guy, M.R. Jennings, P. Igic, S.P. Wilks, P.A. Mawby
School of Engineering, University of Wales Swansea, Singleton Park, Swansea SA2 8PP, UK
Received 5 August 2004; received in revised form 4 May 2005; accepted 8 May 2005

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract
An investigation of the structures and design parameters of 4HSiC trench inversion-channel MOSFETs using a two-dimensional (2D) numerical device simulation is presented. Material parameters have been adjusted appropriately for the 4HSiC polytype and a systematic characterisation and optimization of a specic trench MOSFET with a 1.2 kV blocking voltage capability has
been performed. Simulations have concentrated on optimizing the p-type doping concentration at the trench bottom, to keep the
breakdown electric eld in the oxide under its critical value. The trench depth was also examined and optimized to give a better
on-state performance. For the MOSFET structure examined, a minimized on-state resistance of 53 mX cm2 was obtained.

2005 Elsevier Ltd. All rights reserved.
Keywords: 4HSiC; Trench MOSFET; Electric eld; Breakdown; On-state resistance

1. Introduction
The superior material properties of 4HSiC, such as
its wide band gap of 3.26 eV and its high critical electric
eld of 2.2 106 V/cm, compared to those of silicon,
mean it is ideally suited for high temperature and high
voltage applications [13]. Power MOSFETs based on
silicon are hampered by the rapid increase in on-resistance with increasing blocking voltage. MOSFETs using
SiC have an on-resistance two orders of magnitude
lower than their silicon counterparts [4,5], and consequently their current handling capability is much higher.
SiC also has an advantage over other wide band gap
materials such as GaN in that it has silicon dioxide as
its native oxide. This makes it easy to produce metaloxide-semiconductor structures by thermally growing
an oxide at the SiC surface. However, the conventional
*

Corresponding author. Tel.: +44 179 251 3181; fax: +44 179 229
5686.
E-mail address: li.chen@swansea.ac.uk (L. Chen).
0038-1101/$ - see front matter
2005 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2005.05.003

thermal oxidation process normally results in a high

density of SiC/SiO2 interface traps (Dit) [6,7], with an
increasing Dit near the edge of conduction band [8].
The high value of Dit consequently results in poor
channel mobility, and limits the on-state current
conductivity.
The trench MOSFET design has several advantages
over the conventional planar DMOSFET structure. In
trench structures, the cell space can be minimized, as
the channel is generated vertically on the trench sidewall
for more ecient use of the wafer. In addition, the width
of the trench groove can be reduced down to the processing limits in order to further reduce on-resistance.
Out of the two commercially available wafer 4H and
6H polytypes, 4HSiC demonstrates more isotropic
electrical properties, a higher band gap energy and
higher carrier mobility, which make it more attractive
for use in the fabrication of vertical MOSFET structures
than 6HSiC. This paper presents the simulation of electrical characteristics of 4HSiC trench MOSFET structures, using the nite element based device simulator

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L. Chen et al. / Solid-State Electronics 49 (2005) 10811085

Academi2d [9], which is a Microsoft Windows based 2D

semiconductor device modelling and circuit simulation
program. It is encouraging to see good performance
from high voltage trench MOSFETs with junction termination extension structure [10], but the current paper
simply focuses on the issue of breakdown within the cell
structure, rather than termination at the periphery of
device.

2. Trench structure and dopant parameters

A half cell cross-section of a SiC trench MOSFET is
shown in Fig. 1. This structure would be fabricated on a
4HSiC wafer with 10 lm thick epitaxial layer (n drift)
grown on top of a heavy doped n+ substrate, followed
by another 1.2 lm p-type epitaxial layer and n+ layer
grown. The n+ epilayer and p epilayer should be served
as source and p-well regions. The trench would be
formed using a dry etching technique, with the channel

dened vertically between the n+ source and n drift

regions in the p-well, just beneath the gate oxide on
the trench sidewall. In forward bias, electrical current
can ow through the trench MOSFET device, from
the drain to the source, if a suciently large voltage is
applied to the gate electrode to generate a n-channel
inversion layer. The current conductivity of the device
is then limited by the on-state voltage drop across the
resistive components between the drain and the source.
In the simulated structure, the dimension of the gate
oxide was 120 nm in thickness, and the source depth was
0.2 lm. The vertical channel length was approximately
1 lm. Both source and p-well regions were assigned a
box shape doping prole. The lateral distance of the
trench bottom was 4 lm and the depth of trench (d in
Fig. 1) was varied between 2 lm and 3 lm. The total lateral cell pitch was 14 lm.
The doping concentration for dierent regions is
listed in Table 1. The p-well doping is crucial in determining the on-state as well as o-state performance of

Fig. 1. Mesh structure and doping regions of the simulated trench MOSFET.

L. Chen et al. / Solid-State Electronics 49 (2005) 10811085

3.1. O-state characteristics

Table 1
Doping concentration distribution and layer thickness
n+ source
3

Doping (cm )
Layer
thickness (lm)

19

1 10
0.2

p-well
1 10
1.0

17

drift region
15

4 10
10

1083

Substrate
1 1019
1.0

MOSFETs. Relatively high doping of the p-well can

prevent the device from suering premature breakdown
in the o-state condition due to p-well punch through.
The disadvantage of a highly doped p-well is that the
threshold turn on voltage is high. An intermediate value
of 1 1017 cm 3 was adopted in this simulation as a
compromise between these two factors. To eliminate
the electric eld enhancement at the trench corner, a
p-type implantation in the trench bottom was used. This
1 lm thick implant had a Gaussian doping prole, and
was self-aligned to the trench bottom. To provide a
good Ohmic contact to the p-well, a shallow p+ implant
(250 nm deep) was adopt adjacent to the n+ source. The
p-well and source were electrically shorted in the simulation. With regard to the SiC/SiO2 interface, a xed interface state density of 1 1012 cm 2 eV 1 was assumed
[11,12].
For the nite element simulations, a mesh was constructed with the nest mesh grid points in the channel,
oxide and pn junction regions. The mesh was subsequently rened as a function of doping contrast, in the
channel region and at the trench bottom. This produced
an approximately 5 nm ne mesh grid in the channel and
trench corner regions and a coarser mesh grid in the
drift region. The bottom left corner of the trench groove
was rounded with a curved radius of 200 nm. The thickness of the heavily doped SiC substrate was scaled down
to 1 lm, in order to speed-up the simulations, and thus,
save on CPU time.

3. Simulation results and discussion

Parameter values for the physical properties of the
4HSiC polytype, used in the simulation, were adjusted
specically for this material. These included the energy
band gap at room temperature, thermal conductivity,
relative permittivity, ionization energies for donors
and acceptors, eective density of states for electron
and hole, electron and hole bulk mobility and the avalanche ionization coecients. These parameters were
abstracted from the published literature [13,14]. The
main physical models used in the simulation were
ShockleyReadHall recombination, impact ionization,
Auger recombination, electric eld dependent mobility
model, and a impurity concentration dependent mobility model. Although 4HSiC has fairly isotropic electric
properties, the nonisotropic eects were included in the
simulations.

The high impact ionization energy in SiC, means that

the electric eld can become very high without initiating
avalanche multiplication of ionized carriers. Due to the
large energy band gap in SiC, the intrinsic carrier concentration at room temperature is extremely low, which
leads to convergence problems when simulating the ostate characteristic. To overcome this numerical problem, the intrinsic carrier concentration has to be raised,
and this was achieved by elevating the material simulation temperature of SiC up to 600 C in this study [11].
The trench MOSFET structure suers a high electric
eld in the gate oxide in the o-state blocking mode, due
to electric eld enhancement at the sharp trench corner.
Oxide breakdown may occur even before avalanche
breakdown in the adjacent SiC region, if parameters of
the structure are not optimized. Although high eld
strengths for SiC oxides of 10 106 V/cm have been reported [15,16], for long-term reliability, the electric eld
in the oxide must not exceed 4 106 V/cm [17]. One critical parameter that must be determined in order to
achieve a high blocking voltage is the p-type doping concentration in the trench bottom. In this study, a range of
p-type dopings was examined. The doping value was
optimized at 2.3 1018 cm 3 to allow the electric eld
at the trench bottom pn junction to reach the critical
value for SiC, while still keeping the oxide peak electric
eld at the trench below 4 106 V/cm. In this case, the
SiC peak electric eld (at breakdown) occurs at the corner of the trench bottom pn junction (Fig. 2). The breakdown voltage of 1293 V was achieved in this condition.
For the designed trench MOSFETs, structures with
p-type doping at the trench bottom lower than 2.3
1018 cm 3 may lead to the electric eld in oxide reaching
4 106 V/cm, before avalanche breakdown occur in SiC.
This can cause destructive damage to the device. On the
other hand, an over heavily doped p+ region in the
trench bottom would lead to a higher built-in electric
eld at the pn junction, eventually causing avalanche
breakdown at a slightly lower voltage.
3.2. On-state characteristic
In the on-state characteristic simulations, a model of
carrier mobility dependent on the impurity concentration and the temperature, and a low channel mobility
incorporation of a perpendicular electric eld dependent
mobility model were employed. In addition, surface
charges were included in the structure.
Simulations were performed to predict the threshold
voltages for the trench structure. This was done by
shorting the gate and drain electrodes together and
ramping up the potential bias applied to the gate and
drain, from zero to a few tens of volts. From the resultant IdsVgs plots, the threshold voltage of 4.0 V for the

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L. Chen et al. / Solid-State Electronics 49 (2005) 10811085

Fig. 2. Electric eld distribution at breakdown for p-type doping at 2.3 1018 cm 3.

1.20E+02

200

180
170
160

140
0.00E+00

3.00E+18

6.00E+18

9.00E+18

1.20E+19

trench bottom p-type implant doping (cm-3)

Fig. 4. On-resistance as a function of the p-type doping in trench

bottom.

180

Vgs 6v
Vgs 8v

160

Vgs 10v

140

Ron (mOhms*cm2)

8.00E+01

190

150

Vgs 4v

1.00E+02

drain current (A/cm2)

210

Ron ( mOhms*cm2)

simulated MOSFET structure was extracted from a line

plot tted to the linear portion of the curve. The forward
characteristic obtained from a MOSFET with a trench
bottom p-type implant at 3 1018 cm 3 is shown in
Fig. 3.
A JFET region is formed in the n drift region, between the p-well and the trench bottom p-type implant.
This JFET eect would introduce a further resistance to
the on-state current. The specic on-resistance can be
extracted from the linear part of the forward IV characteristic at low drain voltage. Fig. 4 shows the specic
on-resistance as a function of the p-type implant doping
in the trench bottom. The value increases quickly as the
doping goes up from 3 1018 cm 3 to 9 1018 cm 3.
The on-resistance plateaus as the doping increases beyond 9 1018 cm 3.
Further investigation indicates that the on-resistance
was dominated by the JFET resistance. The on-resistance

6.00E+01
4.00E+01
2.00E+01

120
100
80
60
40
20
0

0.00E+00
0

10

15

20

drain voltage (V)

Fig. 3. Forward IV characteristic of the trench MOSFET.

1.5

2.5

3.5

trench depth (m)

Fig. 5. On-resistance variation as a function of trench depth.

L. Chen et al. / Solid-State Electronics 49 (2005) 10811085

can be reduced by using a larger trench depth, to increase

the current spreading between the p-well and the trench
bottom p-type implant. This is shown in Fig. 5, where
the on-resistance drops from 160 mX cm2 to 53 mX cm2
as the trench depth increases from 2 lm to 3 lm.

4. Discussion
In the design of SiC trench MOSFETs, maximization
of the blocking voltage while maintaining an appreciably low on-state threshold voltage is desirable. In inversion mode trench MOSFET power devices, premature
oxide breakdown can occur before the critical electric
eld in SiC is reached. This is particularly apparent at
the bottom trench weak point corner, where the electric eld crowding is most severe and the critical electric
eld can be easily exceeded. Such a high electric eld will
lead to catastrophic breakdown in the oxide. This severely limits the potential performance for the SiC
trench MOSFET in the blocking mode.
The blocking voltage can be dramatically inuenced
by improvements in device design, such as incorporating
a p-type implant in the trench bottom. Structures with
heavy p-type doping in the trench bottom can dissipate
the electric eld in oxide, and this ensures that the device
eventually breaks down inside semiconductor rather
than in the dielectric. In this study, the p-type implant
doping concentration should be in the range between
2.3 1018 cm 3 to 5 1018 cm 3 with a Gaussian distribution, for simulated structures with a 1.2 kV rated
blocking voltage. The drawback of introducing the ptype implant to the trench MOSFET is that it restricts
the current spreading due to the JFET region between
the p-well and the p-type implant. Also, high temperature annealing (P1600 C) processes used to activate
the implant could further degrade the mobility at the
surface due to the surface damage known as step bunching [18].

5. Conclusion
Prospects for the development of SiC trench MOSFET structures have been analyzed using 2D numerical
simulations. The o-state characteristics were investigated by varying p-type implant doping concentration
at the trench bottom. It has been demonstrated that
peak electric eld crowding at the trench corner in the
gate oxide is a major limiting factor with respect to high
blocking voltage performance. Utilizing an optimized ptype implant in the trench bottom can maintain a high
blocking voltage. To obtain a low on-resistance, an
appropriate distance in the n drift between the p-well
and the p-type implant at trench bottom, should be used
to avoid current crowding at the trench corner.

1085

Acknowledgements
The authors would like to acknowledge the nancial
assistance provided by the Establish Silicon Carbide
Application for Power Electronics in Europe (ESCAPEE) project (GRD1-2000-25337) for this work. The
authors would like to thank Dr. S. Evans for guidance
and advice with regard to the Academi2d simulation
software.

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