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Scan Insertion:
1).Explain scan insertion steps?
2).what are the basic things that needs to taken care for Scan Insertion?
3).what are the DRC Violations that u have faced during Scan Insertion and how did you fix those ?
4).what is test point Insertion? Can you tell and explain one TestPoint Insertion scenario?
5).Some Questions on design complexity like what was the gate and flops count of yours recent
project?
6).Explain Decompression logic?
7).what is sdc file and what does it contains?
8).what is the use of clock gaters in design?
9).Draw the internal diagram of clock gating cell?
10).what is use of latch in clock gating cell?
11).How glitches can be remove through latch?
12).Draw the muxed flip flop and explain?
13).Take three scan flop and stitch it and explain the scan operation?
14).How you will decide the number of scan chains for your core?
15).what is lockup latch and why we use it?
16).what are Manufactured defects?
17).what is clock latency?
18).will latency effect data shifting in scan chain?
19).consider two flop of .2sec and 0.3 sec latency how do you connect the flops in scan chain?
20).write the RTL coding for an asynchronous and a synchronous Flip-flop?
21).Implement a 2 by 1 Mux through gates?
22).How you will decide the compression ratio for the core?
23).what all information you will ask from designer for smooth scan insertion?
24).what all ctls you read while scan insertion?
25).Draw and explain the Structure of the compressor and decompressor circuit?
26).why we don't go for higher compression ratio like 90-100%?
27).How many scan clocks you had for your core?
28).which one is better having single or multiple scan clock?
29).what all things you need to take care while/before inserting on chip clock controller circuit?
30).In which path we insert the lockkup latch, data or clock path?
31).How you will resolve the combinational feedback loop issue in design if present?
32).why we don't connect the capture flop's clock to the lockup latch?
33).why we use flop trays in design?
34).what is the purpose of DFT?
35).why we need scan? or why we convert normal D flip flops to scan flops in design?
36).what work around you can do if you don't have scan equivalent for some flops in design while
scan insertion?
ATPG:
37).Did you worked on Coverage Analysis? How did you improved your Coverage?
38).what are the ATPG Untestable faults?
39).How much test coverage you got in your last project?
40).what are the input files required for scan insertion and ATPG and what all output files we get after
completing scan insertion and ATPG?
41).what is Stuck at fault?
42).How many faults sites are there for a 2 input AND Gate?
43).what is the difference between transition and path delay fault model?
44).what the SPF/test procedure file contains?
45).what are the different types of fault classes?
46).what is fault collapsing?
47).For a given fault coverage the number of patterns for TFT is more than the patterns generated for
Stuck-at-faults. Why so?
48).How the 2 pulses are generated for transition faults?