Chapter 7 PDF

ESE 570 COMBINATIONAL CMOS
LOGIC GATES AND CELLS

STATIC AND DYNAMIC SPECIFICATIONS
Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13
pMOS Net = dual (nMOS Net)
Two-Input NOR Gate

AB = AB
(A . B)
F (VF)
A (VA)
F (VF)
A (VA)
B (VB)
X (VX)
B (VB)
(A + B)
For Complimentary CMOS: Pull-up Net = dual (Pull-down Net)
SWITCH-RC TRANSISTOR MODLELS

nMOS
(W/L)n
Cg
(W/L)n = n (W/L)un
Cd
Assume: bulk at GND

Rn = Run
where typically n = 1
ON/
OFF
I Dn
1
W
G n= =
= KP n
R n V DS
L n
(W/L)p = p (W/L)up
Cd
For an INV p = n/p
Cd = Cdbn = Csbn
VDD
pMOS
pCd
Assume: bulk at VDD
KP n =n C ox
VDD
(W/L)p
pCg
I Dn
1
W
G p= =
=KP p
R p V DS
L p
KP p = p C ox
Rp = pRup
VDD
ON/
OFF
pCd
Cd = Cdbp = Csbp
4

nMOS
Assume: bulk at GND
(W/L)n
Cd
Rn
Cg
ON/
OFF
2-input
NOR
pulldown
Net
Cd
(W/L)n = n(W/L)unit
I Dn
1
W
G n= =
=KP n
R n V DS
L n
INV pull-down Net
RnEQV= Rn/2
or
GnEQV= 2Gn
ASSUME VTn = VT0n

for all nMOS
2-input
NAND
pulldown
Net
RnEQV = 2Rn
or
GnEQV = Gn/2
5

pMOS
Cd
Assume: bulk at VDD

VDD
(W/L)p
VDD
VDD
Cg
Rp
VDD
ON/
OFF
Where Wp = p Wunit
I Dn
1
W
G p= =
=KP p
R p V DS
L p
Cd
VDD
RpEQV = 2Rp
or
GpEQV = Gp/2
ASSUME VTp = VT0p

for all pMOS
INV pull-up Net

VDD
2-input
NOR
pull-up
Net
VDD
VDD
2-input
NAND
pull-up
Net
VDD
RpEQV = Rp/2
or
GpEQV = 2Gp
6

2-input
NOR
pulldown
Net
2-input
NAND
pulldown
Net
(W/L)nEQV = 2 (W/L)n
RnEQV= Rn/2
or
GnEQV= 2Gn
RnEQV= Rn/2
(W/L)nEQV = 1/2 (W/L)n
RnEQV = 2Rn
or
GnEQV = Gn/2
RnEQV= 2Rn

VDD
2-input
NOR
pull-up
Net
VDD
(W/L)pEQV = 1/2 (W/L)p
VDD
VDD
RpEQV = 2Rp
or
GpEQV = Gp/2
VDD
2-input
NAND
pull-up
Net
RpEQV = 2Rp
VDD
(W/L)pEQV = 2 (W/L)p
VDD
VDD
RpEQV = Rp/2
or
GpEQV = 2Gp
RpEQV = Rp/2

VDD
2-input
NOR
Nets
VDD
RnEQV= Rn/2
RpEQV = 2Rp
VDD
2-input
NAND
Nets
RnEQV= 2Rn
VDD
RpEQV = Rp/2
= ID1 + ID2
0
0
VDD
VDD
0
VDD
0
VDD
VDD
VOL1
VOL1
VOL2 < VOL1
n
n
where for NR2: m = 0, 1 or 2

10
= ID1 + ID2
KPn
KPn
00
VDD
VDD
VDD
0 0
VDD
VOL1
VOL1
VOL2 < VOL1
11
Rn
Rn
KPn
KPn
Gn = 1/Rn
I Di
ID
1
W
W
G i= =
=
= KP i =KP
R i V DS V DS
L i
L
VOL for INV:
2
1
1
2
V OL =V DD V T0n k R V DD V T0n k R
V DD
k
R
nEQV
L
nEQV
L
nEQV
L
k nEQV R L
k nEQV R L
k nEQV R L
G(R)EQV-NR2
0
0
INV
Equivalent to
NR2
Gn(Rn)
Gn(Rn)
2Gn(Rn/2)
knEQV = mkn = KPn m(W/L) = KPn (W/L)EQV where m = 1 or 2

(Pattern
Dependent)
12
Cload-NR2 = Cn-int1 + Cn-int2 + Cext = 2Cd + Cext

Cload-INV = Cd + Cext
Cg
Cn-int2
Cg
Cd
Cext
Cd
Cn-int1
Cwire
Cg
Cd
Cg
nCg
Cd
n = fanout to
R-load INVs
13
INV
Equivalent to
NR2
Cload-NR2
kn -> knEQV = mkn
Cload-NR2
(input pattern dependent)
14
VA = VDD, VB = 0 or VA = 0, VB = VDD
2V DD V T0n
2V DDV T0n
k
R
k nEQV R L =
=k n R L=
nEQV L
2
2
2V DDV T0nV OL NR2 V OLNR2
2V DDV T0n V OL INV V OL INV
VA VDD, VB = 0 or VA = 0, VB VDD
0 V set to 0 V.
0->VDD0 V and the other input
one input switching
DD
C load INV
2 V T0n
4V DDV T0n
PHL INV =
[
ln
1]
k n V DDV T0n V DD V T0n
V DDV OL INV
= Cdbn ++ C2C
Cload-NR2 = 2Cdbn + Cext
CCload-NR2
load-INV= 2 C
ext + C + C
gd
db
int
gb
(VOL-NR2 = VOL-INV)
kn -> knEQV
(knEQV = kn for
1,) 2)
for Cases
max PHL
15
k-INPUT NOR (NRk)

(W/L)1 = (W/L)2 ... = (W/L)k = (W/L)
R EQV NRk =
1
R n where 0 m k
m
(W/L)k
where for NRk: 0 m k

16
R EQV NRk =
Vi = 0
VOL
KPn
IL
Rn
=
1
m
G = 1/Rn
R nin
KPn
Rn
Rn
Rn
Vi = VDD
INV
Equivalent to
NRn
W
Gni =mG
n
W
W
k
=
=m
EQV
L EQV m ON L m
L
where for NRk: 0 m k

input pattern
dependent
17
0 DD
V , Vi = 0 for all i j
1. Design to set max VOL to VOL spec., i.e. Vj = V
Set (W/L)j = (W/L) = (W/L)EQV
2VRDDV T0n
2V DD V T0n
k
k nEQV R L =
=k n R L=
nEQV L
2
2
2V DD V T0n V OL NRk V OL NRk
2V DDV T0n V OL INV V OL INV
2. Design to set for knEQV at min value, i.e. Vj VDD, V0i = 0 for all i j
L H and all other inputs set to 0 V.0.
C load INV
2 V T0n
4V DDV T0n
PHL INV =
[
ln
1]
k n V DDV T0n V DD V T0n
V DDV OL INV
-> C
C->
n Cd gd+ +CnextCdb + Cint + Cgb
CCload-INV
->
= kC
load-INV
load-NRn
load-NRk
k
PHL-NRk
Cload-INV Cload-NRk
VOL-INV VOL-NRk
k k->
k knEQV
n
n
nEQV
(VOL-NRk = VOL-INV worst case)

(knEQV = kn for max PHL)
18
VT1 VT0n
0
0
VDD
VDD
0
VDD
0
VDD
VDD
VDD
VDD
VOL-ND2
Vout = VOH = VDD

19
Rn = 1/Gn
ASSUMPTION:
VT = VT0n
Rn = 1/Gn
Gn
1
R EQV ND2=2R n G EQV ND2=
=
2R n 2 =>
knEQV
W
1 W
=
L EQV 2 L
2V DD V T0n
1
k nEQV R L = k n R L =
2
2
2V DD V T0n V OLND2 V OL ND2
For INV
Equivalent to
ND2
20
Cdb1 = Cdb2 = Cd
In Pull-up Cload-ND2 and PLH-ND2

are input-pattern dependent
Csb1 = Csb2 = Cd
##
V = VDD
OH
CASE1: A
VB = VDD
-> 0 @t = 0 VA #
OH
CASE2:
VA = VDD
-> 0 @t = 0
OH
VB = VDD
VB
OH
Vout
#C
#n-int
Vx
#
sb2
#
S
D
Cwire
2Cn-int
##
##
Cext
nCg
Vout = low -> high

Vx Vout = low -> high
Vx = low .0
CASE1:
Cload = Cgd1 + Cgs1 + Cdb1 + Csb1 + Cdb2 + Cgd2 + Cint + (worst
Cgb (worst
casecase)
max value)
Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext
aaCdb1 + Csb1 + Cdb2 + Cint + Cgb (worst case)

CASE2:
>
Cload-ND2 Cn-int + Cext
PLH_ND2
PLH_ND2
Cn-int = Cd
21
In Pull-down Cload-ND2 and PHL-ND2

PHL
are input-pattern dependent
CASE1:
VA = VDD
Cdb1 = Cdb2 = Cd
Csb1 = Csb2 = Cd
Cext
Cn-int
DD
VB = 0 -> VDD@t = 0 VA
nCg
CASE2: VA = 0 -> VDD@t = 0
VB = VDD
DD
Vout
VB
2Cn-int
VB
Vout = high -> low
Vx Vout = high -> low

Vx = low .0
CASE1:
Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext

CASE2:
Cload-ND2 Cn-int + Cext
(worst case)
case max value)
PHL_ND2 > PHL_ND2
Cn-int = Cdbn = Csbn

22
INV
Equivalent to
ND2
R EQVND2=2R n n
n
knEQV
W
1 W
=
L EQV 2 L
k n R L=
2V DDV T0n
2
2V DD V T0n V OL INV V OL INV

2V DDV T0n
kn
k nEQVkRnEQV
= RL
L = R La
2
2V DDV T0n V OL NR2V OL NR2 2
k n=2 k nEQV
C load ND2
2 V T0n
4 V DD V T0n
PHL ND2
[
ln
1]
k nEQV
V DD V T0n V DD V T0n
V DD V OL ND2
knEQV
Cload-ND2 3Cd + Cext
(worst case)
23
k
k
k-1
VOH &
k
1
R EQV NDk =kR n G EQV NDk = G n
k
ASSUMPTION:
VT1 = VT2 = ... = VTk = VT0n
W
1 W
=
L EQV nk L
k
24
Cn-int C
load-NDk
Cext
Vx1
Vx1
C2
2C
n-int
Vx2
Vxk-1
Vxk-1
<=>
k
2C
Cnn-int
Worst-case H-L: V1 = V2 ... = Vk-1 = VDD and Vk = 0 -> VDD @t= 0 => Vout = VDD -> 0
and Vx1V=
high
Vxk-1
=high
low;->...low
; Vxn-1 = high -> low
Vx2-> low;
V
V =->high
x2
x1
out
Worst-case L-H: V1 = V2 ... = Vk-1 = VDD and Vk = VDD -> 0 @t= 0 => Vout = 0 -> VDD
and Vx1V=x1low
high;
= low
; Vxn-1 = low -> high
V->
V
Vx2xk-1
Vout->= high;
low ->...high
x2
Cload-NDk Cn-int1 + 2 (k - 1)Cn-int + Cext = (2k -1) Cn-int + Cext (worst case max value)
Cn-int = Cd
25
W
1 W
=
L EQV nk L
k
k
2V DDV T0n
kn
k nEQV R L =
= RL
2
2V DD V T0n V OL NRk V OL NRk k
C load NDk
2 V T0n
4V DD V T0n
PHL NDk knEQV
[
ln
1]
k nEQV V DD V T0n V DD V T0n
V DD V OL NDk
Cload-NDk (2k -1) Cn-int + Cext

Cn-int = Cd
(worst case max value)
26
VT = VT0p
V1 V2
1 1
1 0
0 1
0 0
approximation:
VT = VT0p
Vout
0
0
0
1
VT VT0p
VT = VT0n
VT = VT0n
27

VDD
2-input
NOR
Nets
VDD
RnEQV= Rn/2
RpEQV = 2Rp
VDD
2-input
NAND
Nets
RnEQV= 2Rn
VDD
RpEQV = Rp/2
28
CMOS NR2
Vout
VDD
simultaneous
switching
3 VTC Cases
V1 = 0 V; V2 = 0 VDD @ t = 0
V1 = 0 VDD @ t = 0; V2 = 0
V1 and V2 = 0 VDD @ t = 0 simultaneously
only one
input
switches
Vin
29
R pEQV NR2=2 R p
1
G pEQV NR2 = G p
2
kp
k pEQV =k p / 2
kp
k nEQV =2 k n
kn
kn
G nEQV NR2=2 G n
1
R nEQV NR2 = R n
2
k nEQV =k pEQV or k pEQV / k nEQV =1 & V T0n=V T0p V th EQINV =V DD /2

V th NR2=V DD / 2 k nEQV =k pEQV k p =4 k n
k p=2 k pEQV
k n =1/2 k nEQV
30
2Cp-int
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Cd
Vx
Csb1p = Csb2p = Cd
Cd
Cd
Cp-int
2nCg
Cd
Cd
Cext
Cn-int
Cn-int
V1 = 0, V2 = VDD-> 0 @t=0 & Vx Vout = 0 -> VDD

Cload-NR2 2Cn-int + Cp-int + 2Cp-int + Cext = 2Cd + 3Cd + Cext
(worst case)
WORST CASE for PULL-DWN => V1 = 0, V2 = 0 ->VDD@t=0 & Vx Vout=VDD-> 0

Cload-NR2 2Cn-int + Cp-int + 2Cp-int + Cext = 2Cd + 3Cd + Cext
(worst case)
KEEP COMPLEMETARY CMOS
NRk: Cload-NRk kCd + (2k - 1)Cd + Cext
GATES SIMPLE (i.e. limit k)
31
V th NR2=V DD /2 k pEQV =k nEQV k p =4 k n
min
size
k p=2 k pEQV
1
k n = k nEQV
m
C load NR2
2 V T0n
4V DD V T0n
PHL NR2
[
ln
1]
m k n V DD V T0n V DD V T0n
V DDkp = n kpEQV m = 1 or 2
2
case m = 1)
Vth(NRn)
=
V
/2
=>
k
=
n
k
2
V
4V DD k
V= T0p
(worst
C load NR2DD
(1/m)
k
p T0pn
n
PLH NR2
[
ln
1]nEQV
V DD
k p /2V DD V T0p V DD V T0p
p
32
NRk
Rn
R nEQV NRk =
m
R pEQV NRk =m R p
k
V th NR2=V DD /2 k p =k 2 k n
W
2
2 n W
k p =k k n =k

L p
p L n
PHL-NRk
PLH-NRk
k p=k k pEqv
k
k
k
p
PLH-NRk
PHL-NRk
33
1
R pEQV ND2 = R p
2
kp
kp
k pEQV =2 k p
kn
kn
k nEQV =k pEQV & V T0n=V T0p V th EQINV =V DD /2

V th ND2=V DD / 2 k nEQV =k pEQV k n =4 k p
k nEQV =k n /2
R nEQV ND2=2 R n
k p =1/2 k pEQV
k n =2 k nEQV
34
Cdbp1 = Cdbp2 = Cdbp
Cp-int
Cdbn1 = Cdbn2 = Cdbn
Cp-int
Csb1n = Csb2n = Csbn = Cdbn

nCgb
Cn-int
V1
Vx
V2
Cext
2Cn-int
V1 = VDD, V2 = VDD-> 0 @t=0 & Vx Vout= 0 ->VDD

Cload-ND2 Cn-in + 2Cn-int + 2Cp-int + Cext = 3Cn-int + 2Cp-int + Cext (worst case)
WORST CASE for PULL-DOWN => V1 =VDD, V2 = 0 ->VDD @t=0 & Vx Vout=VDD-> 0
Cload-ND2 Cn-in + 2Cn-int + 2Cp-int + Cext = 3Cn-int + 2Cp-int + Cext (worst case)
NDk: Cload-NRn (2k - 1)Cn-int + kCp-int + Cext

(worst case)
35
kp = 1/m kpEQV
Vth(ND2) = VDD/2 => knEQV = kpEQV => kn = 4kp
kn = 2 knEQV
C load ND2
2 V T0n
4V DD V T0n
PHL ND2
[
ln
1]
k n /2 V DD V T0n V DD V T0n
V DD
2V T0p min 4V DD V T0p
C load ND2
PLH ND2
[
ln
1] m = 1 or 2
size
V DD
m k p V DD V T0p V DD V T0p
(worst case m = 1)
Vth(NDn) = VDD/2 => kn = n2kp
kp = 1/m kpEQV
kn = n knEQV
C load NDn
2 V T0n
4 V DD V T0n
PHL NDn
[
ln
1]
k n / nV DD V T0n V DD V T0n
V DD
2V T0p
4V DD V T0p
C load NDn
PLH NDn
[
ln
1] 1 m n
V DD
m k p V DD V T0p V DD V T0p
(worst case m = 1)
36
NDk
NDk:
k2
k2
k2
PHL-NDk
PLH-NDk
Cload-NDk
Cload-NDk
37
Delay Macromodels
VDD
ND3
Cext = 0
VDD
CCL = =0.5
0.5pFpF
ext
ND3
VDD
CCLext= =1 1.0
pF pF
PLH C ext =int , LH c ext ext , LH

PHL C ext =int , HL c extext , HL
ND3
C ext
c ext =
1 pF
Cext = 0
PLH =0.26 nscext2.12 ns

PHL=0.42 nsc ext3.88 ns
Cext = 0.5 pF Cext = 1.0 pF
0.26
cext
int , XY = PXY c ext =0
0.42
(ns)
(ns)
Simulation Data
38
Eight(8) Input NAND and NOR Gates
LH ?
HL ?
LH ?
HL ?
cext
cext
C ext
c ext =
1 pF
39
CCext = 0 -> 1 pF.

L
cext
cext
Cext = 0.5 pF
C ext
c ext =
1 pF
cext
40
41
42
NOR
NAND
43
R A R DR E =R A
or
G AG DG E =
R BR C
RD RE
R D R E
IL
or
G BG C =
G A G D G E
G A G DG E
GB GC
G BG C
G1 < G2 < G3 < G4
G EQV =G AG D D E G BG C
W
W
W
W
W
[ ]
L A L D
L E
L B L C
W
=
L EQV
W
W
W
W
W

L A
L D
L E
L B
L C
44
EQV Inverter Case G4 where A = B = C = D = E = 1

G A G DG E
G AG DG E =
G AG DG E
G B GC
G BG C =
G B GC
W
W
W
W
W
[ ]
L A L D
L E
L B L C
W
=
L EQV W
W
W
W
W

L A
L D
L E
L B
L C
Let
W
W
W
W
W
W
= = = = =
L n
L A
L B
L C
L D
L E
G EQV =G AG D D E G BG C
W
W
W
W
W
2 W
1 W
7 W
= 2 = =
L EQV L n
L n L n L n 3 L n 2 L n 6 L n
45
W
W
1 W
=
=
L EQV
L EQV ND2 2 L
46
Gate Layout in Standard Cell Style
47
D S
GND
48
OPTIMIZED
49
Arbitrary Stick Layout
diffusion
breaks
d
d
d
d
i.e. n, p Euler paths with

identical sequences of
inputs
50
Y
Y
51
Is A-D-E-C-B a common Euler path?
X
X
YES for
- for
pMOS net
NO - for
nMOS net;
C-B not on
path
52
Arbitrary Stick Layout
Optimized Stick Layout
53
3. If no common n- and p- Euler paths are found in step 2,

partition the gate n- and p- graphs into the minimum
number of sub-graphs that will result in separate common
n- and p- Euler paths.
54
AB AB= AB AB= AB AB
AB AB= AA ABABB B=AB AB
55
AND
OR
INV
AOI = OAI
AOI
SUM of Products => OR of ANDs
AOI Implements logic function F
in the order AND, OR, NOT (Invert)
56
OR
AND
OAI = AOI
INV
F
F
PRODUCT of SUMS => AND of ORs
OAI
OAI Implements logic function F in

the order OR, AND, NOT (Invert)
57
ADVANTAGES?
DISADVANTAGES?
58
59
VDSp = - VDD + Vout
Note
at t = 0-: Vin = 0, Vout = 0
at t = 0+: Vin = 0 -> VDD
- VTp
60
kp (- VDD - VTp)2
kp [2(- VDD - Vtp) (Vout VDD) - (Vout VDD)2]

kp [2(- VDD - Vtp) - (Vout VDD)]
kp [2(- VDD - Vtp) - (Vout VDD)]

61
62
63
64
INTRODUCTION TO PASS TRANSISTOR LOGIC (PTL)

In conventional CMOS logic, inputs are applied to the transistor
gate terminals. In PTL inputs are applied to the transistor
source/drain terminals.
These circuits act as net of switches using either using nMOS
transistors or nMOS/pMOS transmission gates.
In PTL using transmission gates, both nMOS and pMOS are
equally sized, Wp = Wn.
Generally PTL leads to reduced transistor count and smaller node
parasitic capacitances resulting in decreased die area, delays
and power dissipation.
65
PASS TRANSISTOR LOGIC (PTL)
66
PTL USING TRANSMISSION GATES

Z = As Bs
Z
Z
Note that s and s

must be available
simultaneously.
CMOS Transmission Gate (TG) implementation of XOR
F = BA + BA = AB + AB
It is crucial that a conducting TG
network always be provided between
the output and one of the inputs.
67

CMOS TG-PTL Implementation of Boolean Function F
B
V DD
B
C
A
F =BCBACA
F = AB AC ABC
68
TG-PTL BOOLEAN FUNCTION UNIT

F1
F 1 AB
F2
F 2 AB
F 3
AB
C par
F 4
A
B
F3
F4
(TG)
AND(A, B)
BF 4AB
F 3A
Z= F 1AB F 2AB
69
(TG)
NOR (A, B)
= AB
= AB
Z= F 4AB
= AB OR (A, B)
Z
XOR (A, B)
F 3AB
Z= F 2AB
B
A
.= AB
AND (A, B)
Z= F 1AB= AB
= AB NAND (A, B)
Z
70

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ESE 570 COMBINATIONAL CMOS

LOGIC GATES AND CELLS

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

pMOS Net = dual (nMOS Net)

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

Two-Input NOR Gate

For Complimentary CMOS: Pull-up Net = dual (Pull-down Net)

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

SWITCH-RC TRANSISTOR MODLELS

Assume: bulk at GND

For an INV p = n/p

Assume: bulk at VDD

SWITCH-RC TRANSISTOR MODLELS

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

ASSUME VTn = VT0n

SWITCH-RC TRANSISTOR MODLELS

Assume: bulk at VDD

ASSUME VTp = VT0p

INV pull-up Net

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

SWITCH-RC TRANSISTOR MODLELS

(W/L)nEQV = 1/2 (W/L)n

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

SWITCH-RC TRANSISTOR MODLELS

(W/L)pEQV = 1/2 (W/L)p

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

SWITCH-RC TRANSISTOR MODLELS

(W/L)pEQV = 1/2 (W/L)p

(W/L)nEQV = 1/2 (W/L)n

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

where for NR2: m = 0, 1 or 2

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

knEQV = mkn = KPn m(W/L) = KPn (W/L)EQV where m = 1 or 2

Cload-NR2 = Cn-int1 + Cn-int2 + Cext = 2Cd + Cext

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

kn -> knEQV = mkn

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

(input pattern dependent)

k-INPUT NOR (NRk)

where for NRk: 0 m k

where for NRk: 0 m k

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

(VOL-NRk = VOL-INV worst case)

Vout = VOH = VDD

In Pull-up Cload-ND2 and PLH-ND2

Vout = low -> high

Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext

aaCdb1 + Csb1 + Cdb2 + Cint + Cgb (worst case)

Cload-ND2 Cn-int + Cext

In Pull-down Cload-ND2 and PHL-ND2

CASE2: VA = 0 -> VDD@t = 0

Vout = high -> low

Vx Vout = high -> low

Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext

Cload-ND2 Cn-int + Cext

PHL_ND2 > PHL_ND2

Cn-int = Cdbn = Csbn

2V DD V T0n V OL INV V OL INV

Cload-ND2 3Cd + Cext

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

Kenneth R. Laker, University of Pennsylvania, updated 25 Feb13

Cload-NDk (2k -1) Cn-int + Cext

(worst case max value)