Origin of transient Vth shift after erase and its impact on 2D/3D structure

charge trap Flash memory cell operations

Jong Kyung Park1, Dong-Il Moon1, Yang-Kyu Choi1, Seok-Hee Lee1, Ki-Hong Lee2, Seung Ho Pyi2,
1*
and Byung Jin Cho
1

Dept. of Electrical Engineering, KAIST, Daejeon 305-701, Korea

2
SK Hynix Semiconductor Inc., Gyeonggi-do, Korea
*Phone: +82-42-350-3485, Fax: +82-42-350-8565, Email: bjcho@kaist.edu

Results and Discussions

Abstract

A. Mechanism of transient Vth shift after erase

The mechanism of transient Vth shift after erase is

studied in detail. It is concluded that the main mechanism
is hole redistribution in the charge trap layer. A new erase
scheme is proposed and demonstrated to reduce transient Vth
shift. The impact of transient Vth shift on the 3D charge trap
device is investigated, as well.

Fig. 5 shows the transient Vth shift after erase. Vth shift
toward negative voltage is clearly shown; this is completely
opposite to reports that show a positive Vth shift after erase
with a small erase voltage [1,3]. Figs. 6-9 provide strong
evidences that the transient Vth shift is not due to dielectric
relaxation. The dielectric relaxation is the result of slow
dipole formation in high-k dielectrics, which leads to a
momentary delay until having its original k-value under the
electric field. Usually, therefore, the higher the k value is,
the larger the dielectric relaxation is. However, a CTF
device with a cubic structured HfLaO (k ~ 38) blocking
layer [4] shows a smaller shift in Id compared to that of a
device with an Al2O3 blocking layer. Fig. 7 shows that the k
value of Al2O3 increases with temperature [5]; however, the
transient Vth shift value decreases with temperature. Fig. 8
shows that devices before and after P/E cycling generate
different transient Vth shifts; however, the k-value of
dielectrics is not related to the P/E cycling. Fig. 9 shows
that the Vth in a SONOS-type device with no high-k material
in the gate stack also decreases after erase. All these
experimental results run opposite to expectation based on
dielectric relaxation effect, and thus confirm that dielectric
relaxation is not the cause of transient Vth shift after erase
operation.
Then, the only possible cause is the
redistribution of charge in the gate stack.
Fig. 10 provides a band diagram of the erase state; all
possible scenarios of charge redistribution by internal
electric field are marked. Mechanisms d~g and i in Fig.
10 cause the increase of Vth; therefore, these cannot be the
reason. Mechanisms c and h are possible, but the effect
of c is contradict to the results in Fig. 11. If mechanism c
is the main cause of transient Vth shift, the amount of Vth
shift will increase with tunnel oxide thickness due to a
larger amount of trapped electrons during erase. Therefore,
mechanism h is the most possible cause. In mechanism h,
hole movement is dominant over electron movement
because the quantity of electrons in the charge trap layer
after erase is small. Therefore, we can conclude that the
hole redistribution in the trap layer may be the main cause
of the transient decrease of Vth after erase. The other

Introduction
Recently, transient Vth shift in charge trap Flash (CTF)
memory devices after erase operation has become an
important issue [1,3]. Since Vth after erase does not settle to
the final target Vth immediately (Fig. 1), there will be an
incorrect estimation of the error bit percentage in the erase
verification step (Fig. 2), depending on the time interval
between the erase and read operations. Waiting until the
final settlement of Vth significantly increases the total erase
time. This Vth transient phenomenon after erase has been
attributed to the dielectric relaxation effect in the high-k
layer [1] or to charge trapping/detrapping [2], or to mobile
charges in the Al2O3 layers [3]. However, the mechanism is
still under dispute.
In this work, we present new
experimental findings through detailed and systematic study
of this issue; we identify the true mechanism behind the
phenomenon and propose a new method to mitigate the
problem.
Experimental
Various CTF memory cells with/without high-k
dielectrics are fabricated. Gate-all-around (GAA) SONOS
device is also prepared for studying the impact on 3-D flash
memory. Fig. 3 shows the Vth measurement scheme in our
experiment. The transient change of Id is monitored at a
given read voltage and then converted to the corresponding
Vth value using Id-Vg characteristics. The bias condition and
typical Id during this measurement are shown in Fig. 4. The
erase voltage is set to be large enough so that the amount of
Vth change is similar to that in the real operating situation,
which is the main difference between the results in our
report and those from previous reports [1,3].

978-1-4673-4871-3/12/$31.00 2012 IEEE

2.4.1

IEDM12-25

device with small nanowire diameter has advantage in fast

erase operation.

suggested cause in a previous report [3], as-grown mobile

charge in Al2O3, is also ruled out because it cannot explain
the tunnel oxide thickness dependency (Fig. 11), trap layer
material dependency (Fig. 13), or transient Vth shift in a
SONOS-type device (Figs. 9 and 17). Fig. 11 shows that
the thinner tunnel oxide has a larger transient Vth shift. This
can be evidence of a hole redistribution mechanism. The
thinner tunnel oxide allows a larger amount of hole
injection to the nitride charge trap layer during the erase
(Fig. 12), resulting in a larger amount of transient Vth shift.
When the Si3N4 charge trap layer is replaced with the HfO2
layer, the transient Id and Vth shifts are reduced and saturated
earlier (Fig. 13); this reduction results from the fast
redistribution of holes along the grain boundaries of the
crystallized HfO2 layer [6]. According to this, early
saturation of Vth shift at high temperature in Fig. 7 can be
also understood from enhanced hole redistribution by the
effect of elevated temperature.

Conclusion
The transient Vth shift after erase is found to be due to
hole distribution in the charge trap layer. The proposed new
erase scheme, employed to make fast redistribution of holes,
reduces the transient Vth shift. Transient Vth shift is also
important in 3D CTF devices and can be reduced by the
proper scaling of the 3D device.
Acknowledgements
This work was financially supported by SK Hynix
Semiconductor Inc. The authors would like to thank
National Nanofab Center for device fabrication support.
The authors would also like to thank Jusung Engineering
Inc. and UP Chemical for ALD equipment and precursor
supports, respectively.

B. Proposed erase scheme to expedite the erase process

Based on all these observations, we propose a new erase
scheme (Fig. 14) that can speed up the erase process. Prior
to applying a read voltage, a small positive gate pulse is
applied immediately after the main erase pulse. This
subsequent small positive pulse helps fast redistribution of
holes in the charge trap layer and thus greatly reduces the
Vth transition period after erase. Small positive pulse
marginally increases erase pulse time, but greatly shortens
Vth transition time. Then, the total erase time is greatly
shortened. However, the compensating positive voltage
should be carefully decided at a level to avoid the soft
programming disturbance. The results shown in Fig. 15
verify that the proposed erase scheme works and is very
effective to expedite the erase process.

References
[1] J. Fujiki, N. Yasuda, R. Fujitsuka, W. Sakamoto, and K. Muraoka,
Successful suppression of dielectric relaxation inherent to high-k NAND
from both architecture and material points of view, IEDM Tech. Dig., pp.
16.7.1-16.7.3., 2009.
[2] C. P. Chen, H. T. Lue, C. C. Hsieh, K. P. Chang, K. Y. Hsieh, and C. Y.
Lu, Study of fast initial charge loss and it's impact on the programmed
states Vt distribution of charge-trapping NAND flash, IEDM Tech. Dig.,
pp. 5.6.1-5.6.4., 2010.
[3] B. J. Tang, W. D. Zhang, J. F. Zhang, G. Van Den Bosch, B.
Govoreanu, and J. Van Houdt, Abnormal VTH/VFB shift caused by asgrown mobile charges in Al2O3 and its impacts on Flash memory cell
operations, IEDM Tech. Dig., pp. 9.6.1-9.6.4.,2011.
[4] W. He, L. Zhang, D. S. H. Chan, and B. J. Cho, Cubic-structured HfO2
with optimized doping of lanthanum for higher dielectric constant, IEEE
Electron Device Lett., vol. 30, pp. 623-625, 2009.
[5] A. Padovani, L. Larcher, D. Heh, G. Bersuker, V. Della Marca, and P.
Pavan, Temperature effects on metal-alumina-nitride-oxide-silicon
memory operations, Appl. Phys. Lett., vol. 96, no. 223505, 2010.
[6] Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, Over-erase
phenomenon in SONOS-type flash memory and its minimization using a
hafnium oxide charge storage layer, IEEE Trans. Electron Devices, vol.
51, pp. 1143-1147, 2004.
[7] D. I. Moon, S. J. Choi, C. J. Kim, J. Y. Kim, J. S. Lee, J. S. Oh, G. S.
Lee, Y. C. Park, D. W. Hong, D. W. Lee, Y. S. Kim, J. W. Kim, J. W. Han,
and Y. K. Choi, Ultimately scaled 20nm unified-RAM, IEDM Tech.
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[8] Z. Huo, J. Yang, S. Lim, S. Baik, J. Lee, J. Han, I. S. Yeo, U. I. Chung,
L. T. Moon, and B. I. Ryu, Band engineered charge trap layer for highly
reliable MLC flash memory, VLSI Symp. Tech. Dig., pp. 138-139, 2007.
[9] B. Kim, S. Baik, S. Kim, J. G. Lee, B. Koo, S. Choi, and J. T. Moon,
Characterization of threshold voltage instability after program in charge
trap flash memory, IRPS, pp. 284-287, 2009.
[10] M.-K. Jeong, S.-M. Joe, C.-S. Seo, K.-R. Han, E. Choi, S.-K. Park,
and J.-H. Lee, Analysis of Random Telegraph Noise and Low Frequency
Noise Properties in 3-D Stacked NAND Flash Memory with Tube-Type
Poly-Si Channel Structure, VLSI Symp. Tech. Dig., pp. 55-56, 2012.

C. Impact on 3D flash memory devices

We also investigated the impact of transient Vth shift on
3-D memory devices. The device has a GAA structure
fabricated using silicon nanowire and a SONOS gate stack
[7]. In the GAA-SONOS device, a smaller diameter of
silicon nanowire shows a better erase efficiency due to the
electric field concentration effect on the tunnel oxide (Fig.
16). However, the GAA-SONOS device also shows a
transient Vth shift after erase (Fig. 17). The amount of Vth
shift is related to the amount of memory window, and the
Vth shift in GAA-SONOS is well correlated to that in planar
TANOS devices (Fig. 18), implying the same mechanism.
It is worthwhile to note that the transient Vth shift can be
reduced by scaling of the channel length (LG) and the
diameter of the silicon nanowire (WNW) (Fig. 19) in GAASONOS, probably due to a compensation effect by charge
crowding and lateral charge spreading (Fig. 20). When the
diameter of nanowire goes below 6 nm, the tendency of Id
increase disappears. Therefore, the nanowire type 3D CTF

IEDM12-26

2.4.2

Vth

Erase verification
Actual Vth

Target Vth

-1

GND

Vg

10
Time ( sec )

10

Vth
Id

-2.0

-2.4 -2
10

Vd (0.05V)
t

10

(a)

25C
85C
150C

-2.0

(b)
-1

(b)

Si

SiO2 Si N
3 4

0.8

4.50

0.6

4.45

Fig. 8. The amount of

transient Vth shift of
TANOS device before and
after program/erase (P/E)
cycling.

TaN

Al2O3

D
Si

Fig. 10. (a) Band diagram after erase and possible scenarios of charge redistribution, and
(b) cross-sectional view of device structure and lateral hole distribution. 1 electron/ d
hole detrapping from tunnel oxide, e electron/ f hole detrapping from blocking layer,
g hole detrapping from trap layer to gate and substrate, h&i electron/hole
redistribution within charge trap layer in vertical and lateral directions. At the end of
erase pulse, hole concentration at the Si3N4/blocking oxide interface is high due to
charge centroid movement [8] and then holes are redistributed when the negative erase
pulse is removed. Mechanisms d~g and i cause the increase of Vth. Mechanisms c
and h are possible, but the effect of c is contradict to the results in Fig. 11. Therefore,
mechanism h is the most possible cause. In h, hole movement is dominant.

2.4.3

40.0n
30.0n
20.0n
10.0n

4.30

Fresh Cycled

SONOS(ONO 4/6/8nm)

4.35

0.2

4.40

0.4

TaN

-1

10
10
10
Time ( sec )

Fig. 6. Transient Id in TANOS device with

Al2O3 or Al2O3/HfLaO blocking oxides.
HfLaO have the k-value of ~38 [4]. The
device with Al2O3/HfLaO dual blocking
layer shows the smaller Id change which
means smaller transient Vth shift.
4.55

0.0

10 10 10 10
10
10
10
Frequency (Hz)
Time (sec)
Fig. 7. (a) Capacitance-frequency characteristics of TANOS device.
The increase in the accumulation capacitance at high temperature is
due to the increase of k-value of Al2O3 [5]. (b) Vth shift of TANOS
device. The shift is smaller at higher temperature. This is opposite
to the expectations based on dielectric relaxation mechanism for the
transient Vth shift.

(a)

-2

10

1.0

Vers= -20V (10ms)

-2.4 -2
10

200.0p

10
10
Time (sec)

-2.2
5

Vth shift @ 30sec (V)

25C
85C
150C

400.0p

Fig. 5. Converted Vth shift from Id change.

After erase pulse, the Vth shifts toward
negative.

-1.8
Vth (V)

Capacitance (F)

-1.6

-1

800.0p V =18V(100us)
pgm
600.0p Vers=-20V(10ms)

Vth (V)

t=0

Fig. 4. Measurement bias conditions and

transient Id of TANOS device (ONA
4.5/6/15nm). Erase pulse is 20 V for 10 msec
and the read voltage is 1 V.
29.0p
28.0p
27.0p
26.0p
25.0p
24.0p
23.0p
22.0p

1.0n

0.0

Vers(-20V, 10ms)
Vd

40.0

AlO(15nm),
EOT 13.7nm
AlO/HfLaO(6/30nm),
EOT 13.5nm

1.2n

20.0

-2.2

Vread (-1V)

GND

Vg
Fig. 3. Vth shift is calculated from the change
of Id, assuming that the Id-Vg curves are
parallel. Drain current (Id) is monitored at a
given read voltage.

60.0

-1.8
Vth(V)

Id (A)

Erase Pulse

10

Immediate
after erase

Vth
Fig. 2. Schematic drawing of Vth
distributions immediately after erase pulse
and after final settlement. Incorrect
estimation of the error bit percentage will
happen in the erase verification step,
depending on the time interval between the
erase and read operations.
-1.6
80.0

Vth shift after erase

After time
elapse

Verification
fail

Id (A)

80.0
60.0
40.0
20.0
0.0

Id Vth

distribution
after erase

Fig. 1. Illustration of transient Vth shift after

erase. Vth does not fully reach the target Vth
immediately after erase pulse and continues to
decrease for a while.

Vread

Id (A)

Vers

Id

Erase verification
Final
voltage
distribution
after erase
Immediate

Id (A)

Floating

Vth shift @ 30sec (V)

Vread

GND

Number of bits

Vg

0.0

Vers = -16V (100ms)

-2

10

-1

10
10
10
Time (sec)
Fig. 9. Transient Vth shift and Id change of
SONOS device. Transient Vth phenomenon
is also found in SONOS device with no highk material in the gate stack.

0.8
0.6
0.4
0.2
3.5

4.0
4.5
5.0
5.5
SiO2 thickness (nm)
Fig. 11. Amount of transient Vth shift of TANOS
devices as a function of tunnel oxide thickness. The
thinner tunnel oxide allows a larger amount of hole
injection to Si3N4 during the erase (Fig. 12). This data
also indicates that mechanism in Fig. 10 is not proper
to explain the negative Vth shift.

IEDM12-27

80.0

TaN

40.0
20.0

Si3N4 6nm
-1

-1.6

Proposed
erase method
Si

Vth (V)

Enhanced
redistribution

Vread
Vers

Si3N4

-20V, 10ms t

-2

Id (A)

SiNW
WNW

-0.5

LG=150nm
ONO

16
20
24
WNW (nm)
Fig. 16. Erased saturation voltage versus
nanowire diameter in GAA-SONOS device. Si
nanowire is fabricated onto the bulk-Si substrate
by deep reactive-ion-etching process [7]. A
smaller diameter of silicon nanowire shows a
better erase efficiency due to the electric field
concentration effect on the tunnel oxide.

12

(a)

Drain current (a.u.)

W/L = 23/50nm
W/L = 23/100nm
W/L = 23/150nm
Vpgm=11V(100us)
Vers=-12V(10ms)

-2

10

Vpgm=11V(100us)

Vers=-12V(10ms)
GAA-SONOS(ONO 3/6/8nm)

-1

Vers=-12V(10ms)
W/L = 24/150nm
-1

10

10
10
Time ( sec )
Fig. 17. Transient Id of GAA-SONOS device.
Vth reduction after erase is still found in
GAA-SONOS without high-k layer. Lower
Vth shift than the planar TANOS device is
due to the lower memory window effect in
Fig. 18.

Vers=-12V(10ms)

10

-2
GAA-SONOS

-4

-0.2
-0.4

-6
-8

TANOS
Vers (10ms)

-0.6

-14

-16
-18
-20
Erase voltage (V)
Fig. 18. Correlation of Vth window and Vth shift
after erase operation. This is attributed to the
difference in the amount of injected hole from
sub to Si3N4. The Vth shift in GAA-SONOS is
well correlated to that in planar TANOS devices,
implying the same mechanism for the transient
Vth shifts.

(b)

Vpgm=11V(100us)

WL direction
SiNW

BL direction

W/L = 6/150nm
W/L = 16/150nm
W/L = 23/150nm
-2

-1

Poly Gate

10
10
10
10
10
10
Time ( sec )
Time ( sec )
Fig. 19. Transient Id of GAA-SONOS devices with different (a) channel length (LG) and (b)
nanowire diameter (WNW). Transient Vth shift becomes smaller when the channel length and the
wire diameter are scaled. Sudden drain current fluctuation in GAA-SONOS may be due to
single electron effects [9] or random telegraph noise [10].

IEDM12-28

10

0.0

Drain current (a.u.)

-1.0

Vth= 0.24V

1.0n

-1

10
10
Time (sec)
Fig. 15. Comparison of Vth shifts of TANOS
device using conventional and proposed erase
scheme. When read voltage is -2V, some cells
using conventional method are identified as fail,
though they will be erased eventually to target
voltage. However, the issue is solved by using the
proposed erase method.
0.0

2.0n

Erased voltage (V)

Poly Gate

0.0

Conventional
Proposed

10

Al2O3

Fig. 14. . (a) Conventional erase and verification scheme in flash memory device and (b)
proposed erase and verification scheme in this work: prior to read voltage, a relatively small
gate pulse is applied immediately after the main erase pulse . The small positive pulse helps
the hole redistribution and thus greatly reduces Vth transition time after erase. Small pulse
marginally increases erase pulse time, but greatly shortens Vth transition time. Then, the total
erase time is greatly shortened.

0.5

Vread

-2.0

-2.4

SiO2

Vth by erase (V)

-20V, 10ms

Verification pass

-2.2
TaN

Vers

Verification fail

-1.8

5V, 1ms
GND

-0.6

10

(b)

Vg

-0.4

-0.8 -2
0
1
-1
0
1
10
10
10
10
10
10
Time ( sec )
Time (sec)
Fig. 13. (a) Transient drain current and (b) Vth shift of TANOS and TAHOS devices. Si3N4 and
HfO2 are used as charge trap layer. The transient Id and Vth shifts are reduced and saturated earlier
at the device with HfO2 trap layer, which is caused by the fast redistribution of holes along the
grain boundaries of the crystallized HfO2 layer [6].
-2

Vread

GND

HfO2 6nm

(b)

-0.2

HfO2 6nm

10

Conventional
erase method

Si3N4 6nm

2.4.4

Vth after erase (V)

SiO2

Fig. 12. Band diagram during erase

operation. While electron is detrapped from
Si3N4, hole tunneling occurs through the
tunnel oxide. The thickness of the tunnel
oxide is a critical factor to determine the
amount of hole injection.

Vg

(a)

0.0

Si

(a)

Vers=-20V(10ms)

60.0
Id (A)

Al2O3

0.0

Vpgm=18V(100us)
Vth shift (V)

Si3N4

SiNW

SiNW

Fig. 20. . Illustration of scaling effect of

GAA-SONOS device. Hole redistribution
effect may be compensated by charge
crowding and by lateral charge spreading.