PROGRAMMABLE COMMUNICATION INTERFACE (8251)

Programmable communication interface is used for serial data transmission. It is an

Universal Synchronous/Asynchronous Receiver Transmitter (USART). It is compatible
with 8085, 8086, 8088 and 8748.
It is fabricated using N-channel silicon gate technology 8251 can be used to transmit/
Receive serial data.
It accepts data in the parallel format from the microprocessor and converts into serial
data for transmission. It also receives serial data and converts them into parallel data
and sends the data to the CPU. The following figures shows the schematic diagram of
8251.

Pin Diagram

C /D (Control/ Data) when it is low data is transmitted on data bus when

it is high control signals are transmits on the data bus.
RD (Read). When it is low CPU reads data from 8251.
WR (Write). When it is low CPU writes data into 8251.
DSR (Data Set Ready).
DTR (Data Terminal Ready).
RTS (Request to Send).
CTS (Clear to Send). A low or this pin enables 8251 to transmit (data)
serial data.
TXC (Transmitter Clock). It governs the rate of data transmission.
T E (Transmitter Empty). TXE goes high when 8251 has no characters
to transmit. It indicates the end of transmission.
T RDY (Transmitter Ready).
R RDY (Receiver Ready).
R D (Line for Recurring Data).
T D (Line for serial data transmission).
R C (Receiver Clock). It governs the rate at which the characters are
received.

Methods of Data Communication:

The data transmission between two points involves unidirectional or bi-directional
transmission of digital data. There are basically 3 modes of data transfer.
(a) Simplex (b) Half Duplex (c) Duplex.
In Simplex mode data is transmitted only in one direction over a single communication
channel. Example: a computer (CPU) may transmit data for a CRT display unit.
In Half Duplex mode, data transmission may take place on either direction, but only
one direction at a time.
In a Duplex mode data may be transferred between two transreceivers in both
directions simultaneously.

ARCHITECTURE AND SIGNAL DESCRIPTION OF 8251

The following figure shows the block diagram. The data buffer interfaces the internal
bus of the architecture with the system bus. The Read/write control logic controls the
operation of the peripheral depending up on the operation initiated by the CPU. This
unit also selects one of the two internal address these are control address and data
address at the behest of the C/ D signal.
The modem control unit handles the modem handshake signals to coordinate the
communication between the modem and the USART. The transmit control unit transmits
the data byte received by the data buffer from the CPU for further serial communication.
This decides the transmission rate which is controlled by the Tx C input frequency.

8251A Operating Modes:

8251A can be programmed to operate in its various modes using the mode control
words. A set of control words may be written in the internal register of 8251A to make
it operate in the desired mode.
Once the 8251A is programmed as, required, the T X RDY is raised high to signal the
CPU that 8251A is ready to receive data byte from it that is to be converted in to serial
format and transmitted. This automatically goes low when the CPU writes the data in
to 8251A.
In the receiver mode 8251A receives serial data byte from modern or IO device. After
receiving a entire data byte, R RDY signal is raised high to inform the CPU that
8251A has a character read for it. The R RDY , signal is automatically reset after the
CPU reads the received byte from 8251A.
The control words of 8251A are divided into two function type.
(1) Mode Instruction Control Word.
(2) Command Instruction Control Word.
Asynchronous Mode:
Mode instruction control word define the general operational characteristic of the 8251A.
After the internal (reset command) or external (reset input pin) reset, this must be written to
configure the 8251A as per the require operation once this has been written into 8251A,

SYNCH character or command instruction may be programmed further as per the

requirement. To change the mode of operation from synchronous to asynchronous or viceversa,
8251A has to be reset using master chip reset.

Asynchronous Mode (Transmission):

When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial
data bits, followed by optional parity bit and stop bits using the asynchronous mode instruction
control word format. This sequence is the transmitted using T X D output pin on the following
edge T X C. When no data character are sent by the CPU to 8251a the T X D output
remains high if a break has not been detected.

Asynchronous Mode (Receive):

A falling edge of R X D input line marks a start bit. At a baud rate of 16 X and 64 X, this
start bit is again checked at the center of the start bit pulse and if detected low it is a valid
start bit and the bit counter starts counting. The bit counter locates the data bits, parity bit and
stop bit. If parity error occurs, the parity error flag is set. If a low level is detected as a stop
bit, the framing error flag is set. The receiver require only one stop bit to mark end of the
data bit string regardless of the stop bit program at the transmitting end. The 8-bit character
is the loaded in to parallel IO buffer of 8251 A. R RDY pin is then realised high to indicate
to the CPU that a character is ready for it. If the previous character has not been read by the
CPU the new character replaces it, and the overrun flag is set indicating that the previous
character is lost.
Synchronous Mode (Transmission):
The T D output is high until the CPU sends a character to 8251, which usually is a
SYNC character. When CTS line goes low the first character is serially transmitted out. All
the characters are shifted out on the falling edges of TXC . Data is shifted out at the same
rate as TXC , over TXD output line. If the CPU buffer becomes empty, the SYNC character
or characters are inserted in the data stream over TXD output. The TX EMPTY pin is raised
high to indicate that 8251A is empty; and is transmitting SYNC character. The TX
EMPTY pin is reset, automatically when a data character is written to 8251 A by the CPU.

Synchronou
s Mode (Receiver):
In this mode character synchronization can be achieved, internally or externally. If this

mode is programmed, then ENTER HUNT command should be included in the 1st command
instruction word written in to the 8251A. The data on RXD pin is sampled on the rising edge
of the R C . The content of the Receiver buffer is compared with the 1st SYNC character
at every edge until it matches. It 8251 A is programmed for two SYNC character, the
subsequent received character is also checked. When both the characters match, the hunting
stops. The SYNDET pin is set high and is reset automatically by status read operation. If a
parity bit is programmed, the SYNDET signal will not go high until the middle of parity bit,
otherwise till the middle of the last data bit.