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DRAM(Dynamic Random Access Memory)Leakage

Path Analysis

Abstract
DRAM is one of the key products used for high-density data storage. Data retention
performance is key item of DRAM product yield, This paper present three possible
leakage current path that can downgrade data retention performance in IC process.
Keywords: DRAM,Leakage path,Junction leakage,GIDL,Subthreshold leakage

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Introduction

DRAM product can be fabricated in large volumes with given fabrication process. Process problems
result in failing memory cells. And yield Limitation is the key point for DRAM product mass
production profit. The control of the retention time is the key issue for realizing high density DRAM
because the refresh time doubles with each successive generation [1] The retention time can be
defined as the duration until the stored signal can be read out. There are several leakage current paths,
by which the stored charge flowed out from the storage capacitor.
Fig.1 shows schematic of a 0.20 um Stack type CUB (Capacitor Under Bit line)DRAM device, Cell
Capacitors top and bottom plates are poly silicon material, Nitride-Oxide structure is for capacitor
dielectric.Rogered poly was deposited on bottom poly silicon to increase the area of plates which can
enlarge cell capacitance to store more charge. Tungsten(W) was used as bit line and bit line contact to
charge sense amplifier. When positive voltage is applied on poly gate (Vpp,usually 3.1~3.3V),cell
transistor will be turned on ,charges stored in cell capacitor flow out ,this can cause the voltage on bit
line have a drop or jump change, sense amplifier will catch this change and judge the capacitor stored
information is one or zerologic.Automatically ,when transistor is turned on, charges in capacitor
will be refreshed(recharged). During the period, charge will leak through some paths, we will
investigate age e three kinds of leakage current path with example of this stacked type DRAM.
Here are major possible leakage path as shown in Fig.1:
(1) Reverse Junction leakage current from the storage node
(2) Gate Induced drain leakage (GIDL) current
(3) Subthreshold leakage current of NMOS transistor

Bitline

Bitline Contact

Capacitor

N-

(3)
(2)

N-

(1)

P-Sub
Fig.1 Schematic of stack type DRAM device

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Leakage current Paths analysis

2.1 Junction leakage

The fabrication process of node p-n junction of DRAM device is as follows.Firstly,well formation
steps: Boron was implanted in order to form the p-well. The acceleration energy was
180Kev.Followed by anti punch through implant, Boron was implant with 80Kev acceleration energy.
The implantation dose was changed in order to vary the boron concentration of the p-well. MeV
implantation can be used to implant a minority carrier diffusion barrier between the ends of the
junction, which functions in a similar manner to a retrograde well used to improve data retention time.
After capacitor contact hole was formed,concact implant to reduce the resistance is performed.
Phosphorous with acceleration energy 80kv was implanted under the capacitor contact .The storage
node of the capacitor consist of n- diffused layer p-n junction is formed under capacitors. Fig2&Fig3
shows the implanted material depth distribution profile by SIMS.

Fig.2 Phosphorous
implant distribution
profile

Fig.3 Boron implant

distribution profile

We will explain junction current with reverse applied voltage, and this condition is DRAM cell storage
1condition. Fig.4 shows the measured feature of the current-voltage (I-V) characteristics with
Aglient 4156C, the leakage current increases exponentially as the applied reverse voltage increases.

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This characteristic cannot be explained neither by diffusion current nor G-R current. Diffusion current
Diffusion current does not depend on the applied voltage because the concentration of the minority
carrier at the depletion layer edge remains constant even if the reverse bias change.
Generation-Recombination current has a square root relationship to the applied voltage. These two
kinds of relationship are different from the I-V characteristics shown in Fig.4.

Contact implant dosage Vs Data Retention Time(ms)

300
250
200
150
100
50

Data
Retention
Time(ms)

0
6.00E+ 7.00E+ 8.00E+ 9.00E+ 1.00E+ 1.10E+ 1.20E+ 1.30E+ 1.40E+
03
03
03
03
04
04
04
04
04

Fig.5 Experiment of different

Fig.4 p-n Junction I-V
contact implant dosage vs data
characteristic with
Thermal Field Emission current has an exponential relationship to theretention
appliedtime
voltage. Thermal
reverse voltage
emission rate from a deep level is enhanced by tunneling effect due to the strong electric filed in the
depletion region. There, the conduction mechanism of the leakage current of p-n junction formed on
P+ type substrate is thermionic field emission, When no bias is applied to the junction, diffusion
current flows at the n+/p-well junction, when the reverse bias is applied to the junction, diffusion
current disappears and TFE current can be observed. Different from diffusion current, the junction
leakage current increases as the boron concentration of the n-/p-well increases. The electric field in the
depletion layer is enhanced when the Phosphorous/boron concentration of the p-well increases. It
leads to the enhancement of the tunneling probability of electron. Therefore, the thermal emission of
electron from a deep level also increases.Fig.5 is process experiment with different contact implant
dosage result. From the result ,we have the conclusion: higher node dosage of n-p junction can
decrease the data retention time because of higher junction dosage induced higher electrical field. This
give us the clue to improve DRAM product data retention time.
Because reverse junction leakage usually is less than 10-12order,the junction leakage direct
measurement on the wafer is not sensitivity for High-density DRAM product; a useful method to
evaluate the leakage performance of DRAM product is tail bits distribution. The distribution can be
divided into two distributions: Main Distribution and Tail Distribution The retention time of
almost all the memory cells belonged to Main Distribution. However, there are a few memory cell
whose retention time does not belong to Main Distribution: We defined this shorter retention time

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distribution as Tail Distribution that follows 6rules. Tail Distribution dominates the refresh
characteristics of DRAM. [2] Usually, the DRAM products have redundancy capacity design for
normal tail bits, by using laser repair, the tail bits will be replaced by redundancy cells. If the tail bits
count appear beyond redundancy repair capability in less than designed data retention time, this chip
will be categorized as Non-Function chip.
A static retention test can be used on DRAM product to catch tail bits, the test methods is described as
follows: Write one(high level voltage) to the cell capacitor with word line fast operation ,Waiting for
some time with doing nothing, Read data from each cell with word line fast operation.The program
was created on Mosaid 4205 tester.This is a kind of general purpose memory engineering tester and
widely used on memory product electrical failure analysis. We can see from Fig6, with lower
Vbb(bulk bias voltage), tail bits increase more rapidly, this means worse data retention performance.
This result match I-V characterization shown on Fig.4, junction leakage increase with applied reverse
voltage.So,this give us the clue to evaluate the junction leakage more precisely.We can judge from
Fig7,the Vbb Vs Fail Bit Count curve,Condition1s fail tail bit count increase faster when Vbb
decrease compared with the other three which means high reverse junction leakage. Usually, Vbb is
set at 0.2V to suppress subthreshold leakage, and at the same time ,a low level reverse junction
leakage can be kept. We can use this kind of test methods to evaluate the junction leakage of different
DRAM process instead of insensitivity Direct Current measurement.

Fig.6 Tail bits distribution under

different Vbb condition.

Fig.7 Tail bits distribution under different

process condition when Vbb decrease.

Another kind of junction leakage mechanism is defect related, either contamination or crystal defect
across node junction or LDD area can break down the barrier of p-n junction. Fig.8 is a failure
analysis case of high junction leakage, From the TEM(Transmission Electron Microscope) picture, a

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slice shape defect was observed ,and material analysis on the defect found abnormal Titanium peak,
This Titanium diffuse from the top of poly contact. This Ti contamination across Junction cause huge
junction leakage. Crystalline defects in the substrate can also cause junction leakage and degrade the
data retention property. Especially for downscaled devices, the probability of the failure due to the
defects are increased, because the junction layers become shallower. It is generally known that the
dislocation loops are generated at Ion implant, Poly etch, Spacer SiN deposition.Fig.9 shows
dislocation across the junction layer from the side-wall edge in transistor with LDD structures. This
pictures shows the cross-sectional TEM picture after poly etch at the sample with LDD structure. The
dislocation profiles were observed at the depth of 50nm. Usually,LDD thickness is 300~400A,this
dislocation depth is 500A,which is across the junction.

Fig.8 Ti contamination
caused junction leakage

Fig.9 Silicon crystal

defect across LDD area

2.2GIDL
A negative worline bias voltage usually named VNWL is used to reduce the subthreshold leakage of
deep submicron DRAM cell transistors. The sub threshold leakage of cell transistors poses a great
challenge for next generation cell transistor. Owing to the concern of junction leakage increase, the
cell transistors threshold voltage(Vt) cant be raised simply by increasing the dose of Vt adjustment
implant or arsenic implanted shallow junction[3].It is very difficult to control the process-induced

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point defects and rduce the channel doping concentration without degrading the subthreshold
characteristics of cell transistors.Fig.2 shows the Vt roll-off characteristics of cell transistors for
technology generation. It was found that the short channel effect (SCE) is getting serious with the
shrinkage.So,It is necessary to apply a negative worline bias voltage at the memory cell design in
order to gain the cell transistor on current while maintain desired off current. Although the sub
threshold characteristic of a DRAM cell can be improved by applying negative word line bias, the
GIDL can come serious. Saino et al. reported that GIDL current impacts tail retention time distribution
dominantly [4] When a 1signal stores in the storage capacitor, the junction near the capacitor is also
at high level. Therefore, if the gate is turned off at negative word line bias, the gate induced drain
junction leakage is serious because of the increased vertical electrical field as compared to ground
word line[5].
Fig.10.shows the schematic of cell device structure, and proposed GIDL current path. A negative
voltage is applied on the word line when the cell transistor is turned off. Depletion region border in the
p-well and the node-diffusion in the bias condition is marked b a dotted line. The rather high voltage
difference between gate and node-diffusion causes a strong field across the oxide in the overlap region.
If the electric filed becomes sufficiently large, the valence band electrons can tunnel to conduction
band and they are immediately swept laterally to the node-diffusion, which has a lower electron
potential. GIDL leakage can be reduced by tuning LDD implant recipe,Fig11 shows the Data
Retention performance under different LDD implant condition, The red curve stands the static data
retention characterization curve, the acceleration voltage is 30Kev with 2.5e13 dosage. Compared
with the blue curve with condition 20Kev and 2.5e13, high acceleration voltage shows better data
retention performance. This result can be explained as below: Higher implant energy can increase the
depth of Ion distribution, The LDD diffusion area depth under GOI will increase also, so the electrical
filed will decrease when same voltage dropped across the area.

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2.3Subthreshold Leakage
As the device shrinkage, the source and drain junction depletion length cant be ignored compared
with effect channel length ,short channel effect is significant when the channel length is in deep
submicron . Fig.12 is the device simulation result of threshold voltage (Vt) under different channel
length with Pocket (Halo) implant. Pocket implant is performed with the material same with bulk
substrate. It can increase the device Vt and roll off short channel effect, increase Poly gate dry etch
process window. In the DRAM fabrication, Poly gate etch CD control is critical for data retention
performance.When poly CD is lower than the target value, Vt will be lower which means subthreshold
leakage is beyondFig.10
designSchematic
value. of
Fig.11 Experiment of LDD
GIDL mechanism
implant to suppress GIDL

VT(V)

Channel Length(um) Vs Vt(V)

1.000
0.900
0.800
0.700
0.600
0.500
0.400
0.300
0.200
0.100
0.000

VT(V)
0.00

0.10

0.20

0.30

0.40

0.50

0.60

Channel Length(um)

Fig.12 Simulation result of

Channel length vs. Vt

Fig.13 Correlation
between Vt vs. Yield

Fig14,is wafer map of a DRAM product, the red area means fail dies that suffer a test item disturb
fail, the disturb test is to detect subthreshold leakage of the DRAM transistor. Wafer bottom suffer
serious disturb fail. Fig13 is correlation analysis of two parameters Vt vs. Wafer Yield ,from the
result we can see the wafer yield have correlation vs. transistor Vt .Fig14 is the VT measurement value
at different region of wafers. Where there are disturb fail die, Vt is lower that of good dies.

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Fig.15 Wafer map that

Fig.14 WAT
3.Conclusion
hasdisturbfailed die in it
measurement found VT
We analyze three major DRAM
device
leakage
paths,Junction
Leakage,GIDL
Leakage,and Subthreshold
lower at failed region
leakage.And studied the current mechanism and how to evaluation and diagnose the current path. .With
device shrinkage, due to shallow junction ,Gate Oxide tunneling, short channel effect etc. transistor leakage
is becoming more and more serious.How to quickly and precisely identify leakage path and process issue in
DRAM fabrication is very important.More efficient and useful Electrical,Physical failure analysis and data
analysis methods is always great challenge for DRAM data retention analysis.

Acknowledgement
Thanks the great instruction and help from Dr. Qiyu Huang and Shirla Cheng of School of
Microelectronics,Shanghai Jiao Tong University.
References
[1]

T.Hamamoto,S.Sugiura,and S. Sawada,Well Concentration:A novel scaling limitation factor

derived from dram retention time and its modeling,in IEDM Tech.Dig,.1995,915-918 .

[2]

El-Bakry, H.M (2001) Human Iris Detection Using Fast Cooperative Modular Neural Nets. Neural Networks,

[3]

S.KamoharaStatistical PN Junction Leakage Model with Trap level Flucuation for

Tref(Retention)-Orientied DRAM DesignIEDM.PP.549-541, 1999
A.Chatterjee et al.,A pass transistor design methodology for 256Mbit DRAM and beyond,in
Proc.Synp.VLSI TechnolDtg.Tech.Papers,1999,PP.137-138
K.Saino et al.,Impact of gate-induced drain leakage current on the tail distribution of DRAM

[4]

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[5]

data retention time,in IEDM Tech.Dtg.2000,pp.837-840.

Minchen Chang etcImpact of Gate Induced Drain Leakage on Retention Time Distribution of
256Mbit DRAM With Negative Wordline BiasIEEE Transactions on electron
Devices,VOL.50,NO.4,APRIL.2003

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