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I.
INTRODUCTION
539
Power Flow
1:N
L1
D1
VLow
A.
Circuit Description
Fig. 1 shows the proposed converter. The input side (VLow)
is connected to a low voltage, high current bidirectional dc
source, the output side (VH) is connected to a 24 V dc system.
The main circuit is an isolated Cuk converter [16], and the two
main switches S1 and S2 work in a complementary mode.
When the power flow is from VLow to VH, S2 is operated in
the SR mode. When the power flows in another direction, S1
works in SR mode. With the synchronous rectification, the
switches conduction and switching loss can be decreased. In
the circuit diagram, D1 and D2 are the body diodes of S1 and
S2, respectively. For each switch, ten MOSFETs are used in
parallel. Due to the complexity of the layout, no external
Schottky diodes are used. An active snubber circuit is added to
recover the energy stored in the leakage inductance. DS1, DS2,
Csb1, Lsb1 and SS1 form the low voltage side active snubber
circuit; and DS3, DS4, Csb2, Lsb2, Ss2 form the high voltage
side active snubber circuit.
B. Operation Principles
If the power flow is from VLow to VH, the high voltage
side snubber circuit will not influence the circuit operation,
and SS2 can be disabled. Then the low voltage side referred
equivalent circuit is shown in Fig. 2, in which LS is the
leakage inductance of transformer, SS1 and S1 have the same
gate signal. Vice verse, when the power changes direction,
SS1 is disabled and SS2 is controlled in synchronization with
S2.
The circuit analysis is based on following assumptions: 1)
C1 and C2 are large enough to keep almost constant vC1 and
vC2; 2) L1 and L2 are large enough to result in negligible
ripple currents on L1 and L2. For the circuit shown in Fig. 2,
at steady state [16]:
CLow S
1
CS1
DS1
Lsb1
SS1
DS3'
DS4'
DS2
Csb1
Csb2'
L2'
C2'
D2'
Lsb2'
CS2'
S2'
CH'
SS2'
L1
vC1
vL1
VLow
CLow
iLs
C1
iS1
D1
S1
vLs
DS1
Lsb1
LS
CS2 D2
DS2
vS1
CS1
CH
vS2
SS1
Csb1
vcsb1
S2
C2
L2
vC2
VH
iL2
vL2
C1
I
VH
D
,
= Low =
VLow
IH
1 D
v C1 = V Low , and
v C2 = V H .
where D is the duty ratio of S1.
(1)
(2)
(3)
540
Step 2 (t1 t2): at t1, S1 is turned off. Since the voltage across
S1 is clamped by C1 and Csb1, and vCsb1(t1)= vC1, S1 is
ZVS off. The main circuit currents iL1 and iL2 begin to
flow through Csb1, Csb1 will first release the stored energy
to C1 until vCsb1 reaches zero. After that this energy
feedback stops and Csb1 begins to absorb energy from L1
and L2. vCsb1 keep increasing and reaches VH at t2. Since
LS<< L2, the voltage on LS is negligible. Then D2 is
forward biased and starts to conduct current.
Vgs,S1 &
Vgs,SS1
Step 5 (t4 t5): both iL1 and iL2 are flowing through S2. The
current on DS1 has reached zero and DS1 is reversed biased.
The voltage on S1 is clamped by C1, LS and C2. Because
LS << L1, vLs 0, then vS1 vC1 + vC2 = VLow + VH.
Step 6 (t5 t6): at t5, S2 is ZVS off, and both iL1 and iL2 will go
through D2.
Step 7 (t6 t7): at t6, the deadtime is over and S1 and SS1 are
turned on. Since vLs = vC1 + vC2 = VLow + VH, iLs will
increase from iL1, and S1 is ZCS on because iS1 = iL1 + iLs.
In the active snubber circuit, resonant inductor Lsb1 will
clamp the change current through SS1, so SS1 is also ZCS
on. Then, Csb1 begins to resonate with Lsb1, and vCsb1 is
decreasing.
vS1
ZVS OFF
iS1
ZCS ON
vCsb1
Energy
Recovery
Step 8 (t7 t8): at t7, both iL1 and iL2 are flowing through S1,
there is no current flowing through D2. The voltage on D2
is clamped by C1, LS and C2. Since iLs = iL2, and iL2 has
negligible ripple, vLs 0, then vD2 = vC1 + vC2 = VLow +
VH, D2 is reverse biased. In the active snubber circuit,
vCsb1 keep decreasing. At t8, vCsb1 reaches vC1 and is
clamped to be vC1 by D1 and DS1.
ZVS On
iCsb1
iLsb1
Vgs,S2
vS2
ZVS Off
iS2
SR
iD2
iL1
iL2
iLs
t
0
t1 t2 t3 t4
t5 t6 t7
t8
TS TS + t1
541
III.
DESIGN GUIDELINE
VLow
ILow
VH
Pmax
Vgs,S2
iL1
IL1
iL2
IL2
iLs
iL2
iL1
iCsb1
iDS1
iDS2 , iLsb1
& iSS1
VCC
GS3
GD1
Gate
Tr
GD3
GR1
Chip
GS2
GS4
GD2
1:N
GD4
GD5
GC1 10*IPB019N08N3
Drive
6TS TS
GD6
542
VLow + VH
t , 0 < t < 1TS
LS
, and
(4)
0
, 0 < t < 4TS
I L1 + I L 2
, 5TS < t < DTS
(5)
where
1 =
5 =
LS I L1 + I L 2
TS VLow + VH
21 TS
, 1 =
1
LS Csb1
VLow + VH Csb1
+D
)
I L1 + I L 2
TS
, 4 = (
and
+ 4 .
LS
Csb1
(6)
e) iLs = IL1, from 5TS to TS .
Figure 6. Active snubber circuit operation description
VLow
0,
3TS < t < TS
vC1=VLow
where
C1
S1
SS1
DS1
2 =
1
Lsb1 Csb1
3 = 2 + (
Lsb1
. (7)
DS2
VLow
) / (2TS ) ,
vCsb1_ initial
, 2 = (arccos
) sin(2 2TS )
and
Csb1
iDS 1
0,
0 < t < 2TS
V
(2 Csb1 vCsb1_ initial sin(2 2TS )) Low (t 2TS ), 2TS < t < 3TS
Lsb1
0,
3TS < t < DTS
=
I L1 + I L 2 ,
DTS < t < 4TS
0,
5TS < t < TS
vCsb1= - VLow
b) vCsb1 is clamped to VLow, from 2TS to 3TS .
. (8)
1
TS
TS
iSX (t )2 dt
(9)
543
1
TS
TS
iDSX (t )dt
(10)
iCLow _ RMS =
I L2 ,
1TS < t < DTS
iC1 =
I L1 ,
DTS < t < TS
iC 2
V + VH
t ,
I L1 Low
LS
I L2 ,
=
I ( I + I ) cos( (t T )),
1
4 S
L1
L1
L2
I L1 ,
, and
(11)
(13)
1
TS
TS
iCX (t )2 dt
(14)
1 VLow D TS
L2
2 3
, and
.
(19)
(20)
(12)
0,
2TS < t < DTS
iCsb1 =
I L1 + I L 2 ,
DTS < t < 4TS
( I + I ) cos( (t T )), T < t < T
1
4 S
4 S
5 S
L1 L 2
0,
5TS < t < TS
iCH _ RMS =
1 VLow D TS
L1
2 3
IV.
I L1 + Low
t ,
LS
I L2 ,
iLs =
I + ( I + I ) cos( (t T )),
L1
L2
1
4 S
L1
I L1 ,
iLsb1 = iDS 2
VLow
0,
3TS < t < TS
(15)
.(16)
(17)
iL 2 _ RMS = I L 2 .
(18)
For transformer, it has both core loss and copper loss. The
core loss calculation is similar to normal forward converter
cases, thereby it is not elaborated here.
544
Vgs_S2'
10 V/div
SR
vds_S2'
20 V/div
VH
20 V/div
Efficiency
0.8
0.75
0.7
300
600
Power (W)
900
VLow=3 V
VLow=6 V
VLow = 9 V
VLow=12 V
1200
Figure 10. Low voltage side switching transients and snubber operation
waveforms
545
0.65
REFERENCES
[1]
Efficiency
0.6
0.55
[2]
0.5
0.45
[3]
0.4
0
30
60
90
Power (W)
120
150
[4]
VLow=1.5 V
[5]
Figure 13. Efficiency curve when VLow = 1.5 V
S1
S2
SS1
DS1
DS2
C1
C2
Csb1
L1
L2
Lsb1
Transformer
CLow
CH
Current (A)
iS1_RMS = 237.7 A
Is2_RMS = 215 A
Iss1_RMS = 101 A
iDS1_RMS = 101 A
iDS 1_Mean = 50.6 A
iDS 2_RMS = 101 A
iDS 2_Mean = 50.5 A
iC1_RMS =161.2 A
iC2_RMS =156.2 A
iCsb1_RMS =96.4 A
iL1_RMS = 200 A
iL2_RMS =121.5 A
iLsb1_RMS = 101 A
iTr_RMS = 161.2 A
iCLow_RMS = 4.76 A
Ich_RMS = 8.65 A
Total power loss
V.
[6]
[7]
[8]
[9]
Resistance (m)
Power Loss
(W)
0.37
0.367
1.85
VD0 = 0.4 V
RD = 1.25 m
VD0 = 0.4 V
RD = 1.25 m
0.06
0.017
1.85
0.34
0.18
0.18
0.2
18
2
20.9
16.96
18.87
32.95
[11]
[12]
32.95
[13]
[10]
1.56
0.41
17.2
13.6
2.66
1.8
5.20
0.4
0.14
165.60 W
[14]
[15]
[16]
[17]
CONCLUSION
[18]
546