Вы находитесь на странице: 1из 4

A Novel Digital Controller for Boost PFC Converter with High Power Factor and Fast Dynamic Response

Daying Sun, Weifeng Sun, Qing Wang, Shen Xu, Shengli Lu National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

E-mail:hasdysun@seu.edu.cn

Abstract

A novel digital controller for boost power factor

correction converter is proposed to achieve high power

factor and fast dynamic response. A method of direct

duty cycle calculation is adopted to improve the power

factor. The prediction module is adopted to estimate the

track of the output voltage and the inductor current of

next switching cycle in advance to improve the dynamic

response. A multiplex successive approximation

analog-to-digital converter (ADC) is designed to aim

high resolution via little hardware resource. Meanwhile,

a novel digital pulse width modulator (DPWM) is

realized to improve the regulation linearity. The boost

PFC converter with proposed digital controller based

on the field programmable gate array (FPGA) has been

implemented. Experimental results indicate that the

proposed digital controller can achieve high power factor

more than 0.98, the dynamic response under load

variation is about 80ms and the output voltage overshoot

is about 6%.

Index Terms

PFC converter, digital controller, high power factor, fast

dynamic response

1.

Introduction

Power factor correction (PFC) converters have been

widely used in power conversions that are required to

meet EN61000-3-2standard [1][2]. In low or medium

power applications, discontinuous conduction mode

(DCM) as well as critical conduction mode (CRM) is

widely used due to its simplicity and small inductor size.

In high power applications, continuous conduction mode

(CCM) is often used due to lower conduction losses and

reduced EMI filtering requirements[3][4]. Digital PFC

controller has received increased attention in PFC

applications recently [5][6], due to its improved

integration, programmability and opportunity for

realization of more advanced control technique.

Compared to peak current control or hysteresis current

control, average current control is commonly used for

boost PFC operating in CCM mode because of its higher

power factor and less sensitive to switching noise [7][8],

But the implementation of such control approach is

complicated. Meanwhile, as is a tradeoff between the

dynamic response and the input current distortion caused

by output voltage ripple, the bandwidth of the voltage

control loop is typically 10-15 Hz.

This paper presents a novel digital controller for boost

PFC converter operating in CCM to achieve high power

factor and fast dynamic response. The organization of

paper is as follows. The structure of digital PFC

controller system is described in Section 2, and the

design of digital controller is introduced in details in

Section 3. The experimental results are analyzed in

Section 4 and the conclusion is described in Section 5.

2. Architecture of the digital controller

The architecture of the digital controller system for boost

PFC converter is shown in Figure l. The output voltage,

input voltage and input current are respectively sampled

by the three-time-sharing multiplex successive

approximation ADC, the prediction module is used to

estimate the track of the output voltage and the inductor

978-1-4673-6417-1/13/$31.00 ©2013 IEEE

current of next switching cycle, the direct duty cycle calculation module is used to improve the power factor and simplify the control loop, the novel DPWM is utilized to realize the digital-to-analog conversion.

Boost PFC Converter V in D V O i L L AC Q C EMI
Boost PFC Converter
V
in
D
V
O
i
L
L
AC
Q
C
EMI
R
Filter
i
i
R
C
Vo[t]
V
in [t]
I
in [t]
V
in [n]
V
o [n]
three-time-sharing multiplex successive
approximation ADC
I
in [n]
direct
d[n]
_
d
* [n]
e[n]
Novel
PID
Prediction
duty cycle
V
o [n+1]
DPWM
Compensation
Moudle
calculation
+
e[n]
V
ref [n]
FPAG
Digital Controller

Figure l. The architecture of digital PFC controller

3. Design of the digital controller

3.1 Direct duty cycle calculation law The aim of power factor correction (PFC) boost converter is to make the input average current follow the input voltage perfectly. As shown in Figure 1, if the aim is satisfied, the whole PFC converter system can be equivalent to the resistance R e , and the system can be described as

u g

Ri

eg

(1)

Where u g is the input voltage and i g is the average component of the inductor current. For CCM boost converter, the relationship between the input voltage u g ,

the output voltage u o and the duty ratio d is expressed as

uu

g

o

(1

d

)

(2)

Based on the formula above, the expression can be derived as

Ri

eg

Ri

sg

u

o

R

s

R

e

(1

u

o

(1

d

)

d

)

u

m

(1

d

)

1

T

d T

(1

0

)

u d

m

,0 t T

(3)

(4)

Where R s is the equivalent current detection resistance of

system and u m is equal to u o R s /R e . The formula (4) can be

modified through discrete operation. The digital control law can been expressed as

*

dn []

1

R

s

u m

in []

g

(5)

From the above formula, compared to the average

current control, such digital control approach omits the

input voltage sensing and has better immunity for the

variation of input voltage and electrical load.

3.2 Prediction module

According to the PFC circuit structure, whenever the

power system in steady-state or dynamic-state, the relationship of voltage and current of inductance can be described as

dI

L

dt

V

L

L

V

in

L

V

L

in

V

o

, MOSFET is off

, MOSFET is on

(6)

Where I L is the inductor current, V in is the input voltage, V o is the output voltage, L is the inductance of the boost inductor. According to (6), the output voltage and the inductor current of the next cycle can be derived as

k

1]

i

[

LL

i

[

k

]

v

1]

[

oo

[

k

v k

v k

in

[]

]

L

v k

[

o

]

RC

dT

s

dT

s

v k [] vk [] in o (1 d T ) s L v k
v k
[]
vk
[]
in
o
(1
d T
)
s
L
v k
[
]
[ k ]
o
i av
R
(1
d T
)
s
C

(7)

The average current I av [k] can be calculated as

i av

[ k ]

 

v k

[

]

i

L

[

k

]

2

in

L

 

dT

i

sL

[

k

1]

 

4

(8)

3.3 Multiplex successive approximation ADC

A three-time-sharing 8-bits

approximation ADC is designed for digital PFC controller. The proposed ADC has a 1.6MHz sampling

frequency and an input voltage range from 0 to 3.3V.

Charge redistribution method is employed to realize an 8-bit DAC. To reduce the offset error of comparator,

multiplex

successive

a self-calibrating comparator is adopted. Digital control logic circuits not only select the input channel in turn and control the outputs of the ADC with three shift registers, but also coordinate the work between different modules. The architecture of analog-to-digital converter is shown in Figure 2.

Clk

I

vin0

vin1

vin2

vcm

Control signal generator EN_ADC Input selecting S&H SA d[7:0] And Register DAC Comp Control r[7:0]
Control
signal
generator
EN_ADC
Input
selecting
S&H
SA
d[7:0]
And
Register
DAC
Comp
Control
r[7:0]
logic
Shift
Shift
Shift
register
register
register
Q1[7:0]
1
2 3
Q3[7:0]
Q2[7:0]

Figure 2. The architecture of proposed ADC

3.4 Novel digital pulse width modulator

The digital pulse-width modulator has the function of converting digital signal to analog signal. A 10-bit digital

pulse-width modulator is designed for digital PFC controller. The architecture of digital pulse-width modulator is shown in Figure 3. The delay line of the DPWM takes advantage of the programmable delay unit (PDU) .The delay-locked loop (DLL) technology is used to eliminate the influence of process, temperature and voltage that improve the linearity of PWM dramatically.

Digital PLL Clk Ring oscillator Counter 0 1 2 2 6 -1 Duty LSB [5:0]
Digital PLL
Clk
Ring oscillator
Counter
0
1
2
2 6 -1
Duty LSB [5:0]
4_bit
2 6 : 1 Mux
out
Comparator
Duty MSB[9:6]
4_bit
out
Duty[9:0]
Comparator
R
4_bit
Q
out
S
dpwm_out

Figure 3.The architecture of digital pulse-width modulator

4. Experimental results

A boost PFC converter with the proposed digital controller based on FPGA has been implemented. The parameters of the boost PFC converter are listed as follows: V in =90-265 V, output voltage V o =400V, output power P o =300W, line frequency f line =50Hz, switching frequency f s =100kHz. The proposed digital controller is coded in verilog hardware description language and implemented on the FPGA control board.

The input current and voltage waveforms for the full load under the steady state are shown in Figure 4. The input current can follow the input voltage under such condition, the power factor is 0.985.The proposed digital controller can achieve high power factor under the steady state.

V in I in Time:10ms/div
V in
I
in
Time:10ms/div

Figure 4.

Measured input current and voltage waveforms for the full load under the steady state

The dynamic responses of the PFC converter with the proposed digital controller under load variation from 50% load to full load and from full load to 50% load are shown in Figure 5 and Figure 6 respectively. It can be seen that the PFC converter has fast dynamic response and small overshoot.

70ms V o: 400V/div Time : 100ms/div I in: 5A/div
70ms
V o: 400V/div
Time : 100ms/div
I in: 5A/div

Figure 5. Measured output voltage and input current dynamic response for load variation from 50% load to full load

80ms V in: 400V/div Time : 100ms/div I in: 5A/div
80ms
V in: 400V/div
Time : 100ms/div
I in: 5A/div

Figure 6. Measured output voltage and input current dynamic response for load variation from full load to 50% load

Table 1 shows the performance comparison with previously reported works. With the proposed digital controller, the boost PFC converter features high power factor over 0.98. Meanwhile, the PFC converter has fast dynamic response and small output voltage overshoot.

Table 1 Performance comparison

 

[6]

[8]

This work

Operating Condition

in =220V

V

o =400V

V

P

o =300W

s =100kHz

f

in =110V

V

o =200V

V

P

o =400W

f

s =50kHz

in =220V

V

o =400V

V

P

o =300W

s =100kHz

f

Power Factor

0.999

0.978

0.985

Dynamic Response(ms)

200

90

80

Overshoot(%)

6

8

5

Load Variation

100

60

100

50

100

50

5.

Conclusion

The proposed digital PFC boost controller can attribute to achieve high power factor and fast dynamic response over a universal input voltage range. The main feature of the proposed controller is that novel digital control law is implemented without the use of input voltage sensing so the realization cost of controller is reduced. Furthermore the track of the output voltage and the inductor current of next switching cycle can be estimated in advance to improve the dynamic response. The experimental results have demonstrated the effectiveness of the controller.

Acknowledgments

The authors would like to thank the scientific research guidance foundation of southeast university wuxi branch campus.

References

[1] O.Garcia, J.A.Cobos, R.Prieto, P.Alou, and J. Uceda, “Single phase power factor correction: A survey,” IEEE Trans. Power Electron., 18, p.749-755( 2003).

[2] B.Singh, B.N.Singh, A.Chandra, K.Al-Haddad, A.Pandey, and D.P. Kothari, “A review of single-phase improved power quality AC-DC converters,” IEEE Trans. Ind. Electron., 50, p.962-981( 2003).

[3] P.Barbosa, F.Canales, J.Crebier, and F.C.Lee, “Interleaved three-phase boost rectifiers operated in the discontinuous conduction mode: Analysis, design

considerations and experimentation,” IEEE Trans. Power

Electron. , 16, p.724-734(2001).

[4] K.Taniguchi and Y.Nakaya, “Analysis and

improvement of input current waveforms for discontinuous-mode boost converter with unity power factor,” IEEE Power Conv. Conf., p. 399-404(1997).

[5] S.Buso, P.Mattavelli, L.Rossetto, G.Spiazzi, Simple

digital control improving dynamic performance of power factor pre-regulators,IEEE Trans. Power Electron., 13, p.

814-823(1998).

[6] Moon S, Corradini L, Maksimovic D. “Autotuning of digitally controlled boost power factor correction rectifiers,” IEEE Trans.Power Electron, 26, p.3006-3018

(2011),

[7] J.Rajagopalan, F.C.Lee, P. Nora, A general technique for derivation of average current mode control laws for single-phase power-factor-correction circuits without input voltage sensing,IEEE Trans. Power Electron., 14, p.663-672(1999). [8] F. Zhang and J. Xu, “A novel PCCM boost PFC converter with fast dynamic response,” IEEE Trans. Ind. Electron., 58, p.4207-4216(2011).