2009 27th IEEE VLSI Test Symposium

A High-level Signal Integrity Fault Model and Test Methodology for

Long On-Chip Interconnections
Sunghoon Chun1, Yongjoon Kim1, Taejin Kim2 and Sungho Kang1
1

Department of Electrical and Electronic Engineering Yonsei University

134 Shinchon-dong Seodaemoon-gu, Seoul, Korea
E-mail: <shchun, yjkim, shkang>@yonsei.ac.kr
2
Avionics R&D Lab., LIG Nex1 Co.
100 Shinsungdong Yoosung-gu, Daejeon, Korea
E-mail: tj2010@lignex1.com.

AbstractIn this paper, considering the interconnection

topology information, an abstract model and a new test pattern
generation method of signal integrity problems on interconnects
are proposed. In addition, previous SPICE-based pattern
generation methods are too complex and time consuming to
generate test patterns for signal integrity faults. To more
accurately detect signal integrity defects on practical on-chip
interconnection lines and avoid time consuming for
interconnection analysis, in this paper, we propose a new highlevel signal integrity fault model to estimate noise effects based on
process variation and interconnect signal transition. Experimental
results show that the proposed signal integrity fault model is more
exact for long interconnects than previous approaches. In
addition, the proposed method is much faster than the SPICEbased pattern generation method.

however, this method requires much large computation

power for solving numerical equations.
Moreover, since previous works [1-9] did not consider the
effect of interconnection topology, their accuracy is much
more decreased. For the effect of interconnection topology, in
general, the SPICE-based simulation is necessary. However,
the SPICE-based simulation is prohibitively time consuming
and are unsuitable for iterative evaluations of SoCs. To
alleviate this problem and to generate more effective test
patterns for signal integrity faults, we already proposed the
high-level test pattern generation method with the
consideration of the interconnection topology in [10]. In
general, the proposed fault model in [10] is efficient to
simply generate test patterns for signal integrity faults with a
slight error. However, for high-speed VLSI circuits, highlevel signal integrity fault model presented in [10] is not
sufficient to accurately detect signal integrity defects on
practical long interconnections because it cannot consider
physical phenomenon of practical on-chip interconnection
lines.
To more accurately detect signal integrity defects on
practical on-chip interconnection lines and avoid time
consuming for interconnection analysis, in this paper, we
propose a new high-level signal integrity fault model to
estimate noise effects based on process variation and
interconnect signal transition. Especially, for signal integrityinduced delay errors, the proposed high-level fault models
are based on TWA (traveling wave based waveform
approximation) technique for multi-coupled interconnects. In
addition, the proposed test pattern generation for a novel
high-level fault model for signal integrity faults is proposed
considering the interconnection topology in the similar
manner of [10].
The rest of the paper is organized as follows. Section 2
explains the signal integrity effects on long on-chip
interconnection lines and two main errors caused by signal
integrity noises. In Section 3, new high-level fault models for
signal integrity-induced errors are proposed and Section 4
provides the proposed test pattern generation algorithm.
Experimental results are presented in Section 5 and this paper
is concluded in Section 6.

I. INTRODUCTION
Signal integrity issues arise from long on-chip
interconnects where the effect of parasitic elements may
jeopardize the functionality and reliability of high
performance SoCs. Long on-chip interconnects fall primarily
into three categories: data-buses, control, or clock. Data lines,
especially those such as data buses between the central
processing unit (CPU) and cache, travel in groups, generally
have half-a-chip-edge in length, and have a small load at the
receiver. Such lines synchronously operate and are designed
for minimum path delay over fairly long length. Therefore,
these data-buses are vulnerable to signal integrity problems
due to their synchronous and possibly in-phase data pattern.
Therefore, in this paper, we focus on testing signal integrity
faults on long interconnects like data-buses.
To enable testing for signal integrity defects, several fault
models and test generation methods have been proposed to
capture the signal integrity effects in gate-level circuits [1-3].
In addition, many approaches for analysis, modeling and
testing signal integrity effects on long interconnect have been
proposed [4-7]. Maximum Aggressor (MA) fault model was
presented in [4], which abstractly models crosstalk effects on
interconnects with a linear number of faults. Although MA
significantly simplifies the problem for interconnects
modeled as RC circuits, it suffers from lack of precision
needed for accurate RLC interconnect models [8]. In [5], the
authors presented a BIST for signal integrity using pseudorandom patterns. Signal integrity fault model was presented
in [9]. This was based on accurate RLC interconnect models;

1093-0167/09 $25.00 2009 IEEE

DOI 10.1109/VTS.2009.38

II. SIGNAL INTEGRITY EFFECTS ON LONG INTERCONNECTS

According to [11], the short local wiring with the highest
159
152

approximation in the time domain.

When the load is open circuit, the response wave becomes
at double the incident wave. But, there are many frequency
components from dc to very high frequency in a pulsed
signal. In addition, since the load has a capacitive reactance
and this impedance depends on the frequency, the reflection
coefficient is inherently frequency-dependent. Since the
sharp edge of the time domain voltage response which is the
summation of the incident and reflected waves is blunt a bit,
therefore, the response wave can be depicted by the
combination of a linear ramp shape and a RC-like behavior
wave shape.
In this case, the first incident wave arrives at the load with
the time of the flight (tf1) of a wave that is as follows.
(1)

density and R>500/cm are found useful for lengths less

3mm. As the scaling to smaller dimensions continues, the
short wires will have resistance several times this value, but
their behavior will stay the same. Their capacitance and
capacitive coupling to adjacent neighbors are the limiting
factors due to delay and delay variation. The medium-length
lines with 100<R<500/cm can be used for lengths up to
10mm if driven by low-impedance drivers and have wide
line-to-line separations that result in low crosstalk. This is
especially important as noise budgets are shrinking. Smaller
devices use lower Vdd levels that could generate lower noise.
However, signal transitions are faster, thus resulting in higher
noise budgets are shrinking. In addition, processing
tolerances for both the devices and the interconnect layers
and larger Vdd variation result in overall noise budget
reduction. Noise sources also have a higher probability of
overlapping within the shorter cycle-time windows. Based on
analysis of [11], the main noise capacitance is not excessive.
The additional noise is generated by the mutual inductance
term. The longer lines, such as data-buses, control and clock
lines, with R<100/cm, can propagate fast signals for lengths
greater than 100mm. The circuit representation which
accounts for both capacitance and inductive coupling is
essential for correctly estimating the crosstalk noise. Since
we develop a more accurate and simpler fault model for
crosstalk for long interconnects in a system-on-chip, both
capacitance and inductance are considered.
In a multiple wire system, the signal transitions on
neighboring wires generate crosstalk-induced noise through
the coupling capacitances and the mutual inductances
between wires. In this section, I define the affecting wires as
aggressors and the affected wires as victims. In general,
crosstalk-induced noise is broadly classified into two types.
Glitch noise [12] occurs when a victim line is intended to be
at a stable state and results in an unwanted noise pulse on the
net. Delay noise [13] occurs when noise is injected on a net
when it transitions, and results in a change in the delay of the
net.

where Lline is the inductance of line and Cline is the

capacitance of the line. In this case, including the load
capacitance CL, an effective time of flight (tf0) is
approximated as follows.
(2)
Thus, the effective response time delay () of the incident
wave due to the capacitive load is defined as follows.
(3)
According to [14], in the time interval between (2n-1)tf0-
and (2n-1)tf0+, where n= 1,2,3,, the waveform can be
approximated with a linear function. In contrast, in the time
interval between (2n-1)tf0+ and (2n+1)tf0+, the waveform
can be modeled with an RC-response-like function. The time
constant can be reasonably modeled as follows [14].
(4)
In [14], the output voltage function is approximated for
three coupled lines. This technique can extend to the output
waveform modeling for multi-coupled lines [15]. The
traveling waves of n-coupled on-chip interconnection lines
can be decoupled into the linear combination of the neigenmodes by using a modal analysis technique in the
frequency domain if the lines are identical [16-17]. Using
these decoupling information and the TWA approximation,
the output voltage waveform can be approximated easily
[15].
Although the TWA-based output voltage function is very
accurate, for the high-level signal integrity fault modeling, it
is not necessary to calculate entire output voltage values of
the victim line because it is very time consuming. Therefore,
we propose a new high-level signal integrity fault model
using the TWA-based waveform function [14, 15].
For slowdown and speedup fault models, the time delay is
estimated when the output voltage of the victim line reaches
50% of the transition voltage. Timing delay of the output
signal depends heavily on the changes of the total line
inductance and the total line capacitance, which are related to
the signal patterns. Since a linear combination of n
eigenmodes of the system depends on the signal patterns, the
signal voltage and the time delay for each signal pattern is

III. HIGH-LEVEL SIGNAL INTEGRITY FAULT MODELS

A. High-Level Fault Model for Delay Noise Errors
For high-speed long interconnection systems, the time
domain response is roughly approximated by two or three
poles. However, since the on-chip interconnection signal
changes abruptly during the transition due to the inductance
and the reflection, the time domain response cannot be
accurately modeled with three or more poles. Therefore, the
voltage signal is better physically represented using traveling
wave concepts.
To accurately model the voltage signal using physical
phenomena, in the TWA-technique [14], the low frequency
transient signal is represented with three-dominant poles and
the high frequency characteristics of the transient signal are
incorporated into an approximation function by exploiting the
traveling wave characteristics and a modified RC-response
153
160

different. In this case, the time delay for each signal pattern
mode is defined to td(k), where k indicates the kth signal
pattern mode.

(7)
(8)
where Aj is the polarity of the coupling parameters. In
addition, though the analysis of the SPICE output response
and the TWA-based waveform in the linear output voltage
function, we can find out that most 50% time delay occurs
during the following time interval.
(9)
In this condition, the 50% time delay can be approximated
to (tf0+(k)), where 0.7 0.9, since the criterion of the
crosstalk-induced delay is just required to determine whether
crosstalk-induced error can occur in the victim line or not.
Therefore, for slowdown delay, if the approximated 50%
time delay is equal to or larger than the threshold delay value
tdth, a slowdown error will occur. From the approximated
50% time delay, td50%(k), we can identify whether the
slowdown error occurs in the victim line or not. The criterion
of the slowdown delay fault, DFRsd is as follows.

Figure 1. Modeling for a signal integrity-induced delay noise

Comparing the SPICE simulation and the TWA-based

waveform approximation and analyzing their results, as
shown in Fig. 1, we can find out that the 50% time delay
occurs in the time interval between (2n-1)tf0- and (2n-1)tf0+
(the period of the linear function). A signal voltage function
is modeled with the consideration of all the frequency
components from dc to high frequency. In this case, since the
reflection coefficient of low frequency components is close to
one, most of the low frequency components may be reflected
at the capacitive load. Therefore, the effects of the low
frequency components will make signal transition fast
because the low frequency components contain the major part
of the signal energy and the reflections are appeared in the
time interval between (2n-1)tf0- and (2n-1)tf0+. In this
abrupt transient time, the signal voltage can be modeled with
the linear function and then the signal voltage will reach 0.5
Vdd in this time interval. Therefore, we can claim that the
50% time delay occurs in the following condition.
(5)

(10)
where is an user defined value based on the manufacturing
process. In this paper, we use =0.9 for experiments.
Based on the monotone property, the larger the delay
factor ratio is, the larger a signal integrity noise will be
generated. Therefore, we can determine whether the noise is
large enough to cause an error from the delay factor ratio
without the SPICE simulation. Similarly, speedup signal
integrity error effects can be estimated and generated.
B. High-Level Fault Model for Glitch Noise Errors
For multiple interconnections, the signal integrity noises
caused by the electric and magnetic fields depend on the
signal patterns. Therefore, we should consider the signal
directions to derive a high-level signal integrity noise model.

In this condition, to accurately the 50% time delay value, it

is necessary to calculate the linear output voltage function in
[14]. The 50% delay of the victim line can be determined by
letting the linear output voltage function be 0.5 Vdd. That is
like the equation (6).
However, it is not necessary to calculate the equation (6) in
order to determine whether a crosstalk-induced delay fault
exists in the victim line or not. Since the time interval of the
50% time delay condition in the linear function is very short
and the value of the voltage output function changes abruptly,
the 50% time delay can be expected through calculating just
the values of tf1 and tf0+(k). Note that the values of tf1 and
tf0+(k) can be calculated by using the equation (1), (2) and
(3). Note that the total inductance and the total capacitance of
the victim line in the equations (1), (2) and (3) are as follows.

Figure 2. An example of two coupled interconnections

First, lets consider an odd mode signal propagation for

(6)

154
161

[18], the characteristic

attenuated by a factor of
impedance factor value for lossless line, Zi,eff(lossless) is
attenuated by the same factor. Based on this theory, using the
following equations, the characteristic impedance factor of
lossless lines can be computed.

two interconnects. The odd mode propagation occurs when

two coupled transmission lines are driven with equal
magnitude and 180 out of phase with one another. In odd
mode propagation, the currents on the lines, I1 and I2, always
are driven with equal magnitude but in opposite directions
(Fig.2). Assume that the self-inductances and selfcapacitances are different values according to the length of
interconnections and the mutual inductances and coupling
capacitances are extracted through the parasitic extraction
tools. Applying Kirchhoffs voltage law produces

(18)
For positive glitch error, if the reciprocal of the effective
impedance factor value is equal to or larger than the
reciprocal of the threshold impedance value ZFth, a positive
glitch error will occur. Therefore, from the impedance factor
ratio ZFRpg, we can identify whether the positive glitch error
occurs in the victim line or not. The ZFRpg is as follows.

(11)
(12)
Since the signals for odd mode switching are always
opposite, it is necessary to substitute I1=-I2 and V1=-V2 into
the equations (11) and (12). Therefore, the equivalent
inductance in a pair of coupled transaction lines propagating
in odd mode is
(13)
Similarly, the effect of the coupling capacitance can be
derived by applying the Kirchhoffs current law. The
equivalent capacitance in a pair of coupled interconnection
propagating in odd mode is
(14)
Subsequently, the equivalent impedance for a coupled pair
of interconnection propagating in an odd mode pattern is

(19)

C. High-Level Signal Integrity Fault Models

Using above criterions of crosstalk-induced errors, we can
determine whether the noise is large enough to cause an error
without the SPICE simulation. Similarly, other signal
integrity-induced error effects can be estimated and
generated. Table 1 shows the proposed high-level signal
integrity fault models obtained from the criterion of each
signal integrity error. Note that the impedance factor ratio is
in inverse proportion to the signal integrity-induced voltage.

(15)

Table 1. High-level signal integrity fault models

Next, we consider an even mode signal propagation for

two interconnects. The even mode propagation occurs when
two coupled interconnections are driven with equal
magnitude and are in phase with one another. The even mode
transmission characteristics for a coupled two line system are
derived in the similar manner for the odd mode.
(16)

Signal Integrity
Fault

Pattern of
Victim Line

Positive Glitch

Stable 0

Negative Glitch

Stable 1

Rising Slowdown

This can be expanded to determine the effective

impedance and variations induced by the signal integrity of
multiple interconnection systems. For n interconnections, the
effective impedance factor is as follows.

Falling Slowdown
Rising Speedup

(17)

Falling Speedup

High-Level
Fault Model

Rising
Transition
Falling
Transition
Rising
Transition
Falling
Transition

ZFR: the impedance factor ratio, DFR: the delay factor ratio

IV. TEST PATTERN GENERATION FOR HIGH-LEVEL SIGNAL

INTEGRITY FAULTS

In this case, including resistance in the analysis of the

interconnect line adds significant complexity to the problem
and the resulting equations and fault models fail to provide
much physical insight. For simplicity, a low-loss
approximation [18] is used to include the effect of line
resistance in the above equation (17). In a low-loss
approximation (R < 2Zi,eff), since a voltage step traveling
along a interconnect line of characteristic impedance is

The proposed test pattern generation, called High-SI

(High-level Signal Integrity fault test pattern generation) is
shown in Fig. 3.
For a given interconnect system, an RLC network is
generated by using parasitic extraction tool with process
technology libraries and the modal decoupling [16-17]. Next,
155
162

a victim line is selected from the list of possible victims and

then the interconnection topology graph for the selected
victim line is generated. In [10], we already proposed the
interconnection topology graph to consider the impact of the
length of the aggressor coupled to the victim line. Using the
topology graph with the effective length and the distance, the
effective test patterns for crosstalk faults can be generated
with the consideration of the impact of the interconnect
topology.
After generating the topology graph, the limited factor for
the selected victim line is determined by calculating the
impedance factor ratio and the delay factor ratio with the
topology graph. Using this information, the desired test
vector pair for the proposed fault model can be produced.
Until the list of possible victim lines is empty, the above
test pattern generation procedures are continued. The
generated test patterns for our proposed fault model consists
of a single victim, the limited number of aggressors whose
dominant aggressor source is the coupling capacitance and
other aggressors whose mutual inductances affect crosstalkinduced errors on the victim line more dominantly.

by the use of HSPICE simulations [19]. For first experiment,

a symmetric 8-bit interconnection line is used to compare the
test pattern generated by the high-MX test generation, the
MA test pattern [4] and the MT test pattern [7]. The on-chip
interconnection line parameters for the first experiment are as
follows: the resistance of 68.966/cm, the self-inductance of
7.214nH/cm and the self-capacitance is 2.432pF/cm. Since
the mutual inductances and the coupling capacitances depend
on the distance between the coupled lines, all values are not
explained in this section. For example, the coupling
capacitance and the mutual inductance between the aggressor
line 1 and the victim line are 0.532 pF/cm and 5.115 nH/cm,
respectively. In addition, all the source resistances are
assumed to be 50 and all the load capacitances are assumed
to be 0.1pF. Assuming that the victim line is the line 4 in the
8-bit interconnection line, the HSPICE simulation result of
each test pattern for the rising slowdown delay is shown in
Fig. 4.
As shown in Fig. 4, the proposed high-SI test generation
method can generate more highly effective test patterns than
previous works. The MA fault model [4] tended to
underestimate noise errors due to the RC interconnect model.
When mutual inductance comes into play, the MA fault
model [7] may not have reflected the worst case and caused
other ways to generate test patterns to create maximal
integrity loss. In addition, although the MT fault model can
lead to generate more effective test patterns than the MA
fault model, many test patterns for a single MT fault model
are required because the test patterns for aggressor lines
excluding the limited lines are generated randomly. The
waveform for the MT test pattern in Fig. 4 shows the worst
case of the randomly generated MT test patterns. Therefore,
as shown in the result of the HSPICE simulation, the
proposed high-SI fault model can lead to generate more
effective test patterns which cause more crosstalk-induced
noises.
For the second experiment, we use 8-bit interconnection
that has randomly generated topology in a 0.18m process,
and assume that the line 4 is a victim line. Note that the tool
FASTHENRY was used for extracting inductance values [20]
and the interconnect parameters are as follows: the resistance
of 0.1/m, the self-inductance of 0.6pH/m and the mutual

Figure 3. Overall algorithm of the proposed test pattern generation

V. EXPERIMENTAL RESULTS
The proposed high-SI test generation method is validated

Figure 4. Slowdown delays of the proposed method and previous works

156
163

methodology to efficiently apply test vectors for the high-SI

fault model.

inductance of 0.4pH/m are considered. In addition, the

capacitance is 0.185fF/m and the coupling capacitance is
0.064fF/m. Interconnection length of 1000m is considered.
Using 8, 16 and 32 interconnection systems with randomly
generated interconnection topologies, running for 3mm in
parallel on metal layer 4, and in a 0.18 m process, we
demonstrated the efficiency of the high-SI test generation
with the interconnection topology graph. In addition, we
perform experiments for AHB and APB bus in our ARMbased Network Processor. Table 2 shows the defect coverage
percentages for the MA test patterns [4], MT test patterns [7]
and test patterns generated by the high-SI method with the
interconnection topology. As shown in Table 2, among the
three test vector sets, the high-SI test generation method with
the interconnection topology is the most efficient for all the
interconnect systems. In addition, the high-SI method
significantly reduces time to generate test patterns for signal
integrity faults than the SPICE-based pattern generation
method.

REFERENCES
[1]

[2]
[3]
[4]

[5]
[6]

[7]

TABLE 2. COMPARISON OF VARIOUS INTERCONNECT SYSTEMS

BUS
8bit (1)
8bit (2)
8bit (3)
16bit (1)
16bit (2)
16bit (3)
32bit (1)
32bit (2)
32bit (3)
AHB
APB

MA [4]
81%
84%
77%
72%
75%
81%
64%
72%
68%
54%
58%

MT [7]
86%
91%
84%
77%
75%
83%
80%
83%
75%
68%
65%

High-SI
96%
98%
93%
90%
87%
86%
91%
92%
90%
87%
91%

[8]
[9]
[10]
[11]
[12]
[13]

VI. CONCLUSION
To more accurately detect signal integrity defects on
practical on-chip interconnection lines and avoid time
consuming for interconnection analysis, in this paper, we
propose a new high-level signal integrity fault model to
estimate noise effects based on process variation and
interconnect signal transition. Especially, for signal integrityinduced delay errors, the proposed high-level fault models
are based on TWA (traveling wave based waveform
approximation) technique for multi-coupled interconnects.
The proposed high-SI test pattern generation is based on
the analysis of the impact of aggressor lines on signal
integrity effect at a victim line. We then presented a
methodology to deal with arbitrary interconnect topologies.
Using the interconnection topology graph and two factors,
the DFR and the ZFR, our methodology generates test vector
pairs to maximize the impact of aggressor lines.
Experimental results showed that the proposed high-SI test
patterns are more exact than the MA and the MT patterns and
the defect coverage is much higher since the MA fault model
leads to underestimation of signal integrity effects due to the
RC network and the MT patterns are randomly generated.
Currently, there is ongoing research to develop a BIST

[14]

[15]

[16]
[17]
[18]
[19]

157
164

A. Rubio, N. Itazaki, X. Xu and K. Kinoshita, An Approach to the

Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits,
IEEE Transactions on Computer Aided Design of Integrated Circuits
and Systems, Vol. 13, pp.387-395, 1994.
W. Chen, S. K. Gupta and M. A. Breuer, Analytic Models for
Crosstalk Delay and Pulse Analysis Under Non-Ideal Input,
Proceedings of International Test Conference, pp. 809-818, 1997.
K. T. Lee, C, Nordquist, J. A. Abraham, Test Generation for Crosstalk
Effects in VLSI Circuits, Proceedings of IEEE VLSI Test
Symposium, pp. 628-631, 1998.
M. Cuviello, S. Dey, X. Bai and Y. Zhao, Fault Modeling and
Simulation for Crosstalk in System-on-Chip Interconnects,
Proceedings of International Conference on Computer Aided Design,
pp. 297-303, 1999.
M. Nourani and A. Attarha, Built-In Self Test for Signal Integrity,
Proceedings of Design Automation Conference, pp.792-797, 2001.
W. Sirisaengtaksin and S. K. Gupta, Enhanced Crosstalk Fault Model
and Methodology to Generate Tests for Arbitrary Inter-core
Interconnect Topology, Proceedings of Asian Test Symposium, pp.
163-169, 2002.
M. H. Tehranipour, N. Ahmed, M. Nourani, Testing SoC
Interconnects for Signal Integrity using Extended JTAG Architecture,
IEEE Transactions on Computer Aided Design for Integrated Circuits
and Systems, vol. 23, pp. 800-811, 2004.
C. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and
Synthesis, John Wiley & Sons, 2000.
A. Attarha and M. Nourani, Test Pattern Generation for Signal
Integrity Faults on Long Interconnects, Proceedings of IEEE VLSI
Test Symposium, pp. 336-341. 2002.
S. Chun, Y. Kim and S. Kang, High-MDSI: A High-level Signal
Integrity Fault Test Pattern Generation Method for Interconnects,
Proceedings of IEEE Asian Test Symposium, pp. 115-120, 2007.
C. Cheng, J. Lillis, S. Lin and N. Chang, Interconnect Analysis and
Synthesis, John Wiley & Sons, 2000.
K. L. Shepard, Design Methodologies for Noise in Digital Integrated
Circuits, Proceedings of Design Automation Conference, pp. 94-99,
1998.
S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov and J. Zuo,
Driver Modeling Alignment for Worst Case Delay Noise,
Proceedings of Design Automation Conference, pp. 720-725, 2001.
Y. Eo, S. Shin, W. R. Eisenstadt and J. Shim, Generalized Traveling
Wave-Based Waveform Approximation Technique for the Efficient
Signal Integrity Verification of Multicoupled Transmission Line
System, IEEE Transactions on Computer Aided Design, vol. 21, pp.
1489-1497, 2002.
S. Shin, Y. Eo, W. R. Eisenstadt and J. Shim, Analytical Models and
Algorithms for the Efficient Signal Integrity Verification of
Inductance-Effect-Prominent
Multicoupled
VLSI
Circuit
Interconnects, IEEE Transactions on Very Large Scale Integration
Systems, vol. 12, pp. 395-407, 2004.
C. R. Paul, Analysis of Multiconductor Transmission Line, New York:
Oxford Univ. Press, 1998.
G. Miano and A. Maffucci, Transmission Lines and Lumped Circuits,
San Diego, CA, Academic, 2001.
H. B. Bakoglu, Circuits, Interconnects and Packaging for VLSI,
Reading, MA, Addison-Wesley, 1990.
HSPICE, v2003.03-SP1, Synopsys Corporation.