Proceedings of the 4th European Microwave Integrated Circuits Conference

Dynamic Power and Signal Integrity Analysis for

Chip-Package-Board Co-Design and Co-Simulation
Sidina Wane1, An-Yu Kuo2, and Patrick Dos Santos3
1

NXP-Semiconductors Campus-EffiScience, Caen France

sidina.wane@ieee.org

Apache Design Solutions, 2645 Zanker Road, San Jose, CA 95134 USA
aykuo@apache-da.com
3

Cadence Design Systems, Paris

patdoss@cadence.com

Abstract This paper presents global dynamic power and

signal integrity analysis methodologies for chip-package-board
co-design and co-simulation. The proposed methodologies are
based on efficient combination of power switching activity
macro-modeling with broadband multi-port model extractions.
Dedicated real-life test carriers are employed for benchmarking
purposes and correlation with on-wafer measurement. The
results from EM simulations are fed into circuit simulator
environment
(Cadence)
following
divide-and-conquer
segmentation approaches. Additionally, two different types of
current activity models are used to model the digital die. The
obtained simulation results are validated by comparison with
time-domain and frequency-domain measurement.

I. INTRODUCTION
In a complex system where analog and digital modules are
integrated together within the same package, power integrity
(PI) targeting at bounded supply voltage/current transient
fluctuations within acceptable margins and signal integrity (SI)
limiting noisy interferences from various electromagnetic (EM)
coupling phenomena represent very challenging constraints
for design success. It is important to address such constraints
at earlier design stage in order to avoid chip-package-board
debugging. All the constraints, physical design constraints as
well as electrical specification constraints, from chip level up
to board level must be taken into consideration in order to
guarantee the quality of the end product. This requires chippackage-board co-design environment that provides all the
equipment to do physical design as well as electrical
simulation.
Although single model EM integral analysis
of unified chip-package-board assembly design would be the
most accurate approach, this is not possible using existing
design tooling suites. The main reason is related to the very
high complexity resulting from the merging of IC level,
package level and board level specific database information
such as layout description, connectivity assignment, layers
stack definition, and etc. To render possible simultaneous
analysis of selected/identified complete paths across the
different integration levels (chip, package and even board),
one needs to use segmentation approaches. This means to
combine different simulation techniques (frequency-domain,
time-domain, and mixed-signal) with extraction models
(broadband equivalent circuit representations, digital activity
model derivation, transistor IPs for analogue blocks, and etc)
for system-level analysis. Such segmentation approaches are
based on divide-and-conquer techniques. Therefore, efficient

978-2-87487-012-5 2009 EuMA

hybridization of various simulation tools with different

assumptions (analytical/semi-analytical, quasi-static, and fullwave), thus different accuracy levels, is required. In order to
accurately model the higher order effects resulting from
discontinuities (bending, power-ground shapes, via-hole
transition connections, bond-wiring, bumps) in the analysis,
proper boundary conditions for each segmentation in
association with the appropriate accuracy assumptions need to
be defined. This is the motivating factor to develop design
guidelines and design rules.

(a)
DEC AP ( Port p)

Analog
ActiveDie

PMU
Analog
Passive
Die

AnalogPassiveDie
Port i

Package
Port j

PCB

(b)

SD 2
SD 3

BasebandDie
SMD

SD 1

Analog
Active
Die

PCB
Multi-port

Baseban
d Digital
Die

SD 4

SMD

(c)

Fig.1 Silicon-based System Level Integration taking advantage of third

dimension integration (e.g., high density trenched capacitors, vertical spiral
inductors, through-silicon-vias)., (a). Schematic view of the selected SiP(b)
test carrier for PI/SI analysis and associated test-bench multi-port system.(c).

In this paper, methodology for power and signal integrity

analysis in a packaged-system i.e. SiP, PoP, and SoC is
proposed. The system-in-package is distinguished into two
major parts, namely passive circuitry and active circuitry.
Quasi-static and full-wave EM solvers are employed to
analyse selected passive circuitries following the divide-andconquer segmentation approach. To model the digital die,
namely active circuitry, two approaches are taken. The first
approach takes a Norton equivalent model that uses triangular
current waveform under the assumption that all gates are
switching at the same time. The second approach uses the
CPM (chip-package model) produced by Apache Redhawk
tooling package which is based on statistical approach

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28 -29 September 2009, Rome, Italy

The co-design of multi-dies systems requires bringing a

unified model of the complete design domains (Chip, package
and board) into a common design environment in order to
perform global design optimisation through different
development iterations. Starting, from initial design
specification, at top-level electrical simulation of sub-blocks
or entire modules efficient synchronization with physical
model connectivity should be considered to properly handle
Engineering Change Order (ECO). Requirement of common
design environment where constraints from Chip level are
propagated to package-level and even to board-level results
from the necessity to facilitate bridging various design
domains (Analog, Digital and Mixed) that used to be driven
by different tools/flows. Classically such design domains are
tackled separately often without a single system-level view for
global simulation. To illustrate a single model system-level
PI/SI simulation a real-world NXP-Semiconductors Systemin-Package carrier designed using Cadence SiP solutions is
selected. Figure 1 shows an illustrative figure of the SiP
design consisting of three dies stacked on a multi-layered
package.
This product represents a very good example of a complex
system for power and signal integrity analysis. The dies
consist of analog/RF dies and digital die combining bondwire
and flip-chip technology. The digital die is represented by its
current activity. To model the current activity, we use Norton
equivalent model and CPM model which use triangular
current waveform and statistical-based current model
produced by Apache Redhawk, respectively as depicted in
Fig.2. Where as for the analog/RF dies, they can be
represented by the sensitive circuitries e.g. LNA (Low Noise
Amplifier) and the noisy circuitries e.g. VCO. Interconnects
connecting the dies to the package i.e. the RDL (redistribution
layer) and bondwires are analysed using quasi-static (Ansoft
Q3D) and full-wave EM solvers (Ansoft HFSS), respectively.
Next, we need to model the multi-layered package. Since the
package contains interconnects only which are passive devices,
we modelled the package by an equivalent circuit (RLC
network) produced by a quasi-static EM solver (Ansoft TPA).
Next, the board containing many SMD components is
modelled by an equivalent circuit produced by Ansoft SIwave.

Lastly, all the models are put together in a circuit simulator

e.g. Cadence Spectre to perform transient simulations.
II. SIMULATION RESULTS, DISCUSSIONS AND
BENCHMARKING
The proposed Chip-package-Board PI/SI Co-simulation
methodology combined two model extractions:
1) a passive network multi-port that includes all relevant
power/ground planes, interconnects, bond-wire
connections, RDL, traces.
2) a behavioral model of the digital baseband die
switching activity, the analog blocks being
represented by transistor level description or
equivalent model reductions.
The accuracy of the passive network model extraction
strongly depends on the used assumption: full-wave or quasistatic. Other important challenges concern partitioning of the
overall system into sub-blocks [1], grounding strategies as
how to properly define current return paths [1,2,3]. To model
the active dies, essential question is how to define a realistic
current switching activity profile. What is the impact of worstcase assumptions where all gates are assumed to be switching
at the same time? How to evaluate influence of decoupling
capacitors (on-chip and off-chip) on simultaneous switching
noise?
In Fig.2, benchmarking of various standard full-wave (3D and
2.5D) and quasi-static EDA commercial tools is presented for
the analysis of on-wafer dedicated test structures, in
comparison with measurement results.
4

Extracted Inductance (nH)

following both vectorless and VCD extraction modes. All the

blocks are then cascaded together in the circuit simulation
environment i.e. Cadence Spectre for time-domain and
frequency-domain simulations.
Dedicated test carriers structures are considered for
benchmarking purposes and correlation with on-wafer
measurement are discussed. The paper is organized as follows:
the second section details the flow methodology, the third
section being devoted to discussion on electromagnetic
extraction results and PI/SI simulation analysis. Influence of
on-die decoupling mechanism on voltage fluctuations known
as simultaneous switching noise (SSN) is discussed based
both on transient and AC investigations. Correlations between
obtained simulation results and real-world system-level
experimental results are discussed.

M easurem ent
A nsoft T P A
A nsoft Q 3D
A nsoft H FS S
O ptim al P akS i-E , return path w ith no shield
O ptim al O -W ave
O ptim al P akS i-E , return path w ith shield

3.5

2.5

1.809n H
2

1.5

1 8
10

10

10

10

F req u e ncy (H z)
Fig.2 Comparisons of Full-wave and Quasi-static inductance extraction with
on-chip Silicon Measurement (chip portion).

Satisfactory agreement between full-wave and quasi-static

assumptions is observed at low frequency with, however,
signification deviations at moderate and high frequencies.
Extracted RLCG parameters showed significant dependencies
of inductance and mutual inductance terms on ground return
path settings. In order to evaluate the impact of such
deviations on system level PI/SI, specifications of acceptable
margin tolerances for analog IP blocks are required. Such
specifications are not easy to derive since they are applicationdependent. This necessitates guidelines and design rules
derivations in order to determine frequency limits of quasistatic accuracy in reference to the aforementioned tolerances.

528

Triangular

signal input/out are evaluated in two configurations: with and

without 150: equivalent termination for the LNA input
impedance.

Vin
(mV)
Vout
(V)

CPM
M odel

T r ia n g u la r
M odel
T im e ( n S )
(b)

C PM M odel
(w te rm in a l)

T ria n g u la r
M o d e l(w te rm in a l)
T ria n g u la r
M o d e l (w /o te rm in a l)

Triangular+Trapezoidal

Peak value

C PM M odel
(w /o te rm in a l)

(V)
VinVin
(PV)

A. Effects of Digital Switching Activity on Power Supply and

RF Signal Integrity.
Extracted multi-port chip-package-board passive network is
combined with digital activity models to simulate system level
PI/SI both in time-domain (for SSN analysis) and frequencydomain (for transfer impedance analysis) simulation.
Concerning the time-domain simulations, Spice/Spectre
models are preferred to S-parameter based models to ensure
smoother convergence and better DC behavior. When Spice
model are not extracted natively, broadband Spice extractions
(BBS) are considered. A special attention should be paid to
passivity and power conservation to guarantee stability and
causality. Two use-models are investigated for the digital
baseband switching activity model: a simplified first-order
switching current activity profile defined by a
triangular/trapezoidal waveform, where the amplitude is
calculated to match the average power obtained from the
measurements. For this simple model the rise and fall times
are deduced from the technology-node information, relatively
to 90nm CMOS. A more complex digital activity model that
takes into account dynamic attributes through statistical
analysis is extracted using Apache Redhawk CPM solution. In
Fig.3(a) and In Fig.3(b) a representation of a triangular
waveform profile and a CPM multi-port model are shown
respectively.
Average value

Tr=500ps

T im e (n S )

Tr=500ps

Freq

(b)
Fig 4. Effects of Digital switching activity on Signal Integrity Analog die
access output (a) and input (b) voltage fluctuations.

Freq

(a)
Vdd1
V ss1
C u rre n t s ig n a tu re
re p re s e n te d a s
P W L s o u rc e s

Vdd2
V ss2
Vddk

C h ip
Pow er
D e liv e r y
N e tw o rk

V ssk

(b)
Fig 3. Classical triangular or combined triangular-trapezoidal waveform
profile for current activity profile (a) and CPM multi-port representation (b).

The CPM consists of a Piecewise Linear (PWL)

compression sources and a passive parasitic network
describing the digital on-chip delivery network. The influence
digital activity switching on power/ground bounces as well as
noise fluctuations at sensitive RF inputs (LNA access) of the
analog active die is studied. For the simulation of decoupling
capacitors impact on PI/SI, impedances in frequency-domain
analysis are calculated at different locations.
In Fig.4 typical time-domain voltage fluctuations of powersupply nodes and signal input/output voltages both for
triangular waveform activity profile and CPM model are
shown. Significant changes in the noise fluctuations are
observed, which demonstrate importance of proper activity
modeling for digital dies. Such fluctuations necessitate proper
estimation of on-chip decoupling capacitance to reduce SSN
impact on PI/SI. In Fig.4(b) the voltage fluctuations on RF

B. Influence of on-chip Decoupling Capacitors

The influence of decoupling capacitors on PI/SI is
investigated from system-level analysis where a global multiport impedance/admittance matrix is extracted. Two
fundamental metrics are considered: time-domain noise
fluctuation metric and impedance-based metric. Following the
global test-bench schematic given in Fig.1(c) an optimization
methodology based on iterative resolution is suggested. For
this the concept of transfer impedance is used to determine
the frequency domain characteristics (resonances for instance)
not easy to distinguish in time domain. The transfer
impedance from port j to port i is given by the voltage at
access i assuming a 1-A current source at access j. Lets
consider a model of on-chip decoupling capacitor (inserted at
port p in Fig.1(c)) described by equivalent impedance function
of ESR, ESL and ESC parameters given in equation (1).
1
(1)
Z p  f  ESR  j 2 S f u ESL 
j 2 S f u ESC
When [ZNO DECAP] designate the global multi-port impedance
matrix (with dimension determined by the total number of
port access) with no decoupling capacitors, an iterative
optimization analysis can be conducted to derive [ZWITH DECAP]
referring to the impedance matrix (seen from port j to port i)
after adding a decoupling capacitor located at port p:

529

predicted by the integrated model and the cascaded model are

very similar. But, dynamic IR-drop predicted by the cascaded
model is smaller than dynamic IR-drop predicted by the more
accurate integrated (global) model by 30mV (including RDL).

(a)

Fig.6- Dynamic IR-drop against time for VDD supply: comparison between
global methodology and cascaded/segregated approach (including RDL layer).

(b)

(c)
Fig 5. Illustration of decoupling capacitors effects on Power Integrity with
CPM model: (a), correlations of simulated results with measurements for
multi-wirebonding structures (b) and on-board TDR/TDT analysis (c).

ZWITH

i, j 

DECAP

ZNO

i, j  

DECAP

ZNO

i, p u ZNO DECAP p, j  (2)

ZNO DECAP p, p  Z p

DECAP

To meet particular system power integrity constraint a target

impedance is classically introduced which is given in (3) by a
ratio of supply voltage and switching current at a specified
port where K is the tolerance variation of the power supply
voltage:
(3)
t  K V dd
z
TARGET

I Switching

It should be underlined that such target impedance metrics

rely on pessimistic assumption since the impedance is not
really proportional to the noise fluctuations. This is partly
related to non-uniform current switching activity. Fig.5(a)
illustrates the influence of decoupling capacitors on analog
suppliers, ground fluctuations and RF input/output voltages.
In Fi.5(b) and Fig.5(c) both frequency-domain measurement
(VNA) and time-domain measurement (TDR/TDT)
conversions are compared in reference the RF-in and RF-out
access in the inset of Fig.5(c), validating the proposed
methodology. As shown in Fig.6, dynamic IR drop curves

III. CONCLUSION
In this paper a global Chip-package-board power integrity
and signal integrity methodology has been proposed and
applied to a real-world NXP SiP product. Hybrid approach
coupling quasi-static with full-wave analysis has been
investigated to extract SiP passive circuitry broadband models.
The obtained multi-port representations have been backannotated into a circuit simulation environment and then
combined with excitation sources, analog block IPs and digital
activity macro-models to determine SSN and power delivery
network frequency characteristics. Influences of triangular
waveform assumption and CPM approach have been
compared showing significant differences which demonstrate
importance of proper activity modeling for digital dies. A
methodology based on iterative process is applied to optimize
on-die/off-die decoupling capacitors. It is observed that
voltage noise metrics are more convenient than target
impedance based metrics in order to avoid excessive overdesign. The obtained simulation results are validated by
comparison with time-domain and frequency-domain
measurement.
ACKNOWLEDGMENT
The authors thank Saoer Sinaga, from Philips-Semiconductors, for
fruitful discussions and collaborative co-work on the test-bench
creation and simulation.

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