Signal-Power Integrity Co-Simulations of High

Speed Systems via Chip-Package-PCB Co-Analysis

Methodology
Wen Jiwei

Jing Weiping

Jiangsu Key Laboratory of ASIC Design, Nantong

University
No.9, Seyuan road
Nantong, Jiangsu, P.R. China, 226019
E-mail: wenjiwei1989@foxmail.com

Jiangsu Key Laboratory of ASIC Design, Nantong

University
No.9, Seyuan road
Nantong, Jiangsu, P.R. China, 226019
*E-mail: jing.wp@yahoo.cn

AbstractUnder the platform of a high-speed package system,

a modeling method considering all the signicant effects from the
chip, package, and board levels is developed to identify and
investigate the critical nets affecting the signal or power
integrity(SI/PI). For SI issues, accurate modelings for signal
channel are verified by system of high speed line. The following
what-if analyses help to identify the package traces bottlenecks
and have great effects on signal transmission. For PI part, the
modeling methodologies for power distribution networks of data
line are demonstrated and validated with the results of frequency
domain simulation. Lastly, with the co-simulations by chippackage-PCB model, the paper was talked about the SI and PI
problem using SI-PI co-analysis methodology. The analysis
results indicates that the parasitic effects of the high speed
package system are the most critical, depicting the importance of
improved package design in the next high speed package system.
Keywordssignal integrity; power integrity; power delivery
network; chip-package-PCB; co-simulation;

I.

INTRODUCTION

With the integration of integrated circuits continue to

improve and the signal rise time continue to decrease, the
signal transmission environment is constantly to deteriorate,
followed SI (Signal Integrity) and PI (Power Integrity) also
have to get people's attention in recent years. When the rise/fall
time of the I/O signal shorten to 100ps, the fast switch worked
at the same time will produce the SSN (Simultaneous
Switching Noise). The SSN noise makes the SI/PI problem,
such as crosstalk, reflect and influence the PDN (Power
Delivery Network). At the same time, getting lower and lower
supply voltage and noise tolerance makes PI issues become
more prominent. Therefore, SI / PI problem becomes cannot be
ignored and SI-PI co-simulation method in the assessment of
performance of the system becomes very important because
their mutual influence. In figure 1[1], the PDN system include
the on-chip PDN, the package PDN and the PCB PDN and
VRM(voltage regulator model), when we are studying the
performance of the PDN system, one kind of Chip-PackagePCB Co-analysis method is very necessary. A co-design
methodology used in the research SSN noise and the effect of
decoupling capacitor to the PDN system, through the signal
path, the signal transmission distance and PVT(process,

voltage and temperature)study, elaborated Chip-Package-PCB

co-analysis the feasibility of the method[2]. Another chippackage co-design method to study the mixed-signal circuit to
considering the impact of the package's on the overall system
performance to improving the accuracy and efficient of the
analysis[3][4]. Use of chip-package-PCB co-analysis method
to study the SI and PI problem of high-speed DDR3 system, by
modeling the command / address line, and a fly-by topology
method to analysis the command / address line of discontinuity
and SI problem; meanwhile, modeling of PDN and
comprehensive analysis of the data bus SSN [5].
In this paper, the chip, package and PCB PDN and
transmission lines were modeled, by the chip-package-PCB cosimulation method to co-analysis the SI, PI problem of the
high-speed package system. The second part of the paper
describes the transmission line model method and package
PDN model method based on the distributed circuit, and
modeling of PCB PDN based on the S-parameter extraction
method, and modeling the on-chip PDN based on SPICE netlist
AC analysis. The third part, we are study the split plane to
effect the SI problem and the PDN noise.

Fig. 1.

The component parts of the PDN[1]

II.

MODELING AND VERIFY OF SI/PI

A. Modeling of package/PCB substrate transmission line

In this section, Modeling Package/PCB substrate signal line
were introduced, and most of the physical structure of the
signal line is the same, so here only described two adjacent
signal line modeling method. Distributed parameter circuit
model of a single transmission line can be obtained by the
wave equation of the transmission line [6]. As shown in figure

1. Industry-Academia-Research collaborative innovation projects in Nantong

city (BC2012012)
2. The Graduate technological innovation projects in Nantong University
YKC12067

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485

2(a), according to the coupling of the signal lines and the return
path of the physical structure of the transmission line, the
signal, ground structure of the T-type equivalent circuit model
can be obtained. The T-type equivalent circuit model is
considering the coupling between the transmission line and the
transmission line, the transmission line and the return path.

C1g and C 2g represent the capacitances of the one signal line

and the other signal line with respect to ground trace. Cm is
the mutual capacitance between the two signal traces. Also L11 ,
L 22 , and Lg are dened as the self partial inductances of the
two signal trace and the ground trace, respectively. In order to
improve the accuracy of high frequency, the cascade T-type
equivalent model was adopted. As shown in figure 2(b), the Ttype equivalent model was cascade N parts (N t 2).

a.

layout physical structure

b.

equivalent T model

Fig. 2.

Fig. 3.

Results of physical structure and LC equivalent model

B. Modeling of PDN
This section explains the PDN modeling methods for timedomain simulation. Chip, package, PCBs PDN equivalent
circuit modeling method are different. Firstly, for the package
PDN modeling, we use the model method based on the
distributed circuit as described in the first part of a transmission
line modeling method, and the package substrate of the PDN
network was modeled RLC circuit too. And the Cadence
XtractIM/Ansys Q3D based on the finite element method is
used to extract the equivalent model of package with resister
and inductance and capacitance. Also the equivalent model was
verified frequency domain simulation tool Cadence PowerSI
and time domain simulation tool Ansys Designer respectively.
As shown in figure 4, the two PDN model Z parameter curves
fit well from 0Hz to 3GHz.

Package/PCB layout physical structure and T equivalent model

In order to verify the equivalent model, two simulation

model were built in the 3-D frequency domain electromagnetic
simulator Ansys HFSS and the 2-D time domain electromagnetic simulator Ansys designer environment like figure 2
shown. By setting the simulation parameters correctly in the
soft environment, the S-parameters of the two models were
simulated with frequency from 0Hz to 2.5GHz respectively.
According to simulated S-parameters of the physical layout
structure and equivalent T-type model, and compared with the
result directly from physical layout model and equivalent Ttype model, the comparison results are shown in figure 3. As
we can see, the two simulation models curves fit very well. It
can be proved that the equivalent T-type model is correct.

Fig. 4.

The two PDN model simulation curves

For the PCB PDN model, we are use the S-parameter

model to replace the power delivery network in the time
domain simulations. In figure 5, the PCB PDN simulation Z
parameter curve was provided. Also other model method, the
macro model methodology, for frequency domain simulation
model to time domain simulation model is effective [7][8]. The
basic idea is to sampling the frequency into the frequency
domain and use the rational function approximation method
converted frequency domain model into time domain passive
macro model, and this model is commonly used in timedomain simulation tools support.

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taking into account the coupling between the power-to-signal,

and also take into account the power collapse impact to driver
and receiver. This section will discuss the SI/PI problem and
SI-PI co-analysis issues based on chip-package-PCB cosimulation method.

Fig. 5.

The PCB PDN model simulation curves

A. Noise Coupling Mechanisms Analysis with Reference

Plane
Because of electromagnetic coupling, when the signal was
transmitted on transmission line, the noise voltage signal which
was coupling the other signal line.

Finally, the On-chip PDN was modeled relatively simple

RC circuit network instead [9], is method can be greatly reduce

simulation time. Wherein Rdie Cdie is obtained to AC

analyzed through chip SPICE netlist, and then manually

calculate Rdie Cdie the amplitude and phase. Figure 6 shows

the RC circuit which phase-frequency response and amplitudefrequency response are fit well with amplifier chip spice netlist
analysis. Even RC circuit model to modeling the on chip PDN
that the simulation accuracy is not high, because of its simple
circuit model and simple method of calculating, and the RC
circuit simulation was not need much memory, so it has good
application on the model on Chip PDN.

The coupling microstrip line with reference plane

Equivalent circuit model

Fig. 7.

The circuit model for crosstalk analysis

As figure 7 shows, the symmetrical coupling line which has

the reference power/ground plane, and the equivalent T circuit
a

Phase-frequency response

Amplitude-frequency response

Fig. 6.

The phase-frequency response and amplitude-frequency response

III.

ANALYSIS AND SIMULATION

that the line length are less than the wavelength of signal. Cm

and C 0 represent the capacitances of the aggressor signal line

with respect to ground trace and the victim signal line.

Also Lw and Lm are dened as the self partial inductances of

the two signal trace and the mutual capacitance between the
two signal traces, respectively. The signal line between node 1
and node 2 was called aggressor line, the signal line between
node 3 and node 4 was called victim line. The crosstalk was
main cause the capacitive coupling and inductive coupling
between the two signal lines.
In practical designs, the capacitive coupling and inductive
coupling are occurred simultaneous. Lets talked the far end
crosstalk, the far-end crosstalk are defined as the far end peak
noise voltage and the signal voltage ratio:

SI / PI problem becomes more and more important in the

high-speed system, but the traditional SI / PI analysis often
consider the impact alone. As for modeling, simulation and
analysis of SI problem, assuming power and ground networks
are ideal only analysis signal nets. Similarly modeling and
simulation analysis of PI problem often overlooked power to
effect the signal net and signal return path and consider a single
model of the power / ground networks only, such as SSN,
ground bounce. SI-PI co-analysis method not only takes into
account the coupling between the signal-to-signal, but also

FEXT= Vf / Va
If supposed the weak coupling, we can got

VFE VFEcap  VFEind

So when the coupling length is l , the

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VFEXT VFE / Vo

Z 0CmlV 0  LmlVo
2tr
2Zotr
Vo

Z 0Cm Lm
Zo l
2tr

And the transient capacitive coupling current in the victim

line is

Ic

Cmvtr Vtro CmvVo

The transient inductive coupling voltage is

VL

I
Lmvtr
tr

Fig. 8.

The far-end crosstalk and near-end crosstalk

Fig. 9.

The eye diagram of with/-out crosstalk

LmvI

Combine with the current of Signal Propagate

CLvVo

and voltage of Signal Propagate

LLvI

We can get the;

VFEXT

VFE / Vo

l 1 Cm L m


vtr 2 CL LL

l
vtr and tr are dened as the noise voltage superposition and
signal rise time. Q is speed of Signal Propagate. Cm and CL
represent the mutual capacitances per unit length between the
two signal traces and the capacitances per unit length of the

signal line. Also Lm and LL are dened as the mutual

capacitance per unit length between the two signal traces and
he self partial inductances of the signal trace, respectively.
For consider of the aggressor line to effect the victim line
only (supposed only one signal was propagate), as shown
figure 8, the far-end crosstalk and the near-end crosstalk
waveform in time-domain and the |S31| and |S41| was observed
in frequency-domain. But in practical design, it has multisignal was propagated, it will produce the other problem like as
inter symbol interference (ISI) etc. Figure 9 shows the eye
diagrams of the received signal with the data rate of 800Mbps,
with and without crosstalk. For the case with the crosstalk, the

27  1 and 215  1 PRBS signals are applied to the aggressor

line and the victim line, respectively. For the case without

crosstalk, a 2  1 PRBS signal is applied to the victim line

only, with the aggressor line left terminated at both ends. As
figure 9 shows, without crosstalk, only the ISI effect is
observed. With the crosstalk both the ISI and crosstalk effects
are observed.
15

B. The Signal Propagate Analysis

In order to supply different required voltage levels or
provide isolation among digital or analog regions, it is
common to split/slot power/ground planes into islands, area
fills, or plane portions in practical high speed package systems
designs. Consequently, it may be inevitable to route signal
traces crossing a split in high density interconnect package
system. As a well-known EMC rule, the traces crossing the
imperfect power/ground plane of the PDN could potentially
cause signal integrity and EMI consequences. From the signal
integrity point of view, the crosstalk among signal trace
crossing a split is non-negligible, even though the space of the
trace is large enough. Also the small amount noise added to
the power supply may cause system breakdown due to low
voltage source is preferred to minimize package system power
consumption [10][11]. AS is well-know, power and the
ground plane are the important element of the PDN. In this
paper, we are study the relationship of the split plane and the
signal propagate. Figure 10 shows the test structure was built
which helps to investigate the effects to the signal in both the
frequency- and time- domain. As shown figure 10, the test
structure model was built, the model include two strip line
and two ground plane and one power plane in the middle of
the ground plane, and the power plane was split two parts.

Top view

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Cross view

Fig. 10.

The test structure [12]

Plane is a large metal structure which is separated by a thin

dielectric material; it is the important part of the package and
PCB system. The plane are play an important role especially
in high frequency field, it is shows the high frequency
capacitor, not only play the conductor to transport the current,
but also as the return path of the signal which are reference the
plane. Also in high frequency, the planes are used to power
distribution and Electromagnetic Shielding in package and
PCB system. The plane impedance is effect the PDN
impedance based on the physical structure and system factors.
As the return path, the return current are through the plane will
encounter the plane impedance and will generation the voltage
drop which called ground bounce. The voltage drop are
dependent the impedance of return path, the impedance are
arise, the voltage drop are larger and the ground bounce will
be larger. Figure 11 shows the relationship between the PDN
impedance and the signal return loss and insert loss in
frequency-domain. In order to provide a low-impedance return
path and decrease the voltage drop and effects, we can
decrease the space of the plane or add the some decoupling
capacitor to provide a low-impedance return path. Figure 12
shows the large PDN impedance will increase the far-end
crosstalk |S41| and near-end crosstalk |S31| in frequencydomain.

Fig. 12.

Impact of Characteristic Impedance on S31 and S41

Similarly, the levels of return path discontinuities will

great effect the signal propagates. As shown figure 10, the
split plane will lead to the return path discontinuities. In this
paper, we are study the relationship between the split width
and the signal propagate. we can clearly to obtain the signal
propagate and the split width has the direct relationship from
figure 13 shows. The large split width will lead to insert loss
decrease and return loss increase, which agrees with our
intuition. It will lead to more signal will loss in propagate.
Also it is easy to found that the crosstalk between the two
stripline traces is a function of the split width, which agrees
with our intuition too. Figure 14 shows the |S31| and |S41|
results in the frequency domain, which represent the near-end
crosstalk (NEXT) and far-end crosstalk (FEXT). We can
clearly observe from figure 13 and 14, the trend in the figure
where split width is changed 5mil, 10mil, 20mil, 40mil to
60mil respectively.
Lastly, we are study the different between the ideal
power/ground plane and split plane effects to signal propagate.
The received signal with the data rate of 800Mbps and a

215  1 PRBS signal are applied to the victim line alone, with

the aggressor line left terminated at both ends. As shown in

figure 15, it is clearly to observe the split plane caused a
overshot and the heye are closed than the ideal plane eye
diagram.

Fig. 11.

Impact of Characteristic Impedance on S11 and S21

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C. The PDN noise simulation

Ideally, a continuous and stable supply voltage is provided
to the circuits on the chip. In reality, the supply voltage is
transmitted through of the not ideal PDN in the PCB, the
package, and on the silicon chip, and each of these elements
adds impedance to the supply path that will cause voltage noise
dependent on the current dissipation of the circuits
As mentioned, power supply network is not ideal. Also
PDN will have they own noise which is mainly due to the large
number of simultaneous switch in the chip. The Chip-PackagePCB co-analysis can be better reflecting the PDN network
noise. As shown in figure 16, the test structure was builted
which include the voltage regulator module (VRM), the onchip PDN, the package/PCB PDN and the transmission model.
Simulation of the signal path to analyze the power network
noise with on-chip PDN, as shown figure 17, the drive end of
the noise is 2.6948v ~ 1.1092v, the noise of the receiving end
for 1.9419v ~ 1.6077v.

Fig. 13.

Impact of Split Width on S11 and S21

The Test Model

The PDN Model[13]

Fig. 16.

Fig. 14.

The Driver-end Noise

The Receiver-end Noise

Impact of Split Width on S31 and S41

Fig. 17.
Fig. 15.

The PDN Noise Measurement Structure

The Power Noise with On-chip PDN

The eye diagram of split/ideal plane

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Designing a high-quality PDN system in a high speed

package system is become very important. As shown in figure
18, the measured eye diagram of the receiver end for two cases.
An 800Mbps PRBS signal with 1.5V. A power noise model
and ideal power are applied to the two different cases,
respectively. The results are obviously, the eye diagram with
ideal power which have a good eye height and signal, and with
the power noise model, the eye diagram are confused and
distorted. Also, consider of crosstalk and power noise as the
same time, the eye diagram with crosstalk and power noise
simulation result shown in figure 19. Clearly, it is a bad eye
diagram: the jitter and ISI are serious effect the signal
propagates.

This paper discussed the molding the transmission line and

package PDN to RLC circuit, and molding the PCB PDN to Sparameter, molding the on-chip PDN to RC circuit based on
the SPICE AC analysis. To do some preliminary discussed to
the SI-PI co-analysis based on the Chip-Package-PCB cosimulation method, further confirmation of the importance of
the issue of SI / PI analysis based on the co-simulation method
for chip-package-PCB.
REFERENCES
[1]

[2]

[3]

[4]

Fig. 18.

Eye Diagram of the Power noise effect

[5]

[6]
[7]

[8]
Fig. 19.

Eye Diagram of both Crosstalk and Power noise effect

IV.

[9]

CONCLUSIONS

Through the SI-PI co-analysis, we can get some

information: take no account of their mutual influence to
analyze SI / PI problem alone, tend to get larger error results,
especially the frequency of the clock in a continuous increase,
the error will be even large. Thus contributing to a growing
number of people is concerned about the co-simulation analysis.
Of course, the appropriate model for the co-analysis of the SIPI analysis is very necessary. For SI, the modeling of the
transmission line and the driver /receiver modeling and signal
transmission environment modeling to SI simulation are
essential and have a great impact. For PI simulation, some
PDN model is crucial for analyze power noise. So SI-PI coanalysis based on the chip-package-PCB is accurate and
efficient method.

[10]

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